Ripple Counter
Synchr onous Binar y Count er s
Design with D Flip- Flops
Design with J- K Flip- Flops
Serial Vs. Parallel Counters
Up- down Binary Counter
Binar y Count er wit h Par allel Load
BCD Count er , Ar bit r ar y sequence Count er s
A count er is a register that goes through a
pr edet er mined sequence of st at es upon t he
application of clock pulses.
Counters are categorized as:
Ripple Counters:
The FF output transition serves as a source for
triggering other FFs. No common clock.
Synchronous Counter:
All FFs r eceive t he common clock pulse, and t he
change of state is determined from the present
state.
Less Significant
Bit output is Clock
for Next Significant Bit!
(Clock is negative edge)
Recall...
The out put of each FF is connect ed t o t he
C input of t he next FF in sequence.
The FF holding t he least signif icant bit
r eceives t he incoming clock pulses.
The J and K input s of all FFs ar e connect ed
to a permanent logic 1.
The bubble next t o t he C label indicat es
t hat t he FFs r espond t o t he negat ive- going
transition of the input.
Operation:
The least significant bit (Q0 ) is
complemented with each
negative- edge clock pulse input.
Every time that Q0 goes from 1
to 0, Q1 is complemented.
Every time that Q1 goes from 1
to 0, Q2 is complemented.
Every time that Q2 goes from 1
to 0, Q3 is complemented, and so
on.
Change edge- triggering to positive
Connect t he complement out put of each FF
to the C input of the next FF in the
sequence (homewor k!)
The design pr ocedur e f or a binar y count er is
t he same as any ot her synchr onous sequent ial
circuit.
The pr imar y input s of t he cir cuit ar e t he CLK
and any cont r ol signals (EN, Load, et c).
The pr imar y out put s ar e t he FF out put s
(present state).
Most ef f icient implement at ions usually use T -
FFs or JK- FFs. We will examine J K and D f lip-
flop designs.
Synchronous Binary Count ers:
J -K Flip Flop Design of a 4-bit Binary Up Counter
Synchronous Binary Count ers:
J -K Flip Flop Design of a Binar y Up Count er (cont .)
Synchronous Binary Count ers:
J -K Flip Flop Design of a Binar y Up Count er (cont .)
Synchronous Binary Count ers:
J -K Flip Flop Design of a Binar y Up Count er (cont .)
Synchronous Binary Count ers:
J -K Flip Flop Design of a Binar y Up Count er (cont .)
logic 1 J Q0 J Q0 = 1
C
KQ0 = 1
K
J Q1 = Q0
J Q1
KQ1 = Q0
C
K
J Q2 J Q2 = Q0 Q 1
C KQ2 = Q0 Q 1
K
J Q3 J Q3 = Q0 Q 1 Q 2
C KQ3 = Q0 Q 1 Q 2
K
CLK
Synchronous Binary Count ers:
J -K Flip Flop Design of a Binar y Up Count er wit h EN and CO
EN = enable control
signal, when 0 counter
remains in the same
state, when 1 it counts
CO = carry output signal,
used to extend the
counter to more stages
J Q0 = 1 · EN
KQ0 = 1 · EN
J Q1 = Q0 · EN
KQ1 = Q0 · EN
J Q2 = Q0 Q 1 · EN
KQ2 = Q0 Q 1 · EN
J Q3 = Q0 Q 1 Q 2 · EN
KQ3 = Q0 Q 1 Q 2 · EN
C0 = Q0 Q 1 Q 2 Q 3 · EN
If serial gat ing (chain of gat es, inf o r ipples
through) is used
serial counter
I f ser ial gat ing is r eplaced wit h parallel
gat ing (t his is analogous wit h r ipple- logic
replaced with carry- look ahead logic in our
adder designs)
parallel counter
Advant age of par allel over ser ial count er :
faster in certain occasions (1111 0000)
clock Q0
n-bit
Up-Down Q1
UD Counter
Qn-1
UD = 0: count up
UD = 1: count down
UD Q2 Q1 Q0 Q2.D Q1.D Q0.D UD Q2 Q1 Q0 Q2.D Q1.D Q0.D
0 0 0 0 0 0 1 1 0 0 0 1 1 1
0 0 0 1 0 1 0 1 0 0 1 0 0 0
0 0 1 0 0 1 1 1 0 1 0 0 0 1
0 0 1 1 1 0 0 1 0 1 1 0 1 0
0 1 0 0 1 0 1 1 1 0 0 0 1 1
0 1 0 1 1 1 0 1 1 0 1 1 0 0
0 1 1 0 1 1 1 1 1 1 0 1 0 1
0 1 1 1 0 0 0 1 1 1 1 1 1 0
Up-Counter Down-Counter
Q1 Q0
UD Q2 00 01 11 10
00
01
11
10
Fill-in the Karnaugh maps f or Q2.D, Q1.D, and Q0.D,
simplif y, and der ive t he logic diagr am using
(a) D-FFs and (b) T-FFs
Load Count Operation
0 0 Nothing
0 1 Count
1 x Load
The binary counter
with parallel load can
be converted into a
synchronous BCD
counter by
connecting an
external AND gate
to it.
The counter starts with an all- zero output.
As long as t he out put of t he AND gat e is 0, each
positive clock pulse transition increments the counter
by one.
When t he out put r eaches t he count of 1001, bot h Q 0
and Q3 become 1, making t he out put of t he AND gat e
equal t o 1. This condit ion makes Load act ive, so on t he
next clock transition, the counter does not count, but
is loaded from its four inputs.
The value loaded then is 0000.
Given an ar bit r ar y sequence, design a count er
that will generate this sequence.
Procedure:
Der ive st at e t able/ diagr am based on given sequence
Simplify (using K- maps, etc)
Draw logic diagram
Example: Use JK- FFs to draw the logic
diagr am f or sequence gener at or (count er ) f or :
0 1 2 4 5 6 0
RING COUNTER
JOHNSON COUNTER/
SWI T CH T A I L COU N T ER/
T WI ST ED RI N G COU N T ER
