COMP0068 Computer Architecture and Operating

Systems
Lecture 6: MIPS Processor

Background Reading:
Harris & Harris, Chapter 6.
Patterson & Hennessey, Chapter 2.
Overview of this Lecture

• The previous lecture examined a number of key concepts

about fixed size binary numbers (signed/unsigned,
big/little-endian, sign/zero-extension etc.). These concepts
will be important when discussing different aspects of the
MIPS Instruction Set Architecture (ISA).

• In this lecture we will first introduce the MIPS32 processor

and where it fits into the architecture of a computer.

• We will then go into more detail about what instructions are

present within the MIPS32 ISA, how these instructions are
encoded in terms of “machine language” and what they do
in terms of semantics (their meaning).
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Overview of MIPS Processors
• There are two main MIPS processor architectures today:
– MIPS32 – a 32-bit design which we will examine.
– MIPS64 – a 64-bit processor design with a similar architecture.

• MIPS was one of the first RISC (Reduced Instruction Set

Computer) based design, compared to Intel’s CISC
(Complex Instruction Set Computer) designs.

• MIPS chips are everywhere, with around half a billion

produced each year, and embedded in games consoles,
DVD equipment, laser printers, internet routers, ...

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R3000 Processor (MIPS32)
Released:1988 Transistor count: 110,000
Used in high-end workstations (e.g. Silicon Graphics SGI Personal IRIS 4D/20)

This processor was used to render 3D scenes in 90s movies like

Jurassic Park or Terminator 2 and more recently a radiation hardened
version of the R3000 flew to Pluto.

Radiation hardened Mongoose-V

version of the R3000 processor used in
Silicon chip view of
the New Horizon space probe to Pluto.
the R3000 processor
MIPS Evolution

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The Imaginations Creative Ci40 single board
computer - like a Raspberry Pi but with a MIPS32
processor

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A Processors’ (or Programmers’) Abstract
View of a Computer Peripherals
Data Bus (Input/Output
Devices)
Address Bus

Control & Status Bus

INPUT/OUTPUT
CPU MEMORY
INTERFACES

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R3000 Processor (MIPS32)
• MIPS addresses are 32 bits long Ø thus PC holds 32 bits

• MIPS instructions are 32 bits long

• In MIPS a single memory Ø thus an instruction must be

location holds one byte held in 4 consecutive
memory locations

MEMORY
0040001C
00400018
00400014
00400010 Instruction
0040000C
00400008
00400004
PC: 00400010 00400000
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 Arithmetic and Registers

$0 0 0 0 0 0 0 0 0
• MIPS – 32 registers ($0 to $31)
$1 0 0 0 0 0 0 1 4 – Arithmetic only allowed on data read
$2 0 0 4 F 2 0 0 3 from registers
…

– RISC based “load and store”

$31 F F F F F F F E architecture (only load and store
instructions access memory – all other
PC 0 0 0 0 0 0 1 4
instructions access registers only)

• To add two numbers in memory requires 4 instructions

1) “load” register ç memory
2) “load” register ç memory
3) “add” register ç register + register
4) “store” register è memory

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MIPS Instructions
• MIPS has 3 instruction formats:
ØR-type - Register operands – all arithmetic
ØI-type - Immediate operands – load, store, some branches
(operand value immediately available in instruction)
ØJ-type - Jump operands – other branches

• Examples of R-type instructions:

add $8, $1, $2 $8 ç $1 + $2
sub $12, $6, $3 $12 ç $6 - $3

• Register 0 ($0) always contains zero

add $8, $0, $0 $8 ç 0 + 0 # clear register $8
add $8, $1, $0 $8 ç $1 + 0 # copy $1 to $8
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R-Type Instruction Encoding
• Represented as:

op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op = operation or type of the instruction

rs = first register argument (source)
rt = second register argument (source)
rd = result of the operation (destination)
shamt = shift amount (ignore at present)
funct = particular type of the operation

If op = 0 and funct = 32 then add

If op = 0 and funct = 34 then sub 11
R-Type Instruction Layout

add $8, $1, $2 # Assembly language comment

# uses hash or sharp symbol.

op rs rt rd shamt funct
6-bits 5-bits 5-bits 5-bits 5-bits 6-bits

000000 00001 00010 01000 00000 100000

0 1 2 8 0 0x20
$1 $2 $8 0 add
è 000000|00001|00010|01000|00000|100000
Machine code that is written into main memory
and directly controls the MIPS processor. 12
R-Type Instructions - Examples
e.g. add $8, $1, $2
op rs rt rd shamt funct
000000 00001 00010 01000 00000 100000
0 1 2 8 0 0x20
$1 $2 $8 0 add
è 00000000001000100100000000100000

e.g. sub $12, $6, $3

op rs rt rd shamt funct
000000 00110 00011 01100 00000 100010
0 6 3 12 0 0x22
$6 $3 $12 0 sub
è 00000000110000110110000000100010 13
Program Example
x = a - b + c - d; High level Language

sub $10, $4, $5

sub $11, $6, $7 Assembly
add $12, $10, $11

Instruction Fields
0 4 5 10 0 0x22
0 6 7 11 0 0x22
0 10 11 12 0 0x20
Machine Code
Machine
000000 00100 00101 01010 00000 100010
000000 00110 00111 01011 00000 100010
000000 01010 01011 01100 00000 100000 14
 Examples of R-Type Instructions

Instruction op funct Description

(Base 16)
add 0 0x20 Addition – with overflow
addu 0 0x21 Addition – without overflow
sub 0 0x22 Subtraction – with overflow
subu 0 0x23 Subtraction – without overflow
and 0 0x24 Logical And
or 0 0x25 Logical Or
xor 0 0x26 Logical Xor
nor 0 0x27 Logical Nor
slt 0 0x2A Set on less than
sltu 0 0x2B Set on less than unsigned
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The key difference between add and addu
(and also sub and subu)

• addu stands for add unsigned – otherwise add is

assumed to be working with 2’s complement signed
numbers.

– But we know the exactly the same (hardware calculation) is used

for adding both unsigned or 2’s complement signed numbers … so
why have different instructions?

• The real difference is that the signed add “throws an

interrupt (or exception)” whenever overflow occurs for
the signed operation.
• Whereas the addu operation just ignores overflow. 16
The bitwise logical operations:
and, or, xor & nor

A B A and B
0 0 0 “and” Truth Table
0 1 0
and $3, $1, $2
1 0 0
1 1 1

00000001111000001111111111111111 … Register $1
00000111100000000000111111111111 … Register $2

00000001100000000000111111111111 … Register $3
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The bitwise logical operations:
and, or, xor & nor
Truth Tables of the other logical operations
(where True is represented by 1 and False by 0)

A B A and B A or B A xor B A nor B

0 0 0 0 0 1
0 1 0 1 1 0
1 0 0 1 1 0
1 1 1 1 0 0

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The I-Type Instruction Format
op rs rt offset
6-bits 5-bits 5-bits 16-bits

In a similar manner to the R-Type format, rs and rt refer to registers.

Offset may be a 16-bit signed value: -215 <= offset <= 215-1
or a 16-bit unsigned value: 0 <= offset <= 216-1
depending on the instruction.

The offset is extended to 32-bits before use: with sign extension

for signed values and zero extension for unsigned.
I-Type Format is used by:
• memory access instructions (Load & Store)
• instructions that require a constant value (addi, andi, lui),
• branch instructions
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I-Type Instruction Example – Load Word

op rs rt offset
6-bits 5-bits 5-bits 16-bits

lw $20, 0x1234($5) # This is a Load Word Assembly

# Instruction (32-bit memory address)

0x23 510 2010 0x1234

100011 00101 10100 0001001000110100
Machine Code
10001100101101000001001000110100

Mem[$5 + 0x00001234] à $20 20

I-Type Instruction Example – Store Word

op rs rt offset
6-bits 5-bits 5-bits 16-bits

sw $8, 0x8000($15) # This is a Store Word Assembly

# Instruction (32-bit memory address)

0x2B 1510 810 0x8000

101011 01111 01000 1000000000000000

Machine Code
10101101111010001000000000000000
$8 àMem[$15 + 0xFFFF8000] 21
I-Type (Immediate Value Instructions)

op rs rt Immediate Value
6-bits 5-bits 5-bits 16-bits

addi $20, $5, 0xABCD # This is a signed add immediate.

001000 00101 10100 1010101111001101

$5 + 0xFFFFABCD à $20

addiu $20, $5, 0xABCD # This is an unsigned add immediate.

001001 00101 10100 1010101111001101

$5 + 0xFFFFABCD à $20
WHY ? 22
 I-Type (Branch Instructions)

op rs rt constant
6-bits 5-bits 5-bits 16-bits

beq $20, $5, 0xABCD # Branch on register $20 equal $5.

0x4 2010 510 0xABCD

000100 10100 00101 1010101111001101
If ($20 == $5)
PC ß PC+ 4 + 0xFFFFABCD * 4
Similarly there is a bgez instruction (branch on greater than or equal to zero).
Offset is number of INSTRUCTIONS to branch over, starting from the
instruction following the branch ! 23
I-Type (Loading Addresses into Registers)
op rs rt constant
lui $17, 0x1234 # Load upper immediate.

0xf 010 1710 0x1234

001111 00000 10001 0001001000110100
$17 ß 0x12340000
ori $17, $17, 0x5678 # Logical OR immediate.

0xd 1710 1710 0x5678

001101 10001 10001 0101011001111000
$17 ß $17 | 0x00005678
The result of these two instructions is: $17 ß 0x12345678
The pseudo-instruction ‘la’ (load address) does the same ! 24
Download MARS (link on Moodle) and try this
example assembly program
# Calculator Version 0.0
.data
vals: .word 4, 5, 8, 0
.text
.globl main
main:
la $4, vals # Load $4 with the address of label 'vals'.
add $8, $0, $0 # Set sum to zero
lw $9, 0($4) # Get first number from memory
add $8, $8, $9 # Add to sum
lw $9, 4($4) # Get second number from memory
add $8, $8, $9 # Add to sum
lw $9, 8($4) # Get third number from memory
add $8, $8, $9 # Add to sum
sw $8, 12($4) # Save the result to memory.
li $v0 10 # System call code for exit = 10
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syscall # syscall 10 (exit)
Summary
• We reviewed the overall computer architecture in terms of
CPU, bus, memory and Input/Output.
• Background on MIPS processor:
– R-type instructions.
– I-type instructions.
• Simple example of MIPS assembly language.
• In the next lecture we will look at more details of MIPS
assembly language programs.
• Further reading:
Harris & Harris, Chapter 6.
Patterson & Hennessey, Chapter 2.

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