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Korg X5 Service Manual

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Mateusz Adamowski
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855 views39 pages

Korg X5 Service Manual

Uploaded by

Mateusz Adamowski
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
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SERVICE MANUAL MUSIC SYNTHESIZER CONTENTS 1. SPECIFICATIONS. 2. FULL VIEW... 3. DISASSEMBLY .. 4. BLOCK DIAGRAM 5. CIRCUIT DIAGR) 8. P.C. BOARDS. 7. TEST MODE .... 8. REFERENCE DATA 9. WAVE ROM SOUT 10. PARTS LIST...... (INSERTION) 1. SPECIFICATIONS ‘Tone generation method : AI square synthesis system ( fall digital processing ) ‘Tone generator : 32 voices 32 oscillators ( Single Mode ) 16 voices 32 oscillators ( Double Mode ) Keyboard : 61 key with aftertouch sensitive TP-7BA Waveform memory 16 Mbit Mask ROM x 3 ( 6 Mbyte ) 340 MULTT sounds 164 DRUM sounds Quantization + 16 bit, 12 bit and 8 bit ‘Sampling frequency 2 31.25kHz Programs RAM ; 100 programs ROM ; 128 programs + 8 drum set programs ( for GM ) Combinations : RAM ; 100 combinations Effects 47 muti digital effects Arrangements 64 arrangements Demonstration song 1 song Control inputs Assignable pedal, Assignable switch Outputs LIMONO, R (output impedance: 1.1kQ residual noise Jess than -904Bm ) PHONES (output impedance: 100) MIDI 1N, OUT, THRU TO HOST Mini DIN Spin ( 31.25 KBPS, 38.4 KBPS ) Display 16 x 2 LCD with LED back light Dimensions 900(W) x 254.2(D) x 83.4¢H)mm Weight 47g Power consumption 12 700mA, * Specifications and design are subject to change without notice for the purpose of product enhancement, W=900 mm D=254.2 mm 7 fi ati H= 83.4 mm Weight=4.5 Kg Seo . 61000: 000 7 x2 (x2 r ve Vue Pe g i w 900 D1] flew seticnvees 1 iiineteiney | ‘O ine) BE Hl | =| MalA TINA *Z 1 Remove the Lower Case 2. Remove the Mala Bosrd(KLM.950) 1} Reaibve al the eres onthe lowercase 1) Unplug all" the haracttes and Spee. of che screws and carefully Ut the case ‘oa the. mainboard [BT BBZNC4x 10)" x9 Ofan:@) {tir wzatc 338) xs (Mark: A) 7 [Tre BzMc 3x14) X10 (Mare D [RED BzMc 3x8} Xi (Mar: $) [BT BZMC 3312) %2 (Merk: %) 2) Remove the main board and the EMI cover ATaINASSVSIC ‘€ tL ( RUBBER SPACER -emicover | PANEL ‘PHONES(CNI NIDA Vi : Pr KEYAL NI HNS-3028 |" KEYBOARD HIGH ~ GNI “LCD HARNESS LCD SNA P: WIRE BAND PLT-1M (3 points) (C'S SPIRAL CLIP C88 (2 point) 3, Remove the Pane! Boan(KLM.049) 6, Remove the Master VR Bowd(KLM.987) (STB BZMC 3x6) X9 (Mask: (BT B B2MC 3x8) 2 (ark: @) 4, Remove the LCD Assy 17. Remove the Headphone Board(KLM-938) PLAX BZMC2%6) x2 (Mare) {BT'BBZMC 3x8) Xt (Mark: 5. Remave the Wheel Assy TBTR B2Me 3x8) 4 (Mark: @) wean atest SY _GNO SPRING cam Asse Ted fi = aces Hier E = eae - IGNABLE _ aE {ezrenenoo] [vacue_] fo]swzren . 0 | Pedal, system) [system] | cpu RAM ROM O}rn VSSPr io Ol our no || sroroanay oi | SWITCH TE] He meer sor] fygo; tco KEYBOARD eer ie! cian aun ven =. oo gowen Lg 9C52¥ “rm SUPPLY IN WV¥DVIG 19078 ‘Fy gai Stott a ‘a ity 1 fi 6. P.C, BOARDS KLM-947/948/949 KLM-950 COMPONENT SIDE KLM-950 SOLDERING SIDE 7. TEST MODE ‘The XS has a test mode for checking numerous functions, When the (est mode is activated, the X5 internal data is initialized, Hence, if it contains any necessary data, save this data beforehand in a MIDI data filer or other memory device. ‘The’ figure below shows the equipment and settings required for carrying out tests. (Standard Setting) ‘oscilloscope: ‘audio analyzer [eee I = signal selector EXP-2 DS-1 ‘the Test_Model ‘Turn the power switch ON while pressing “PAGE+" and “PAGE-. When the test mode is activated, the internal tests shown below are automatically initialized, If the test results for all of the tests are normal, the next test item is moved to. ‘The initialized internal tests are as follows: + System ROM Check Sum (Internal Test#01) + Internal RAM Test Internal Test#02) + LCD RAM Test (Internal Test#03) + TGLUF Test (Unternal Test#04) + Internal Battery Test (Internal Test#05) + MIDI Loop Test (Internal Test#06) + PCIO Loop Test (Internal Test#07) “PCMROMTGI/F Test (Internal Test#08) If any abnormalities are found in the internal test results, all the LEDs flash and the LCD screen displays an error message. Refer to “Internal Test Error Message Chart” about the contents of the message. " When an internal test is NG, the next test can be moved to by pressing "YES" and "NO" switches at the same time. [YES] SW/[ENTER] SW Test STEP UP [No] sw Test STEP DOWN [PAGE+] SW Test item UP (PAGE-] SW Test item DOWN (External Testi ‘TEST ITEM 1 ‘ Confirm that the LEDs for COMBI, PROG, GLOBAL, MULTI, and 10'S HOLD are all lit. Confirm that the functions of the switches pressed in the order shown on the LCD screen are normal. Confirm that the LEDs are lit when the switches for COMBI, PROG, GLOBAL, MULTI, and 10'S HOLD are pressed. When the test is completed, press the “ENTER switch to move to the next test item. ‘TEST ITEM 2 Step 1 Confirm that the whole LCD is lit, Press the "ENTER switch and confirm that the whole LCD is lit. ‘Step2 Confirm that the whole LCD isnot lit Press the "ENTER" switch and confirm that the whole LCD is blank. Ld Afier confirming it, press the "ENTER" switch to go to the next test item, 2 ‘TEST ITEM 3 Press the "ENTER" switch and confirm the output signal from QUTPUT-L with ‘an oscilloscope. Match MASTER Volume on the panel to the highest level so that the wave form does not clip. Confirm that the MDE Test output wave form is normal. (At least 2 seconds) Confirm that the P-P value of the wave form is within the stipulated range. ‘After confirming it, press the "ENTER" switch to go to the next test item. TEST ITEM 4 ‘Turn the MASTER VOLUME on the product to MAX. Press the "ENTER" switch and measure the noise level of the item to be measured which is displayed on the LCD. Confirm that each noise level is below the stipulated value. ‘Test OUT-L, OUT-R, PHONE-L, and PHONE-R respectively, ‘After confirming it, press the “ENTER” switch to go to the next test item. ‘TEST ITEM 5 Press the “ENTER” switch and measure the output signal level of the item to be measured which is displayed on the LCD. Confirm that each output signal level ig a sine wave within the stipulated range, Also, for OUT-L, OUT-R, PHONE-L, and PHONE-R respectively, confirm that the wave form level changes smoothly when the MASTER VOLUME is controlled and the wave level becomes “0 ‘when the MASTER VOLUME is turned to MIN, After confirming the signal level of PHONE-R, press the “ENTER” switch to go to the next test item. ‘TEST ITEM 6 ‘ Following the display on the LCD screen, play the keyboard from the high keys down to the middle keys to confirm that the touch of the keyboard is normal. ‘TEST ITEM7 Step 1 Confirm ASSIGNABLE SWITCH. ‘After pressing the "ENTER” switch, confirm that the LCD display goes on when the pedal connected to ASS SW is stepped on. Confirm that it goes off when the pedal is released After confirming it, press the "ENTER" switch to go to the next test item. B ‘TEST ITEM 8 Step 1 Confirm PITCH BEND Wheel Confirm that the value displayed on the LCD changes smoothly when BEND is controlled. Confirm that “PASS” is displayed with MAX and MIN, ‘After confirming it, press the "ENTER" switch to go to the next step. Step2 Confirm MODULATION Whee! Confirm that the value displayed on the LCD changes smoothly ‘when MODULATION is controlled. Confirm that "PASS" is displayed with MAX and MIN. After confirming it, press the “ENTER” switch to go to the next step, ‘Step 3 _ Confirm VALUE Slider Confirm that the value displayed on the LCD changes smoothly when VALUE is controlled, Confirm that "PASS" is displayed with MAX and MIN. After confirming it, press the "ENTER" switch to go to the next step. ‘Step4 Confirm ASSIGNABLE Pedal Confirm that the value displayed on the LCD changes smoothly ‘when the ASSIGNABLE pedal is controlled. Confirm that “PASS” is displayed with MAX and MIN. After confirming it, press the "ENTER" switch so that PRELOAD will automatically be executed and the Test Mode will be finished. “ [internal Test Error Message Chart SystemROMChkSum Error: Verify SRAM Write/Read Error: Verify LCDRAMWR Error: Verify TG CPUUF Error: [O~@ } DFA CPU I/F Error: Verity InternalBattry Error:[(D,O]*.#+v MIDI Warning (0.1 PCIO Warning:{,@] (Checksum of system ROM is NG Read/Write of SRAM is NO Read/Write for LCD controller is NG @VoiceFlag ‘Trigger owoff for TGL is NG @TGLING ‘Trigger on/off for TGLI is NG @TGL2 NG ‘Trigger on/off for TGL2 is NG @short/set TGLI and TGL2 can not be started separately Read/Write of TGL internal VDF and VDA resistor is NG Onigh Measured voltage is high Low Measured voltage is low ##:measured voltage value @Oour-->IN Output data and input data are different @OuT x IN Input data is not received or MIDI cable is not connected @Our--21N ‘Output data and input data are different @ouT x IN Input data is not received or RS422 short plug is not connected ‘The read PCM data is NG @:0~F xxxx:PCM address weeeicorrect value ++teread value 6 TEST MODE WAVEFORMS ‘Table 1 Stipulated Range for MDE Wave Form P-P values 55S~7.8 VP-P Table 2 Stipulated Range for Residual Noise and Output Signl Level Residual Noise Output Signal Level Freq. Out-L | -90.0{aBu) or less} 2.00~3.50[4Bu] 488 Hz OutR | -90.0[4Bu] or tess | 2,00~3.50faBu] 412 Hz Ph-L | -90.0{4Bu]orless | -1.00~0.50[4Bu}33Q load | 548 Hz Ph-R | -90.0{dBuj orless | -1.00~0.50{4Bu}33Q toad | 610 Hz Fig.1 : MDE Waveform (at VOL MAX) ah I +. inn hy : SIN Waveform 7 aibep a Fig.3 ; VOL Action Confirmation 16 8. REFERENCE DATA P.C.BOARDs KLM.945/946 : KLM.947 KLM.948, KLM.949 KLM.950 cru TONE GENERATOR = ‘SYSTEM ROM = SYSTEM RAM : DRAM : WAVE ROM : D/A CONVERTOR : PITCH/MOD P.C.BOARD MASTER VR P.C.BOARD HEADPHONE P.C.BOARD PANEL SW P.C.BOARD MAIN P.C.BOARD UPD70433GD-5BB MBCS35104(TGL) ‘MSMS34000B-23RS-*#*(MASK ROM) UPD43256BGU-85L-E2 or MB84256A-10LPF-G-BND-EF ‘MBB81464-10PSZ-G-BB-RS2(64K x 4) ‘TCS11664BIL(64K x 16) ‘MB8316200-15PF-G-402-HT(for GM1) or MX23C1610MC-15 GM1 UPD23C16000BGX-385(for GM2) or MX23C1610MC-15 GM2 LH537GG5 ‘or MX23C1610MC-15 ROMA PCM69AU UPD70433GD-5BB(CPU) PIN ASSIGNMENT danddaaadece NEC sapan pzgasaen vo uv qc14 Ic10 1C13 1€23, 1c24 Ic12 Ici 1c7 1c8 1c9 1c2 UPD70433GD-55B(CPU) PIN FUNCTION. PIN NAME, VO FUNCTION P00-PO7 UO PORTO NMI 1 NON MASKABLE INTERRUPT INTPO-INTPS I EXTERNAL INTERRUPT REQUEST P20-P21 VO PORT2 ‘TXDO-TXD1 0 TRANSMIT DATA OUTPUT RXDO-RXDI I RECEIVE DATA INPUT 1XxC © ‘TRANSMIT CLOCK OUTPUT cTso 1 ENABLING SIGNAL INPUT SCKi © SERIAL CLOCK OUTPUT P40-P47 VO PORTS P50-P52 VO PORTS ANIO-ANI3 I ‘ANALOG SIGNAL INPUT P20-P77 VO PORT7 DMARQO-1 T DMA REQUEST SIGNAL INPUT GND GROUND vpD. +5V POTENTIAL VSS ANALOG GRCUND AVDD ANALOG +5V POTENTIAL ‘AVREF I REFERENCE POTENTIAL INPUT FOR A/D CONVERTER RESET 1 SYSTEM RESET SIGNAL INPUT XA, X2 1 SYSTEM CLOCK INPUT: ‘CLKOUT © SYSTEM CLOCK OUTPUT ASTB © —_ ADDRESS STROBE SIGNAL OUTPUT RD © _ DATAREAD STROBE SIGNAL OUTPUT WRL © —_ LOW BIT DATA WRITE STROBE SIGNAL OUTPUT WRI © HIGH BIT DATA WRITE STROBE SIGNAL OUTPUT READY I READY SIGNAL INPUT. DEX © DATA BUS ENABLE SIGNAL OUTPUT RAS © DRAM ROW ADDRESS LATCH TIMING SIGNAL OUTPUT Da/D16 1 BUS SIZE SELECT INPUT BUSLOCK, © BUS LOCK SIGNAL OUTPUT POLL I POLL SIGNAL INPUT HLDRQ 1 BUS HOLD REQUEST SIGNAL INPUT HLDAK © BUS HOLD ACKNOWLEDGE SIGNAL OUTPUT ADO-ADIS VO ADDRESS/DATA SIGNAL ‘AN6-A23 © ADDRESS SIGNAL OUTPUT TORD © VO READ STROBE SIGNAL OUTPUT. IOWR © ‘VO WRITE STROBE SIGNAL OUTPUT DMAAKO-1 © DMA ACKNOWLEDGE SIGNAL OUTPUT TCEO-TCEI © DMA FINISH SIGNAL OUTPUT 8 MBCS35104 (TGL) PIN ASSIGNMENT = Ex oo von BO mu tie mn 85 2 = =) foie MBCS35104 (TGL) PIN FUNCTION PIN NAME, VO FUNCTION vpD 45v vss Ground Rest I System Rest MCK 1 Master Clock cKO 0 32MHz CKO0-1 © CLK/2 duty 50% output cKo2 O ——CLK/4 duty 50% output CKSEL I Phase Analog Select for CKOO cKCL I CKOO Reset input XMM I for Test mode XMS2-0 I for Test mode XTMCK I for Test mode XTRE I for Test mode XTWE I for Test mode for CPU cPUSL I CPU select V25/H8 cs 1 Chip select WR I CPU WRITE pulse RD 1 CPUREAD pulse A0-9 1 CPU Address Bus Do0-9 VO CPU Data Bus PO-3 O Output Port 9 for PCM ROM MD0-15 uM MD16-23, I MAO-19 ° BNKO-3 ° DMODE I WMODE I SYNCO ° SYNCI I for Serial Interface ‘SD00-1 oO BCKO ° LRCKO ° SDI0-1 1 BCKI 1 LRCKI 1 sMoDO-3 1 for DRAM -- BAO-7 ° EDO-19 v0 EWE ° EOE ° RAS ° CAS ° PCM Memory Data Bus 0-15 PCM Memory Data Bus 16-23 (for 27Gs mode) PCM Memory Address Bus PCM Memory Bank Select, DECODE Mode Select H: Decode BNK# L: Thru BNK# PCM Memory -word Select H: 64 osc. , 27Gs Mode L: 32 ose. , 1TG Mode Counter Synchro Output (only 2TGs Mode) Counter Synchro Input (only 2TGs Mode) Serial Data Outout Out SDO0: Cch & D ch SDOI: Ach & Bch Bit Clock Output @MHz, S0Onsec.) ER Clock Output L:Rch Hi: L ch Serial Data Input. 0,1 ‘SDIO: C ch & D ch SDII: A ch & Bch Bit Clock Input (2MHz, S0Onsee.) LR Clock Input L:Rch Hi Lch Serial VF Format Select DRAM Address DRAM Data DRAM WE DRAM OF DRAM RAS DRAM CAS 20 1, Voltage check of power supply Check that a voltage of +5V (+5%) is input at the VDD pin, 4.75V S VDD 5 5.25V 2. Check of input/output pins, regardless of the CPU interface setting PIN NAME, FUNCTION BCKO 2.0 MHz bit clock signal outputs to the D/A converter. LRCKO 31,25 KHz L/R clock signal output to the D/A converter. If the voltage level of these pins is +3V or less, check the soldering of peripheral pins and the voltage of the connected device, Also, if any of these pins is OV or +5V, check to see whether RESET(TGRES) for the master clock(32,0MHz) has been input. If RESET and MCK are normal, and the test mode setting pins have been set as below, check the soldering and the pattern on the circuit board. 3. Check of inputioutput pins, when any key is on PIN NAME FUNCTION XCS, XWE Control signal from the CPU During KEY ON or PROG. CHANGE, check that a low level pulse signal is input from the CPU to the above pins(XSC, XWE). If these signals cannot be observed with the oscilloscope, check the CPU and its peripheral circuits. PIN NAME FUNCTION SDO0, SDO1 serial data output to the D/A converter In case of observing the waveform with the oscilloscope, it is best to input the LRCKO clock signal to the external trigger input of the oscilloscope. If the serial data cannot be output, check the PCM address bus. To find whether normal serial data is’ output or not, check whether there is a different bit from the code bit at the left side ‘of the leading and the trailing edge of LRCKO on the oscilloscope screen. srcx0-! feselecry spo + sign —+—————_+ swing level a CHECK POINTS 1. CLOCK CIRCUIT - TGL i fIRR ape rom 4pin of 1C19 : “To 139pin(MCK) of IC1O : f= 32.00Mitz Wy TWAT | TM i Te TT i TAR Se i san : e| 2. CLOCK CIRCUIT - CPU S18 From X2(28MHz) To 11pin(X1) and 12pin(X2) of IC14 f= 28.00MHz, A\|/ li | ny a £ 3. TGL - DAC = abc ts From 151pin(CKO0) of [C10 To 1Spin(SYSCLK) of C2 f= 16.00MHz. f f PR a ae ce 4. TGL - DAC fms 1494 44 tit From 152pin(LRCKO) of C10 To 16pin(WDCK) of 1C2 f= 31.25KHz 5. TGL - DAC/PC IF(TO HOST) uae 4 ea UL ny tl From 153pin(BCKO) of IC10 ‘To 14pin(BCK) of 1C2 13 [3 | +5 3 f= 200M e oT 1 6 RESET CPU yp ty se From 7pin(RES) of IC29 cule To Spin(RESET) of IC14 3 when the power is turned on 7. CPU-TGL From 39pin(TXC) of IC14 To 2pin(RESET) of IC10 > when the power is turned on 8, TGL - DAC From 15Spin($D00) of 1C10 To 17pin(DATA-L) of IC2 3 when the MDE test waveform is transmitted Chi: LRCK Ch2: DATA FOR HARNESS & 530 a A 250_ 1 20 HNS-8021 NGA CNEB 0 w 1 Fone PHR-1O. aoe bl BS20-010 200 HNS-8022 CNT7A CN7B 520-009 HNS=8023 Nol HNS-8027, KEYBOARD LOW No.l Nout § SS EEE SaE EU v 33078 wn _| i HNS-3028

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