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Chipedge

The document outlines an analog layout design course covering various topics over 10 weeks. Week 1 covers IC fabrication processes. Week 2 covers layout editor tools. Weeks 3-8 cover techniques for specific layout components like resistors, capacitors, transistors, op amps, and SRAM blocks. Week 9 provides assignments based on the material. Week 10 involves a project to design and layout an analog circuit like an LDO or op amp in the latest technology node.

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MhappyCu
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244 views

Chipedge

The document outlines an analog layout design course covering various topics over 10 weeks. Week 1 covers IC fabrication processes. Week 2 covers layout editor tools. Weeks 3-8 cover techniques for specific layout components like resistors, capacitors, transistors, op amps, and SRAM blocks. Week 9 provides assignments based on the material. Week 10 involves a project to design and layout an analog circuit like an LDO or op amp in the latest technology node.

Uploaded by

MhappyCu
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Analog Layout Design

Course Content outline:

Week 1 : Fabrication Process

 Basic steps of IC fabrication


 CMOS IC fabrication
 Deep Submicron Technology

Week 2: Layout Editor Tool

 Creating and managing libraries and cell.


 Commands for Layout editing.
 Commands for schematic editing.
 Verification : DRC and LVS

Week 3 : Layout or Physical Implementation

 Understanding the schematic symbols and parameters


 Resistor, Capacitor layout techniques
 Cmos and BiCMOS layout techniques

Week 4 : Standard Cell Layout

 Layout of Inverter, AND, OR, NAND, NOR, AOI, OAI, LATCH, FLOP,

Week 5 : Matching

 Matching techniques
 common centriod, interdigitized and proximity matching.
 Matching of Resistors, Capacitors
 Matching of mos transistors

Week 6: Complex Layout enemies

 Electro-migration
 Power/Signal IR Drop
 cross-talk and coupling
 Electrostatic Discharge

Week 7 : Deep Submicron Layout Issues

 Shallow Trench Isolation (LOD)


 Well Proximity Effect.

Week 8 : Analog and Mix signal Layout


 Single stage differential opamp layout
 Input pair, current mirrors and output stage.
 Two stage differential opamp layout
 Input pair, differential routing, Power routing, offset minimizing.

Week 9 : Building blocks of SRAM

 Memory Bit cell


 Row decoder
 Word line driver
 Sense amplifier
 Control block
 Misc digital logic.
 Pitch Calculation for blocks.
 Power Planning
 Assignments based on above theory.

Week 10 : Project

 Analog Projects like LDO, Op-amp & other similar size projects will be executed in latest technology
nodes.
 Std layouts will be done as part of labs & assignments. No separate project will be executed.
Physical Design

Pre-Requisites:

Knowledge on below topics are Required.

1. Working knowledge of linux.


2. Knowledge of digital Electronics fundamentals.
3. Knowledge of CMOS fundamentals.
4. Knowledge of Verilog / VHDL is a plus
5. Knowledge of ASIC / SOC design flow is a plus

Course Outline:

Module 1: CMOS fundamentals & Introduction to Physical Design

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits,
MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical
Design flow.

Module 2: Inputs & Sanity Check

List of inputs (libraries, technology files, netlist, timing constraints, IO placement) to the PD
flow, contents of each input, qualifying the received inputs and sanity checks.

Module 3: Floorplan

Goals of floor planning, different aspects of floor planning, Area estimation,


Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width
estimation, Floor planning guidelines.

Module 4: Power Routing:

Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/std cell
rail.

Module 5: Placement

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, , pre-
place optimization and in-place optimization, congestion analysis, timing analysis, Tie-cells,
High-Fanout Net Synthesis,Scan chain re-order, Regioning/Grouping/Bounds.
Module 6: Timing Analysis & Optimization

Basic timing checks(setup, hold..), understanding timing constraints(SDC), timing corners,


timing report analysis, general optimization techniques, typical causes for timing violations and
strategies for fixing the same.

Module 7: Clock Tree Synthesis (CTS)

Goals of CTS, Types of Clock-tree, CTS Specification, Building clock tree, Analyze the results,
Fine-tuning the Clock-tree and Guidelines for best CTS results.

Module 8: Routing

Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing
violations (DRC, LVS), post route optimization, issues in routing and guide lines for optimum
routing results.

Module 9: ECO Flow

What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing
the ECO placement and routing.

Module 10: Sign-off Checks

Physical Verification (DRC, LVS, ERC), IR drop analysis, Electro-Migration Analysis, Cross-
Talk (SI) analysis, Sign-off Timing analysis, Logical Equivalence checking.

Module 11: Project

2 projects will be given covering Netlist to GDS flow. The method of execution will be similar to
typical block level Physical Design work/project in the industry. Block level input database will
be given and the participant has to complete routing, after cleaning all the issues during sign-off
checks.

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