12/16/2022

Weekly Lecture Plan

Week Topic Textbook
Harris 1.4, 5.3,
1 Introduction to Number Systems and codes, Introduction to VerilogHDL
1.5
Introduction to Boolean algebra, Analysis and synthesis of digital logic
2-3 circuits: Basic logic function, combinational logic design, Universal logic Harris 2.1-2.9
gates, Minimization of combinational logic, k-map
Programming and structural and behavioral design of digital systems
4 using VerilogHDL, Verilog Timing analysis and test bench. Verilog Harris 4
synthesis with combinational logic
Harris 5.2-
5 ALU design (Adder, Subtractor, Comparator)
Floyd 6.1-6.3
Winter Vacation
6 Decoder, encoder, Multiplexer, demultiplexer Floyd 6.4-6.9
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 1
Department of EEE, BUET
1

Class Test Announcement

• 21st December 2022 (Wednesday)
• Respective classrooms.
• A1, B1 and C1 will come in sharp 8am in their respective classes.
• A2, B2 and C2 will come at sharp 8:20am, and wait for the invigilator’s
instruction to enter the classroom
• Class Test Syllabus: 1st 4 weeks

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 2

Department of EEE, BUET
2

1
 12/16/2022

EEE 303 – Digital Electronics

EEE Verilog

303
Lecture 04.1
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology

Digital Circuit Design Steps

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 4
Department of EEE, BUET
4

2
 12/16/2022

High Level Design

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 5
Department of EEE, BUET
5

Low Level Design

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 6
Department of EEE, BUET
6

3
 12/16/2022

RTL Coding

• Register Transfer Logic

• Micro design is converted into Verilog/VHDL code, using
synthesizable constructs of the language.

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 7
Department of EEE, BUET
7

Introduction
• Hardware description language (HDL):
• specifies logic function only
• Computer-aided design (CAD) tool produces or synthesizes
the optimized gates
• Most commercial designs built using HDLs
• Two leading HDLs:
• SystemVerilog
– developed in 1984 by Gateway Design Automation
– IEEE standard (1364) in 1995
– Extended in 2005 (IEEE STD 1800-2009)
• VHDL 2008
– Developed in 1981 by the Department of Defense
– IEEE standard (1076) in 1987
– Updated in 2008 (IEEE STD 1076-2008)

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 8

Department of EEE, BUET
8

4
 12/16/2022

HDL to Gates

• Simulation
– Inputs applied to circuit
– Outputs checked for correctness
– Millions of dollars saved by debugging in simulation instead of
hardware
• Synthesis
– Transforms HDL code into a netlist describing the hardware (i.e.,
a list of gates and the wires connecting them)

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 9

Department of EEE, BUET
9

HDL: Hardware Description Language

IMPORTANT:
When using an HDL, think of the hardware the
HDL should produce.

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 10

Department of EEE, BUET
10

5
 12/16/2022

Verilog Module

• An elementary Verilog program is called a module.

• A module corresponds to a digital circuit.
Modules have input and output ports that correspond to the
input
• and output terminals of a digital circuit.
• The ports and variables used to represent internal signals are
declared at the beginning of the program.
• Modules have other statements used to define how it transforms
the input signals to output signals.
12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 11
Department of EEE, BUET
11

Verilog Modules

a
Verilog SystemVerilog
b y
Module Module
c

Two types of Modules:

– Behavioral: describe what a module does
– Structural: describe how it is built from
simpler modules

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 12

Department of EEE, BUET
12

6
 12/16/2022

Structural vs Behavior

• Structural modules consist of a list of component

modules (defined elsewhere) and a list of wires used to
interconnect the modules.
• Behavior modules specify the output signals as
functions of the input signals. They need not give any
indication of the structure of the circuit.

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 13
Department of EEE, BUET
13

Behavioral Verilog
SystemVerilog:
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule

• module/endmodule: required to begin/end module

• example: name of the module
• Operators:
~: NOT
&: AND
|: OR

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 14

Department of EEE, BUET
14

7
 12/16/2022

Behavioral Verilog vs SystemVerilog

SystemVerilog: (Text Book)
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule

Verilog:
module example(a, b, c, y);
input a, b, c;
output y;
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 15

Department of EEE, BUET
15

Behavioral Verilog: Simulation

Verilog:
module example(a, b, c, y);
input a, b, c;
output y;
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 16

Department of EEE, BUET
16

8
 12/16/2022

HDL
Behavioral Synthesis
Verilog: Synthesis
Verilog:
module example(a, b, c, y);
input a, b, c;
output y;
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
Synthesis:
b
c y
un5_y y

un8_y
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 17
Department of EEE, BUET
17

Verilog Input and Output

• Individual signals (e.g., A, B, ... in the previous example) can take any of the
following four values:
• 0 = logic value 0
1 = logic value 1
z = tri-state (high impedance) x = unknown value
• The unknown value is used by simulators to indicate that they do not know
how to determine a signals value (e.g., the user has not specified a value for
an input signal). The tri-state value means that no signal is assigned to the
variable.
• The unknown value x can also be used to specify a don’t care condition to
the synthesis tools.
• Note that ports must be listed in the module statement (first line) and their
direction (input or output) declared in the following statements.
12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 18
Department of EEE, BUET
18

9
 12/16/2022

SystemVerilog Syntax
• Case sensitive
• Example: reset and Reset are not the same
signal.
• No names that start with numbers
• Example: 2mux is an invalid name
• Whitespace ignored
• Comments:
• // single line comment
• /* multiline
comment */

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 19

Department of EEE, BUET
19

Assignments
module fulladder(a, b, cin, s, cout);
input a,b,cin;
output s, cout;
logic p, g; // internal nodes

assign p = a ^ b;
assign g = a & b;

assign s = p ^ cin;
assign cout = g | (p & cin);
endmodule
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 20
Department of EEE, BUET
20

10
 12/16/2022

Assignment
• The three assign statements are independent and can execute in any order or concurrently.
• The right side of an assign statement is evaluated and its resulting value assigned to the signal
on the left side whenever one of the signals used in the right side changes value.
• This type of assignment is also called a continuous assignment.
• This method of interpreting the execution of assign statements is quite different
• from that use in conventional programming languages in the following ways:
• Two or more assignments can execute simultaneously. This is necessary to represent the
timing characteristics of hardware systems.
• An assignment executes whenever it is ready (i.e., has new data for the variables on its right
side)
• There is no concept of "locus of control" or “program counter” that determines the next
instruction to execute. Therefore, the order the assignments are written does not matter
• This method of assignment statement execution is sometimes called non-procedural or data-
driven execution, where conventional programming languages are said to be procedural.

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 21
Department of EEE, BUET
21

Behavioral vs. Structural Verilog Descriptions

• The previous example is a behavioral descriptions because it specifies the logical values
of the circuit's outputs as logical equations with no reference to how the gates in a
possible implementation might be interconnected.
• It is also possible to specify a structural description in Verilog that specifies explicitly how a
set of smaller components (e.g., gates) are interconnected to form a larger system as
shown on the following slide.
• Note that the internal connections from gate outputs to gate inputs are declared to be of
type wire.
• These wire declarations could be omitted as long as the component modules are simple
gates. Verilog will assume that any gate output signal that is not declared is of type wire.
• Each gate is specified by its name (e.g., and, or, ...) and a list of ports or wires connected
to its terminals. All gates have a single output and it is always listed first in this list.

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 22
Department of EEE, BUET
22

11
 12/16/2022

Structural Verilog
module circuit1s (A, B, C, D, E, X, Y, Z);
input A, B, C, D, E;
output X, Y, Z;
wire T1, T2, T3, T4, T5, T6, T7;
xor(T1, A, B);
or(T2,T1,C);
not(X, T2);
and(T3, B, C);
or(T4, T3, D);
not(T5, T4);
and(Y, T5, E);
or(T6, A, D);
and(T7, B, C);
or(Z, T6, T7);
endmodule
12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 23
Department of EEE, BUET
23

Structural Modeling - Hierarchy

SystemVerilog Verilog:
module and3(input logic a, b, c, module and3(a, b, c, y);
output logic y); input a,b,c;
assign y = a & b & c; output y;
endmodule assign y = a & b & c;
endmodule

module inv(input logic a,

output logic y); module inv(a, y);
assign y = ~a; input a;
endmodule output y;
assign y = ~a;
endmodule
module nand3(input logic a, b, c
output logic y);
logic n1; // internal signal module nand3(a, b, c, y);
input a,b,c;
and3 andgate(a, b, c, n1); // instance of and3 output y;
inv inverter(n1, y); // instance of inv wire n1; // internal signal
endmodule and3 andgate(a, b, c, n1); // instance of and3
EEE 303 – Digital Electronics inv inverter(n1, y); // instance of
Dr. Sajid Muhaimin Choudhury 24
endmodule
Department of EEE, BUET
24

12
 12/16/2022

Bitwise Operators
SystemVerilog Verilog:
module gates(input logic [3:0] a, b, module gates(a, b, y1, y2, y3, y4, y5);
output logic [3:0] input [3:0]a; [3:0]b;
y1, y2, y3, y4, y5); output [3:0]y1, [3:0]y2, [3:0]y3,
/* Five different two-input logic [3:0]y4, [3:0]y5;
gates acting on 4 bit busses */ /* Five different two-input logic
assign y1 = a & b; // AND gates acting on 4 bit busses */
assign y2 = a | b; // OR
assign y1 = a & b; // AND
assign y3 = a ^ b; // XOR
assign y2 = a | b; // OR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
assign y3 = a ^ b; // XOR
assign y4 = ~(a & b); // NAND
endmodule
Synthesis: assign y5 = ~(a | b); // NOR
endmodule
// single line comment
/*…*/ multiline comment

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 25

Department of EEE, BUET
25

Reduction Operators
SystemVerilog:
module and8(input logic [7:0] a,
output logic y);
assign y = &a;
// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4] &
// a[3] & a[2] & a[1] & a[0];
endmodule
Synthesis:

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 26

Department of EEE, BUET
26

13
 12/16/2022

Conditional Assignment
SystemVerilog:
module mux2(input logic [3:0] d0, d1,
input logic s,
output logic [3:0] y);
assign y = s ? d1 : d0;
endmodule
Synthesis:

? : is also called a ternary operator because it

operates on 3 inputs: s, d1, and d0.

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 27

Department of EEE, BUET
27

Internal Variables
SystemVerilog:
module fulladder(input logic a, b, cin,
output logic s, cout);
logic p, g; // internal nodes

assign p = a ^ b;
assign g = a & b;
Synthesis:
assign s = p ^ cin; s

assign cout = g | (p & cin); g s

endmodule cin

cout
a
b
un1_cout cout
p

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 28

Department of EEE, BUET
28

14
 12/16/2022

Precedence
Highest ~ NOT
*, /, % mult, div, mod
+, - add,sub
<<, >> shift
<<<, >>> arithmetic shift
<, <=, >, >= comparison
==, != equal, not equal
&, ~& AND, NAND
^, ~^ XOR, XNOR
|, ~| OR, NOR
Lowest ?: ternary operator

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 29

Department of EEE, BUET
29

Numbers
Format: N'Bvalue
N = number of bits, B = base
N'B is optional but recommended (default is decimal)
Number # Bits Base Decimal Stored
Equivale
nt
3'b101 3 binary 5 101
'b11 unsized binary 3 00…0011
8'b11 8 binary 3 00000011
8'b1010_1011 8 binary 171 10101011
3'd6 3 decimal 6 110
6'o42 6 octal 34 100010
8'hAB 8 hexadecimal 171 10101011
42 Unsized decimal 42 00…0101010
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 30
Department of EEE, BUET
30

15
 12/16/2022

Bit Manipulations: Example 1

assign y = {a[2:1], {3{b[0]}}, a[0], 6'b100_010};

// if y is a 12-bit signal, the above statement produces:

y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 0 0 1 0

// underscores (_) are used for formatting only to make

// it easier to read. SystemVerilog ignores them.

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 31

Department of EEE, BUET
31

Bit Manipulations: Example 2

SystemVerilog:
module mux2_8(input logic [7:0] d0, d1,
input logic s,
output logic [7:0] y);

mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]);

Synthesis:
mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]); mux2
s s
endmodule [7:0] [3:0] [3:0] [7:0]
d0[7:0] d0[3:0] y[3:0] y[7:0]
[7:0] [3:0]
d1[7:0] d1[3:0]

lsbmux

mux2
s
[7:4] [7:4]
d0[3:0] y[3:0]
[7:4]
d1[3:0]

msbmux

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 32

Department of EEE, BUET
32

16
 12/16/2022

Z: Floating Output
SystemVerilog:
module tristate(input logic [3:0] a,
input logic en,
output tri [3:0] y);
assign y = en ? a : 4'bz;
endmodule

Synthesis:
en
[3:0] [3:0] [3:0] [3:0]
a[3:0] y[3:0]

y_1[3:0]

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 33

Department of EEE, BUET
33

Delays
module example(input logic a, b, c,
output logic y);
logic ab, bb, cb, n1, n2, n3;
assign #1 {ab, bb, cb} = ~{a, b, c};
assign #2 n1 = ab & bb & cb;
assign #2 n2 = a & bb & cb;
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 34

Department of EEE, BUET
34

17
 12/16/2022

Delays
module example(input logic a, b, c,
output logic y);
logic ab, bb, cb, n1, n2, n3;
assign #1 {ab, bb, cb} =
~{a, b, c};
assign #2 n1 = ab & bb & cb;
assign #2 n2 = a & bb & cb;
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 35

Department of EEE, BUET
35

Delays
1
module example(input logic a, b, c,
output logic y);
logic ab, bb, cb, n1, n2, n3;
assign #1 {ab, bb, cb} =
~{a, b, c};
assign #2 n1 = ab & bb & cb;
assign #2 n2 = a & bb & cb;
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 36

Department of EEE, BUET
36

18
 12/16/2022

Delays
module example(input logic a, b, c,
2
output logic y);
logic ab, bb, cb, n1, n2, n3;
assign #1 {ab, bb, cb} =
~{a, b, c};
assign #2 n1 = ab & bb & cb;
assign #2 n2 = a & bb & cb;
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 37

Department of EEE, BUET
37

Delays
module example(input logic a, b, c,
output logic y);
logic ab, bb, cb, n1, n2, n3;
assign #1 {ab, bb, cb} =
~{a, b, c};
assign #2 n1 = ab & bb & cb;
assign #2 n2 = a & bb & cb; 2
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 38

Department of EEE, BUET
38

19
 12/16/2022

Delays
module example(input logic a, b, c,
output logic y);
logic ab, bb, cb, n1, n2, n3;
assign #1 {ab, bb, cb} =
~{a, b, c};
assign #2 n1 = ab & bb & cb;
4
assign #2 n2 = a & bb & cb;
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 39

Department of EEE, BUET
39

Procedural Block (Always Blocks)

• A procedural block is a construct that contains statements that are
executed procedurally (i.e., in the order they are written).
always @(sensitivity_list)
begin
procedural statements
end
• The sensitivity list is a list of signals separated by or.
• When any one of the signals in the sensitivity list changes value, the always
block wakes up, executes its procedural statements, and then goes back to
sleep.
• The always block acts like a generalized assign statement where
the action that takes place can be specified by sequential
12/16/2022
code.
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 40
Department of EEE, BUET
40

20
 12/16/2022

Always Block Example

module always_example(x, y, z);

input x, y;
output z;
reg z, s;
always @(x or y)
begin
s = x ^ y;
z = x & s;
end
endmodule
12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 41
Department of EEE, BUET
41

Reg variable

• Variables declared as type reg hold their value until they are assigned a
new value. It is said that the assigned value is registered in the variable
• Whenever x or y changes value, the always block is executed as follows:
• First, the statement s = x^y executes and registers a new value in s Next, the statement
z = x & s executes using the new value of s that
• it received when the first statement was executed.
• Then the block stops executing and waits for either x or y to change again.

• Variables on the left side of a procedural statement must be declared as

type reg.
• The main advantage of using always blocks to represent combinational
circuits is that you can use control statements such as “if then else” as
illustrated by the following example
12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 42
Department of EEE, BUET
42

21
 12/16/2022

Explain how the behaviors of the following two modules differ

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 43
Department of EEE, BUET
43

Conditions for combinational behavior of always blocks

• The following conditions are necessary for an always block to represent

combinational logic (as opposed to sequential logic)
• All reg, wire and input signals that appear on the right side of an assignment statement
within the always block must appear in the sensitivity list
– We call a sensitivity list that satisfies this condition a complete sensitivity list.
• All signals in the sensitivity list must appear without edge specifiers
– Edge specifiers indicate that a signal is asserted by a change in value as opposed to its level (e.g., a rising
edge or falling edge). They are introduced and utilized in later chapters on sequential circuits.

• All output signals must be assigned a value every time the always block
executes
• These conditions guarantee that the input signals uniquely determine the
output signals, which is the very definition of a combinational circuit.
• A sensitivity list of the form @(*) is shorthand for a complete list. It is
recommended that you use this notation for combinational always block
12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 44
Department of EEE, BUET
44

22
 12/16/2022

Example (Incomplete sensitivity list)

module example1(a, b, c, f);

input a, b, c;
output f;
reg f;
always @(a, b)
if (a==1)
f = b;
else
f = c;

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 45
Department of EEE, BUET
45

Logic Operation

12/16/2022

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 46

Department of EEE, BUET
46

23
 12/16/2022

Examples

a = b + c ;
a = 1 << 5;
a = !b ;
a = ~b ;

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 47
Department of EEE, BUET
47

If-else-end

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 48
Department of EEE, BUET
48

24
 12/16/2022

Case

It's a good idea to have a default case. If the Verilog machine enters into
a non-covered statement, the machine hangs. Defaulting the statement
with a return to idle keeps us safe.

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 49
Department of EEE, BUET
49

While

A while statement executes the code within

it repeatedly if the condition it is assigned
to check returns true.

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 50
Department of EEE, BUET
50

25
 12/16/2022

While - counter

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 51
Department of EEE, BUET
51

For

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 52
Department of EEE, BUET
52

26
 12/16/2022

Initial Block

• An initial block, as the name suggests, is executed only

once when simulation starts. This is useful in writing test
benches.

12/16/2022
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 53
Department of EEE, BUET
53

EEE 303 – Digital Electronics

EEE Test Bench

303
Lecture 04.2
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology

54

27
 12/16/2022

Testbenches
• HDL that tests another module: device under test (dut)
• Not synthesizeable
• Types:
• Simple
• Self-checking
• Self-checking with testvectors

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 55

Department of EEE, BUET
55

Testing VLSI circuits

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 56

Department of EEE, BUET
56

28
 12/16/2022

Component Description
Generator Generates different input stimulus to be driven to DUT

Interface Contains design signals that can be driven or monitored

Driver Drives the generated stimulus to the design

Monitor Monitor the design input-output ports to capture design

activity
Scoreboard Checks output from the design with expected behavior

Environment Contains all the verification components mentioned above

Test Contains the environment that can be tweaked with

different configuration settings

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 57

Department of EEE, BUET
57

Testbench Example
• Write SystemVerilog code to implement the
following function in hardware:
y = bc + ab
• Name the module sillyfunction

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 58

Department of EEE, BUET
58

29
 12/16/2022

Testbench Example
• Write SystemVerilog code to implement the
following function in hardware:
y = bc + ab

module sillyfunction(input logic a, b, c,

output logic y);
assign y = ~b & ~c | a & ~b;
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 59

Department of EEE, BUET
59

Simple Testbench
module testbench1();
logic a, b, c;
logic y;
// instantiate device under test
sillyfunction dut(a, b, c, y);
// apply inputs one at a time
initial begin
a = 0; b = 0; c = 0; #10;
c = 1; #10;
b = 1; c = 0; #10;
c = 1; #10;
a = 1; b = 0; c = 0; #10;
c = 1; #10;
b = 1; c = 0; #10;
c = 1; #10;
end
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 60

Department of EEE, BUET
60

30
 12/16/2022

Self-checking Testbench
module testbench2();
logic a, b, c;
logic y;
sillyfunction dut(a, b, c, y); // instantiate dut
initial begin // apply inputs, check results one at a time
a = 0; b = 0; c = 0; #10;
if (y !== 1) $display("000 failed.");
c = 1; #10;
if (y !== 0) $display("001 failed.");
b = 1; c = 0; #10;
if (y !== 0) $display("010 failed.");
c = 1; #10;
if (y !== 0) $display("011 failed.");
a = 1; b = 0; c = 0; #10;
if (y !== 1) $display("100 failed.");
c = 1; #10;
if (y !== 1) $display("101 failed.");
b = 1; c = 0; #10;
if (y !== 0) $display("110 failed.");
c = 1; #10;
if (y !== 0) $display("111 failed.");
end
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 61

Department of EEE, BUET
61

Testbench with Testvectors

• Testvector file: inputs and expected outputs
• Testbench:
1. Generate clock for assigning inputs, reading
outputs
2. Read testvectors file into array
3. Assign inputs, expected outputs
4. Compare outputs with expected outputs and report
errors

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 62

Department of EEE, BUET
62

31
 12/16/2022

Testbench with Testvectors

• Testbench clock:
• assign inputs (on rising edge)
• compare outputs with expected outputs (on
falling edge).

CLK

Assign Compare
Inputs Outputs to
Expected
• Testbench clock also used as clock for synchronous
sequential circuits

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 63

Department of EEE, BUET
63

Testvectors File
• File: example.tv
• contains vectors of abc_yexpected
000_1
001_0
010_0
011_0
100_1
101_1
110_0
111_0

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 64

Department of EEE, BUET
64

32
 12/16/2022

1. Generate Clock
module testbench3();
logic clk, reset;
logic a, b, c, yexpected;
logic y;
logic [31:0] vectornum, errors; // bookkeeping variables
logic [3:0] testvectors[10000:0]; // array of testvectors

// instantiate device under test

sillyfunction dut(a, b, c, y);

// generate clock
always // no sensitivity list, so it always executes
begin
clk = 1; #5; clk = 0; #5;
end

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 65

Department of EEE, BUET
65

2. Read Testvectors into Array

// at start of test, load vectors and pulse reset

initial
begin
$readmemb("example.tv", testvectors);
vectornum = 0; errors = 0;
reset = 1; #22; reset = 0;
end

// Note: $readmemh reads testvector files written in

// hexadecimal

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 66

Department of EEE, BUET
66

33
 12/16/2022

3. Assign Inputs & Expected

Outputs
// apply test vectors on rising edge of clk
always @(posedge clk)
begin
#1; {a, b, c, yexpected} = testvectors[vectornum];
end

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 67

Department of EEE, BUET
67

4. Compare with Expected

Outputs
// check results on falling edge of clk
always @(negedge clk)
if (~reset) begin // skip during reset
if (y !== yexpected) begin
$display("Error: inputs = %b", {a, b, c});
$display(" outputs = %b (%b expected)",y,yexpected);
errors = errors + 1;
end

// Note: to print in hexadecimal, use %h. For example,

// $display(“Error: inputs = %h”, {a, b, c});

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 68

Department of EEE, BUET
68

34
 12/16/2022

4. Compare with Expected

Outputs
// increment array index and read next testvector
vectornum = vectornum + 1;
if (testvectors[vectornum] === 4'bx) begin
$display("%d tests completed with %d errors",
vectornum, errors);
$stop;
end
end
endmodule

// === and !== can compare values that are 1, 0, x, or z.

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 69

Department of EEE, BUET
69

EEE 303 – Digital Electronics

EDA Playground
Example

Dr. Sajid Muhaimin Choudhury, Assistant Professor

Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology

70

35
 12/16/2022

Full Adder – EDA PlayGround

https://www.edaplayground.com/x/3k2b
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 71
Department of EEE, BUET
71

Full Adder – EDA PlayGround - Code

Test Bench Main Code

// Code your testbench here // Code your design here
// or browse Examples
module testbench; module full_adder(s,co,a,b,c);
reg a,b,c; input a,b,c;
wire sum,cout; output s,co;
integer i;
full_adder FA(sum,cout,a,b,c);
assign s=a^b^c;
initial assign co=(a&b)|(b&c)|(c&a);
begin
$dumpfile("full_adder.vcd"); endmodule
$dumpvars(0,testbench);
for(i=0;i<8;i=i+1)
begin
{a,b,c}=i; #5;
$display("T=%2d,a=%b,b=%b,c=%b,sum=%b,cout=%b",
$time,a,b,c,sum,cout);
end
#5 $finish;
end
endmodule

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 72

Department of EEE, BUET
72

36
 12/16/2022

Full Adder – EDA PlayGround - Output

• [2022-12-16 05:25:25 EST] iverilog '-Wall' design.sv testbench.sv &&

unbuffer vvp a.out
VCD info: dumpfile full_adder.vcd opened for output.
T= 5,a=0,b=0,c=0,sum=0,cout=0
T=10,a=0,b=0,c=1,sum=1,cout=0
T=15,a=0,b=1,c=0,sum=1,cout=0
T=20,a=0,b=1,c=1,sum=0,cout=1
T=25,a=1,b=0,c=0,sum=1,cout=0
T=30,a=1,b=0,c=1,sum=0,cout=1
T=35,a=1,b=1,c=0,sum=0,cout=1
T=40,a=1,b=1,c=1,sum=1,cout=1
Finding VCD file...
./full_adder.vcd
[2022-12-16 05:25:26 EST] Opening EPWave...
Done
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 73
Department of EEE, BUET
73

Full Adder – EDA PlayGround - Graphics

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 74

Department of EEE, BUET
74

37
 12/16/2022

16 Bit Adder – EDA PlayGround

https://www.edaplayground.com/x/3BES
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 75
Department of EEE, BUET
75

16 Bit Adder – EDA PlayGround - Code

Test Bench

Test Bench Main Code Main Code

module fulladder_testbench; // Code your design here
reg [15:0] a,b; module full_adder(sum,cout,in1, in2, cin); //16bit adder
reg c; input in1,in2,cin; module bit16_adder(sum,cout,a,b,cin);
wire [15:0] sum; output sum,cout; input [15:0]a,b;
wire carry; wire in1,in2,cin,sum,cout; input cin;
wire w1,w2,w3; output [15:0]sum;
bit16_adder uut xor(sum,in1,in2,cin); output cout;
(.sum(sum),.cout(carry),.a(a),.b(b),.cin(c)); and(w1,in1,in2);
and(w2,in2,cin); wire [15:0]a,b,sum;
initial and(w3,in1,cin); wire cin,cout;
begin or(cout,w1,w2,w3);
$monitor("time=%d:%d + %d + %d = %d, endmodule wire [2:0]c;
carry = %b\n",$time,a,b,c,sum,carry);
#10 a=16'h0000;b=16'h0000;c=0; //4bit adder bit4_adder fa0(sum[3:0],c[0],a[3:0],b[3:0],cin);
#10 a=16'h0111;b=16'h1110;c=0; module bit4_adder(sum,cout,a,b,cin); bit4_adder fa1(sum[7:4],c[1],a[7:4],b[7:4],c[0]);
#10 a=16'h1111;b=16'h1111;c=0; input [3:0]a; bit4_adder fa2(sum[11:8],c[2],a[11:8],b[11:8],c[1]);
#10 a=16'h0010;b=16'h1000;c=0; input [3:0]b; bit4_adder fa3(sum[15:12],cout,a[15:12],
#10 a=16'h0110;b=16'h0110;c=0; input cin; b[15:12],c[2]);
#10 a=16'h0001;b=16'h0010;c=0; output [3:0]sum;
#10 a=16'h0000;b=16'h1111;c=0; output cout; endmodule
#10 a=16'h1000;b=16'h1000;c=0; wire [3:0]a;
#10 wire [3:0]b;
$stop; wire [2:0]c;
end wire [3:0]sum;
endmodule wire cout;
full_adder fa0(sum[0], c[0], a[0], b[0], cin);
full_adder fa1(sum[1], c[1], a[1], b[1], c[0]);
full_adder fa2(sum[2], c[2], a[2], b[2], c[1]);
EEE 303 – Digital Electronics full_adder
endmodule
fa3(sum[3], cout, a[3], b[3], c[2]);
Dr. Sajid Muhaimin Choudhury 76
Department of EEE, BUET
76

38
 12/16/2022

16 Bit Adder – EDA PlayGround - Output

• time= 0: x + x + x = x, carry = x

time= 10: 0 + 0 + 0 = 0, carry = 0

time= 20: 273 + 4368 + 0 = 4641, carry = 0

time= 30: 4369 + 4369 + 0 = 8738, carry = 0

time= 40: 16 + 4096 + 0 = 4112, carry = 0

time= 50: 272 + 272 + 0 = 544, carry = 0

time= 60: 1 + 16 + 0 = 17, carry = 0

time= 70: 0 + 4369 + 0 = 4369, carry = 0

time= 80: 4096 + 4096 + 0 = 8192, carry = 0

** VVP Stop(0) **
** Flushing output streams.
** Current simulation time is 90 ticks.

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 77

Department of EEE, BUET
77

39