Arceo Experiment 5 Logics
Arceo Experiment 5 Logics
Experiment No. 5
NAND GATE
Submitted By:
Arceo Jr., Zuedy G.
BSEE - 3F
Instructor:
Engr. Heronafine De Guzman
ELECTRICAL DEPARTMENT
[DIGITAL ELECTRONICS]
Experiment No. 5
NAND GATE
I. OBJECTIVES:
1. To examine the characteristics and operation of a TTL NAND gate.
2. To implement NAND function using combination of AND and NOT gates.
ELECTRICAL DEPARTMENT
[DIGITAL ELECTRONICS]
IV. PROCEDURE:
1. Construct the circuit shown in Fig. A.
2. Wire the NAND gate to each input combination shown in truth table A.1,
observe itsoutput, and record each in the truth table.
3. Using the same circuit as shown in Fig. A, complete truth tables A.2 and A.3
4. Construct the circuit shown in Fig. B.
5. Wire the circuit to each input combination shown in truth table B, observe its
output,and record each in the truth table.
ELECTRICAL DEPARTMENT
[DIGITAL ELECTRONICS]
0 hang 1 hang 0 1
1 hang 0 hang 1 0
Truth Table B
B A Y
0 0 1
0 1 1
1 0 1
1 1 0
ELECTRICAL DEPARTMENT
[DIGITAL ELECTRONICS]
V. QUESTIONS:
1. What is the equivalent of floating input of a NAND gate?
• The Logic NAND Gate is the reverse or “Complementary” form of the
AND gate.
2. What is the Boolean expression of the circuit shown in Fig. B?
• A . B = A.B = Y
3. What are the 2 ways that must be done on a three-input NAND gate
for it to function as a two-input NAND gate?
A. short any of two inputs.
B. Connect one of input to Vcc
C. CONCLUSION:
ELECTRICAL DEPARTMENT