Scribd
Upload
398 views

FloorPlan Questions

The document contains 40 questions related to floorplanning, inputs required for floorplanning, checks performed during floorplanning, LEF/SDC files, aspect ratio, block sizing based on utilization, placement of macros and decap cells, power/voltage regions, level shifters, power switches, fillers, vias, timing checks, and views in ICC2. Key aspects addressed include inputs like LEF/SDC files, checks on the netlist, impact of technology on floorplanning, purpose of cells like TAP and decap, guidelines for defining power/voltage regions, and differences between views in ICC2.

Uploaded by

nagendra babu
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
398 views

FloorPlan Questions

The document contains 40 questions related to floorplanning, inputs required for floorplanning, checks performed during floorplanning, LEF/SDC files, aspect ratio, block sizing based on utilization, placement of macros and decap cells, power/voltage regions, level shifters, power switches, fillers, vias, timing checks, and views in ICC2. Key aspects addressed include inputs like LEF/SDC files, checks on the netlist, impact of technology on floorplanning, purpose of cells like TAP and decap, guidelines for defining power/voltage regions, and differences between views in ICC2.

Uploaded by

nagendra babu
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 1

1. What are all the inputs needed to Start Floorplan activities?

2. What kind of sanity checks will be done at Floorplan ?


3. What is the LEF and .libs ?
4. Timing Information (SDC and. libs) are mandatory to start Floorplan?
5. What is the aspect Ratio?
6. Is the aspect Ratio is technology dependent?
7. How to create Block size based on Utilization?
8. Are Block X and Y dependent upon the Aspect Ratio?
9. Is utilization will impact the Block Size?
10. What is the purpose of TAP, END CAP and DECAP cells?
11. What are the different types of checks will do for Netlist?
12. Is really technologies (14nm/7nm) will impact the floor Plan?
13. What is the difference between Flip Chip Vs Wire bound designs?
14. What do you mean by latch up?
15. How will TAP cells solve the latch-up problem?
16. How do you create power / voltage regions?
17. Are any guidelines to follow to define the Power / Voltage regions?
18. What is the function of Level Shifter, ISOLATION and power switch cells?
19. What is the difference Between Voltage region and Power domain?
20. What are the different types of Level Shifter?
21. What is the purpose of Power switch cells usage?
22. Really required dual power supply for level shifters?
23. Where do we keep Decap cells?
24. Is Macro's cannot keep middle of the design?
25. What kind of rules will follow for macro-Placement?
26. What is DEF? What kind of information it contains?
27. What kind of checks will you be done after macro placement?
28. How do verify our Power / Voltage region is properly created are not?
29. Why do we keep some space near IO's?( Near IO ports)
30. What is the purpose of filler cells?
31. Area of logical design is X , what is the block area with 50% utilization?
32. What is the difference between single cut via Vs Multi cut vias?
33. How do verify power plan is correct are not?
34. What kind of power checks will be done at Floorplan?
35. How do we make sure the Floorplan is correct are not?
36. Zero RC timing will check at Floor Plan?
37. How to decide the memory channel at Floor Plan?
38. What is poly pitch?
39. What is the placement grid?
40. What is the difference between abstract view Vs Design View (ICC2)

You might also like