DDR SDRAM

Double Data Rate Synchronous Dynamic Random-Access Memory (DDR

SDRAM) is a double data rate (DDR) synchronous dynamic random-access
DDR SDRAM
memory (SDRAM) class of memory integrated circuits used in computers. DDR Double Data Rate Synchronous
SDRAM, also retroactively called DDR1 SDRAM, has been superseded by Dynamic Random-Access
DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM and DDR5 SDRAM. None Memory
of its successors are forward or backward compatible with DDR1 SDRAM,
meaning DDR2, DDR3, DDR4 and DDR5 memory modules will not work in
DDR1-equipped motherboards, and vice versa.

Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface
makes higher transfer rates possible by more strict control of the timing of the
electrical data and clock signals. Implementations often have to use schemes such
as phase-locked loops and self-calibration to reach the required timing
accuracy.[4][5] The interface uses double pumping (transferring data on both the
rising and falling edges of the clock signal) to double data bus bandwidth without
a corresponding increase in clock frequency. One advantage of keeping the clock
frequency down is that it reduces the signal integrity requirements on the circuit
board connecting the memory to the controller. The name "double data rate"
refers to the fact that a DDR SDRAM with a certain clock frequency achieves
nearly twice the bandwidth of a SDR SDRAM running at the same clock
frequency, due to this double pumping.

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate
(in bytes/s) of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits Comparison of DDR modules for
transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, desktop PCs (DIMM).
DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

Contents
History
Specification Front and back of a 1GB DDR-400
Modules RAM module for desktop PCs
Chip characteristics (DIMM)
Double data rate (DDR) SDRAM specification
Developer Samsung[1][2][3]
Organization
JEDEC
Generations
Mobile DDR Type Synchronous
dynamic random-
See also access memory
References Generations DDR2
External links
DDR3
DDR4
History DDR5
Release DDR: 1998
In the late 1980s IBM had built DRAMs using a dual-edge clocking feature and date DDR2: 2003
presented their results in the International Solid-State Circuits Convention in
1990.[6][7] DDR3: 2007
DDR4: 2014
 Samsung demonstrated the first DDR DDR5: 2020
memory prototype in 1997,[1] and
Specifications
released the first commercial DDR
SDRAM chip (64  Mbit) in June Voltage DDR: 2.5/2.6
1998,[8][2][3] followed soon after by DDR2: 1.8
Hyundai Electronics (now SK Hynix)
DDR3: 1.5/1.35
the same year.[9] The development of
DDR began in 1996, before its DDR4: 1.2/1.05
A Samsung DDR SDRAM 64 Mbit specification was finalized by JEDEC in DDR5: 1.1
chip [10]
June 2000 (JESD79). JEDEC has set
standards for data rates of DDR SDRAM, divided into two parts. The first
specification is for memory chips, and the second is for memory modules. The
first retail PC motherboard using DDR SDRAM was released in August 2000.[11]

Specification

Modules

To increase memory capacity and bandwidth, chips are combined on a module. Single generic DDR memory module
For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed
in parallel. Multiple chips with the common address lines are called a memory
rank. The term was introduced to avoid confusion with chip internal rows and
banks. A memory module may bear more than one rank. The term sides would
also be confusing because it incorrectly suggests the physical placement of chips
on the module. All ranks are connected to the same memory bus (address + data).
The chip select signal is used to issue commands to specific rank.

Adding modules to the single memory bus creates additional electrical load on its
drivers. To mitigate the resulting bus signaling rate drop and overcome the
memory bottleneck, new chipsets employ the multi-channel architecture.

Four DDR RAM slots

Corsair DDR-400 memory with heat

spreaders
 Physical DDR layout

Comparison of memory modules for

portable/mobile PCs (SO-DIMM)

Comparison of DDR SDRAM standards

Name Chip Bus Timings

Clock Cycle Clock CL- CAS Voltage

time Transfer Bandwidth TRCD- (V)
Standard Type Module rate rate latency
[12] rate (MT/s) (MB/s)
(MHz) (ns) (MHz) TRP (ns)

PC-
DDR-200 100 10 100 200 1600 2-2-2 20
1600

PC-
DDR-266 1331⁄3 7.5 1331⁄3 266.67 21331⁄3 2.5-3-3 18.75 2.5±0.2
2100

PC-
DDR-333 1662⁄3 6 1662⁄3 3331⁄3 26662⁄3 2.5-3-3 15
2700

A 2.5-3-3 12.5
PC-
DDR-400 B 200 5 200 400 3200 3-3-3 15 2.6±0.1
3200
C 3-4-4 15

Note: All above listed are specified by JEDEC as JESD79F.[13] All RAM data rates in-between or above these listed
specifications are not standardized by JEDEC – often they are simply manufacturer optimizations using tighter tolerance
or overvolted chips. The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.

There is no architectural difference between DDR SDRAM modules. Modules are instead designed to run at different
clock frequencies: for example, a PC-1600 module is designed to run at 100 MHz, and a PC-2100 is designed to run at
133 MHz. A module's clock speed designates the data rate at which it is guaranteed to perform, hence it is guaranteed to
run at lower (underclocking) and can possibly run at higher (overclocking) clock rates than those for which it was
made.[14]

DDR SDRAM modules for desktop computers, dual in-line memory modules (DIMMs), have 184 pins (as opposed to
168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number
of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, SO-DIMMs, have 200
pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and
care must be taken during insertion if unsure of a correct match. Most DDR SDRAM operates at a voltage of 2.5  V,
compared to 3.3  V for SDRAM. This can significantly reduce power consumption. Chips and modules with DDR-
400/PC-3200 standard have a nominal voltage of 2.6 V.

JEDEC Standard No. 21–C defines three possible operating voltages for 184 pin DDR, as identified by the key notch
position relative to its centreline. Page 4.5.10-7 defines 2.5V (left), 1.8V (centre), TBD (right), while page 4.20.5–40
nominates 3.3V for the right notch position. The orientation of the module for determining the key notch position is with
52 contact positions to the left and 40 contact positions to the right.

Increasing operating voltage slightly can increase maximum speed, at the cost of higher power dissipation and heating,
and at the risk of malfunctioning or damage.

Capacity
Number of DRAM devices
The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules.
Chips can occupy one side (single sided) or both sides (dual sided) of the module. The maximal
number of chips per DDR module is 36 (9×4) for ECC and 32 (8x4) for non-ECC.
ECC vs non-ECC
Modules that have error-correcting code are labeled as ECC. Modules without error correcting code are
labeled non-ECC.
Timings
CAS latency (CL), clock cycle time (tCK), row cycle time (tRC), refresh row cycle time (tRFC), row active
time (tRAS).
Buffering
Registered (or buffered) vs unbuffered.
Packaging
Typically DIMM or SO-DIMM.
Power consumption
A test with DDR and DDR2 RAM in 2005 found that average power consumption appeared to be of the
order of 1–3 W per 512 MB module; this increases with clock rate and when in use rather than
idling.[15] A manufacturer has produced calculators to estimate the power used by various types of
RAM.[16]

Module and chip characteristics are inherently linked.

Total module capacity is a product of one chip's capacity and the number of chips. ECC modules multiply it by 8 ⁄9
because they use 1 bit per byte (8 bits) for error correction. A module of any particular size can therefore be assembled
either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.

DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip
and number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently, a
module with a greater number of chips or using ×8 chips instead of ×4 will have more ranks.

Example: Variations of 1 GB PC2100 registered DDR SDRAM module with ECC

Module size (GB) Number of chips Chip size (Mbit) Chip organization Number of ranks

1 36 256 64M×4 2

1 18 512 64M×8 2

1 18 512 128M×4 1
This example compares different real-world server memory modules with a common size of 1 GB. One should definitely
be careful buying 1  GB memory modules, because all these variations can be sold under one price position without
stating whether they are ×4 or ×8, single- or dual-ranked.

There is a common belief that number of module ranks equals number of sides. As above data shows, this is not true. One
can also find 2-side/1-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on
single side ×8 each, but it is unlikely such a module was ever produced.

Chip characteristics

DRAM density
Size of the chip is measured in megabits. Most motherboards
recognize only 1 GB modules if they contain 64M×8 chips (low
density). If 128M×4 (high density) 1 GB modules are used, they
most likely will not work. The JEDEC standard allows 128M×4 only
for registered modules designed specifically for servers, but some
generic manufacturers do not comply.[17]
Organization
The notation like 64M×4 means that the memory matrix has 64 The die of a Samsung DDR-SDRAM
million (the product of banks x rows x columns) 4-bit storage 64MBit package
locations. There are ×4, ×8, and ×16 DDR chips. The ×4 chips
allow the use of advanced error correction features like Chipkill,
memory scrubbing and Intel SDDC in server environments, while the ×8 and ×16 chips are somewhat
less expensive. x8 chips are mainly used in desktops/notebooks but are making entry into the server
market. There are normally 4 banks and only one row can be active in each bank.

Double data rate (DDR) SDRAM specification

From Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee
JC-42.3 on DRAM Parametrics.

Standard No. 79 Revision Log:

Release 1, June 2000

Release 2, May 2002
Release C, March 2003 – JEDEC Standard No. 79C.[18]

"This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data
interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will
subsequently be expanded to formally apply to x32 devices, and higher density devices as well."

Organization

PC3200 is DDR SDRAM designed to operate at 200  MHz using DDR-400 chips with a bandwidth of 3,200  MB/s.
Because PC3200 memory transfers data on both the rising and falling clock edges, its effective clock rate is 400 MHz.

1 GB PC3200 non-ECC modules are usually made with 16 512 Mbit chips, 8 on each side (512 Mbits × 16 chips) / (8
bits (per byte)) = 1,024 MB. The individual chips making up a 1 GB memory module are usually organized as 226 8-bit
words, commonly expressed as 64M×8. Memory manufactured in this way is low-density RAM and is usually
compatible with any motherboard specifying PC3200 DDR-400 memory.[19]

Generations
DDR (DDR1) was superseded by DDR2 SDRAM, which had modifications for higher clock frequency and again
doubled throughput, but operates on the same principle as DDR. Competing with DDR2 was Rambus XDR DRAM.
DDR2 dominated due to cost and support factors. DDR2 was in turn superseded by DDR3 SDRAM, which offered
higher performance for increased bus speeds and new features. DDR3 has been superseded by DDR4 SDRAM, which
was first produced in 2011 and whose standards were still in flux (2012) with significant architectural changes.

DDR's prefetch buffer depth is 2 (bits), while DDR2 uses 4. Although the effective clock rates of DDR2 are higher than
DDR, the overall performance was not greater in the early implementations, primarily due to the high latencies of the first
DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.[20]

Memory manufacturers stated that it was impractical to mass produce DDR1 memory with effective transfer rates in
excess of 400 MHz (i.e. 400 MT/s and 200 MHz external clock) due to internal speed limitations. DDR2 picks up where
DDR1 leaves off, utilizing internal clock rates similar to DDR1, but is available at effective transfer rates of 400 MHz and
higher. DDR3 advances extended the ability to preserve internal clock rates while providing higher effective transfer rates
by again doubling the prefetch depth.

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as 16 banks, 4 bank groups
with 4 banks for each bank group for ×4/×8 and 8 banks, 2 bank groups with 4 banks for each bank group for ×16
DRAM. The DDR4 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch
architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write operation for the DDR4 SDRAM consists of a single 8n-bit-wide 4-clock data transfer at the internal
DRAM core and 8 corresponding n-bit-wide half-clock-cycle data transfers at the I/O pins.[21]

RDRAM was a particularly expensive alternative to DDR SDRAM, and most manufacturers dropped its support from
their chipsets. DDR1 memory's prices substantially increased from Q2 2008, while DDR2 prices declined. In January
2009, 1 GB DDR1 was 2–3 times more expensive than 1 GB DDR2.
 Comparison of DDR SDRAM generations

Name Chip Bus Pins

Release Clock Cycle Clock Transfer Voltage
year Pre- Bandwidth (V) SO- Micro-
Gen Standard rate time rate rate DIMM
fetch (MB/s) DIMM DIMM
(MHz) (ns) (MHz) (MT/s)

DDR-200 100 10 100 200 1600

DDR-266 133 7.5 133 266 21331⁄3 2.5

DDR 1998 2n 184 200 172
DDR-333 1662⁄3 6 1662⁄3 333 26662⁄3
DDR-400 200 5 200 400 3200 2.6

DDR2-
100 10 200 400 3200
400

DDR2-
1331⁄3 7.5 2662⁄3 5331⁄3 42662⁄3
533

DDR2-
DDR2 2003 1662⁄3 6 4n 3331⁄3 6662⁄3 53331⁄3 1.8 240 200 214
667

DDR2-
200 5 400 800 6400
800

DDR2-
2662⁄3 3.75 5331⁄3 10662⁄3 85331⁄3
1066

DDR3-
100 10 400 800 6400
800

DDR3-
1331⁄3 7.5 5331⁄3 10662⁄3 85331⁄3
1066

DDR3-
1662⁄3 6 6662⁄3 13331⁄3 10662⁄3
1333
DDR3 2007 8n 1.5/1.35 240 204 214
DDR3-
200 5 800 1600 12800
1600

DDR3-
2331⁄3 4.29 9331⁄3 18662⁄3 149331⁄3
1866

DDR3-
2662⁄3 3.75 10662⁄3 21331⁄3 170662⁄3
2133

DDR4-
200 5 800 1600 12800
1600

DDR4-
2331⁄3 4.29 9331⁄3 18662⁄3 149331⁄3
1866

DDR4-
2662⁄3 3.75 10662⁄3 21331⁄3 170662⁄3
2133

DDR4-
DDR4 2014 300 31⁄3 8n 1200 2400 19200 1.2/1.05 288 260 -
2400

DDR4-
3331⁄3 3 13331⁄3 26662⁄3 213331⁄3
2666

DDR4-
3662⁄3 2.73 14662⁄3 29331⁄3 234662⁄3
2933

DDR4-
400 2.5 1600 3200 25600
3200
 DDR5-
200 5 1600 3200 25600
3200

DDR5-
225 4.44 1800 3600 28800
3600

DDR5-
250 4 2000 4000 32000
4000

DDR5-
300 31⁄3 2400 4800 38400
4800

DDR5-
3121⁄2 3.2 2500 5000 40000
5000
DDR5 2020 16n 1.1 288 262
DDR5- 1
320 3 ⁄8 2560 5120 40960
5120

DDR5-
3331⁄3 3 26662⁄3 53331⁄3 42662⁄3
5333

DDR5-
350 2.86 2800 5600 44800
5600

DDR5-
400 2.5 3200 6400 51200
6400

DDR5-
450 2.22 3600 7200 57600
7200

Mobile DDR

MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable
electronic devices, like mobile phones, handhelds, and digital audio players. Through techniques including reduced
voltage supply and advanced refresh options, Mobile DDR can achieve greater power efficiency.

See also
Fully buffered DIMM
ECC memory, a type of computer data storage
List of device bandwidths
Serial presence detect

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External links
Retrieved from "https://en.wikipedia.org/w/index.php?title=DDR_SDRAM&oldid=1114523008"

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