1)Difference between struct and union?

A. struct is a collection of different data types where separate memory will be created for
each datatype whereas for union only the highest memory datatype memory will be
created.

2)Explain Dynamic Array and its methods ?

A. A dynamic array is an unpacked array whose size can be set or changed at run time and
hence it quite different from a static array where size is predetermined during declaration of
the array . The default size is zero until it is assigned with new() constructor also array size is
continuously assigned.
Methods : new , size and delete.

3)Explain Associative Array and its methods?

A. An associative array ia an anpacked array datatype.
It does not have any storage allocated until it is used.
Methods : size or num, delete , exists, first, last, next, prev.

4)Explain about Strings and its methods?

A. It is a variable length ordered collection of characters. Number of characters in the
collection is known as length of the string. The memory space for string is dynamically
allocated.
Methods: Length , putc , getc , toupper , tolower , compare…

5) Explain about Queues and its methods?

A. Queue is a variable size , ordered collection of homogeneous (same type) un packed
elements. The main advantage is that one can add or remove element anywhere in a queue.
Methods: size,insert,delete,pop_front,pop_back,push_front,push_back.

5)virtual and pure virtual ?

A. There is nothing called pure virtual class but we have pure virtual methods
Virtual function is a function template in your base class that may be optionally overridden
in your derived class with new code.
Virtual pure function is a function template in your base class that MUST BE overridden in
your derived class with new code. It is even not allowed “end” keyword for example
endfunction/endtask.

6)Abstract class and virtual class ?

A. Abstract class is declared using virtual keyword, it doesn't have any implementation
methods can be declared in derived class.

7)What is static function ?

A. static function can access class by using class name directly without class instantiation by
using scope resolution with static function name.

8)Difference between struct and class ?

A . struct and class both are used to define bundle of data types.
struct is integral type when it is declared the necessary memory is allocated.
class is dynamic type memory allocation happens only when actual object of class is created.

9) Are SystemVerilog class members public or private by default ? Can Sv class

members be made private, if yes how?
A. SystemVerilog class members are public by-default.They can be made private by using a
local keyword for the variables inside a class.

10)Explain about coverages.

 Coverage is used to measure tested and untested portions of the design. Coverage is
defined as the percentage of verification objectives that have been met.
 There are two types of coverage
A) Code Coverage
B) Functional Coverage
 Code Coverage:
 Code coverage measures how much of the “design Code” is exercised.
 This includes the execution of design blocks, Number of Lines, Conditions, FSM,
Toggle and Path.
 The simulator tool will automatically extract the code coverage from the design
code.
 Functional Coverage:
 Functional coverage is a user-defined metric that measures how much of the design
specification has been exercised in verification.
 There are two types of functional coverage,
 Data-oriented Coverage – Checks combinations of data values have occurred. We
can get Data-oriented coverage by writing Coverage groups, coverage points and
also by cross coverage
 Control-oriented Coverage – Checks whether sequences of behaviors have occurred.
We can get assertion coverage by writing System Verilog Assertions

11) What is the difference between $display, $write, $monitor and $strobe in
SystemVerilog?
A. 1) $display : Print the values immediately when executed.
2) $strobe : Print the values at the end of the current timestep.
3) $monitor : Print the values at the end of the current timestep if any values
change. If $monitor is called more than once, the last call will override previous one.
 4) $write : This is same as $display but doesn't terminate with a newline (\n).

12) Regions of sv
A. Preponed ,Active, Inactive, NBA, Observed, Re-active, Re-inactive,Re-NBA, Postpned

13) what is meant by sequence_item,sequence ,sequencer and their purpose

in UVM ?
A. Sequence_item : which consist all the data variable or port variable which are used in
design
Sequence: which is used to generate the sequence_items
Sequencer : its used to route the sequences_item which are generated inside the
sequence .

14) What are the phases in UVM

A. UVM uses standard phases to order the major steps that take place during simulation.
There are three groups of phases, which are executed in the following order.
1. Build phases - In the build phases; the testbench is configured and constructed. It
has following sub-phases which are all implemented as virtual methods in
uvm_component base class.
1) build_phase()
2) connect_phase()
3) end_of_elaboration()
2. Run time phases - These phases can consume time and this is where most of the
test execution happens.
1) start_of_simulation()
2) run_phase()
The run_phase() is further divided into 12 sub-phases as below:
1) pre_reset
2) reset
3) post_reset
4) pre_configure
5) configure
6) post_configure
7) pre_main
8) main
9) post_main
10) pre_shutdown
11) shutdown
12) post_shutdown
 3. Clean up phase - This phase execute after the test ends and is used to collect, and
report results and statistics from the test. This consists of following sub phases:
1) extract()
2) check()
3) report()
4) final()

15) What are the different arbitration mechanisms available for a sequencer?
A. 1) SEQ_ARB_FIFO (Default if none specified). If this arbitration mode is specified, then
the sequencer picks sequence items in a FIFO order from all sequences running on the
sequencer. For Example: if seq1, seq2 and seq3 are running on a sequencer, it will pick an
item from seq1 first, followed by seq2, and then seq3 if available, and continue.
2) SEQ_ARB_WEIGHTED: If this arbitration mode is selected, sequence items from the
highest priority sequence are always picked first until none available, then the sequence
items from next priority sequence, and so on. If two sequences have equal priority, then the
items from them are picked in a random order.
3) SEQ_ARB_RANDOM: If this arbitration mode is selected, sequence items from different
sequences are picked in a random order by ignoring all priorities.
4) SEQ_ARB_STRICT_FIFO: This is similar to SEQ_ARB_WEIGHTED except that if two
sequences have same priority, then the items from those sequences are picked in a FIFO
order rather than in a random order.
5) SEQ_ARB_STRICT_RANDOM: This is similar to SEQ_ARB_RANDOM except that the
priorities are NOT ignored.The items are picked randomly from sequences with highest
priority first followed by next and in that order.
6) SEQ_ARB_USER: This algorithm allows a user to define a custom algorithm for arbitration
between sequences.This is done by extending the uvm_sequencer class and overriding the
user_priority_arbitration() method.

16) What is meant by factory override?

A. The UVM factory allows a class to be substituted with another derived class at the point
of construction. This can be useful for changing the behaviour of a test bench by substituting
one class for another without having the need to edit or re-compile the test bench code.

17) what are types of factory overriding?

A. type override:- override all the objects of a particular type.
inst override:- override a type within a particular instance.
18) What is sequence arbitration?
A. Multiple sequences can interact concurrently with a driver connected to a single
interface. Sequencer supports an arbitration mechanism to ensure that at any point of time
only one sequence has access to the driver.

19)Explain the HREADY signal in AHB?

A. If HREADY signal is high, data phase is finished immediately within one clock. HREADY is
the only signal can extend the address and data phases, when it is low.

20)What is early burst termination in AHB?

A. Bursts can be early terminated either as a result of the Arbiter removing the HGRANT
to a master part way through a burst, or after a slave returns a Non-okay response to any
beat of a burst.

21)What are advantages of TLM?

A. Higher level abstraction.
Reusable, plug and play connections.
Maintainability.
Less code
Easy to implement.
Faster simulation.
Can be used for reference model development.
Connection is between port and exports not in component.
These are parameterized by xtn class.

22)Tell me about HTRANS Signal?

A. This signal indicates the type of transfer for AHB Protocol:
IDLE(00)
BUSY(01)
NON-SEQ(10)
SEQ(11)