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Testbench For OR Gate

This document contains the code for a testbench that tests a 4-bit ALU component. It defines the component being tested, declares signals to connect the inputs and outputs, and contains a process that applies different input patterns and asserts the expected output values are produced. It also contains code for 3 different implementations of a 4-bit ALU - one using a generic package, one using a case statement, and one using an if/else statement.

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Mae Zel
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
25 views

Testbench For OR Gate

This document contains the code for a testbench that tests a 4-bit ALU component. It defines the component being tested, declares signals to connect the inputs and outputs, and contains a process that applies different input patterns and asserts the expected output values are produced. It also contains code for 3 different implementations of a 4-bit ALU - one using a generic package, one using a case statement, and one using an if/else statement.

Uploaded by

Mae Zel
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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-- Testbench for OR gate

library IEEE;
use IEEE.std_logic_1164.all;
 
entity testbench is
-- empty
end testbench; 
architecture tb of testbench is
-- DUT component
component ALU_74381IC is
    Port ( 
        -- 4-bit A, B, F0 - F3 Inputs
        A, B : in  STD_LOGIC_VECTOR(3 downto 0);
        F : in  STD_LOGIC_VECTOR(2 downto 0);
        -- 4-bit Y Output
        Y : out  STD_LOGIC_VECTOR (3 downto 0);
        C : out  STD_LOGIC
    );
end component;
signal c_out: std_logic;
signal a_in, b_in, q_out: std_logic_vector(3 downto 0);
signal f_in: std_logic_vector(2 downto 0);
begin
  -- Connect DUT
  DUT: ALU_74381IC port map(a_in, b_in, f_in, q_out, c_out);
  process
  begin
    a_in <= "1000";
    b_in <= "1001";
    f_in <= "100";
    wait for 1 ns;
    assert(q_out="0001" and c_out='0') report "Test 0" severity error;
    a_in <= "1000";
    b_in <= "1001";
    f_in <= "011";
    wait for 1 ns;
    assert(q_out="0001" and c_out='1') report "Test 1" severity error;
    
    a_in <= "1000";
    b_in <= "1001";
    f_in <= "110";
    wait for 1 ns;
    assert(q_out="1000" and c_out='0') report "Test 2" severity error;
    a_in <= "1000";
    b_in <= "1001";
    f_in <= "111";
    wait for 1 ns;
    assert(q_out="1111" and c_out='0') report "Test 3" severity error;
    a_in <= "0000";
    b_in <= "1111";
    f_in <= "100";
    wait for 1 ns;
    assert(q_out="1111" and c_out='0') report "Test 4" severity error;
    a_in <= "1111";
    b_in <= "1111";
    f_in <= "011";
    wait for 1 ns;
    assert(q_out="1110" and c_out='1') report "Test 5" severity error;
    a_in <= "0101";
    b_in <= "1001";
    f_in <= "010";
    wait for 1 ns;
    assert(q_out="1100" and c_out='0') report "Test 6" severity error;
    a_in <= "0101";
    b_in <= "1001";
    f_in <= "001";
    wait for 1 ns;
    assert(q_out="0100" and c_out='0') report "Test 7" severity error;
    a_in <= "0101";
    b_in <= "1001";
    f_in <= "101";
    wait for 1 ns;
    assert(q_out="1101" and c_out='0') report "Test 8" severity error;
    a_in <= "0101";
    b_in <= "1001";
    f_in <= "000";
    wait for 1 ns;
    assert(q_out="0000" and c_out='0') report "Test 9" severity error;
    a_in <= "0110";
    b_in <= "1010";
    f_in <= "011";
    wait for 1 ns;
    assert(q_out="0000" and c_out='1') report "Test 10" severity error;
    -- Clear inputs
    a_in <= "0000";
    b_in <= "0000";
    f_in <= "000";

    assert false report "Test done." severity note;


    wait;
  end process;
end tb;

library ieee;

use ieee.std_logic_1164.all;   

Entity alu is

Generic(N:natural);

port(A,B:in std_logic_vector(0 to N-1);

        S:in std_logic_vector(0 to  2);

        O:out std_logic_vector(0 to N-1)  

);
End alu;

Architecture alu1 of alu is

Begin 

     process(A,B)

     Begin

         if S="000" then O<='0'(:=others);

         elsif S="001" then O<=B-A;

         elsif S="010" then O<=A-B;    

         elsif S="011" then O<=A+B;

         elsif S="100" then O<=A xor B;

         elsif S="101" then O<=A or B;

         elsif S="110" then O<=A and B;

         else O<='1'(:=others);

         End if;

     End process;

End alu1;

library IEEE;

use IEEE.std_logic_1164.all;

ENTITY ALU_74381IC IS

PORT (

A, B : in STD_LOGIC_VECTOR(3 downto 0);

F : in STD_LOGIC_VECTOR(2 downto 0);


Y : out STD_LOGIC_VECTOR (3 downto 0);

C : out STD_LOGIC

);

END ALU_74381IC ;

ARCHITECTURE rtl OF ALU_74381IC IS

BEGIN

PROCESS ( F, A, B )

BEGIN F IS

WHEN "000" => Y <= "0000" ;

WHEN "001" => Y <= B - A ;

WHEN "010" => Y <= A - B ;

WHEN "011" => Y<= A + B ;

WHEN "100" => Y <= A XOR B ;

WHEN "101" => Y <= A OR B ;

WHEN "110" => Y <= A AND B ;

WHEN OTHERS =>

Y <= "1111" ;

END CASE ;

END PROCESS ;

END rtl ;

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY alu


ISPORT ( s : IN STD_LOGIC_VECTOR(2 DOWNTO 0) ;A, B : IN STD_LOGIC_VECTOR(3
DOWNTO 0) ;F : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;END alu ;ARCHITECTURE
Behavior OF alu ISBEGINPROCESS ( s, A, B )CASE s ISWHEN "000" => F <= "0000" ;WHEN
"001" => F <= B - A ;WHEN "010" => F <= A - B ;WHEN "011" => F <= A + B ;WHEN "100" => F
<= A XOR B ;WHEN "101" => F <= A OR B ;WHEN "110" => F <= A AND B ;WHEN OTHERS
=>F <= "1111" ;END CASE ;END PROCESS ;END Behavior ;

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