Chap 1 Masquage Logique

Chap 2 adresses des registres et Configuration des GPIOs

Chap3 Framework STM
void GPIO_init(GPIO_Typedef GPIOX, GPIO_InitStructureinit) else{
{ // crh
uint32_t mask_crl = 0, new_crl = 0, mask_crh = 0, new_crh = 0; mask_crh |= 0xf << (4(8-i));
for(int i=0; i<16; i++){ new_crh |= init->mode << (4(8-i)); }
int p = init->pin & (1 << i); }
if(p){ }
if(i < 8){ if(mask_crl){
// crl GPIOX->crl &= ~mask_crl;
mask_crl |= 0xf << (4i); new_crl |= init->mode << (4i); GPIOX->crl |= mask_crl;
} }
if(mask_crh){
GPIOX->crh &= ~mask_crh;
GPIOX->crh |= new_crh;
}}

void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* *---------------------------- GPIO CRL Configuration ------------------------*/

GPIO_InitStruct)
{ /* Configure the eight low port pins */
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) !=
pos = 0x00; 0x00)
uint32_t tmpreg = 0x00, pinmask = 0x00; {
tmpreg = GPIOx->CRL;
/* Check the parameters */ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); pos = ((uint32_t)0x01) << pinpos;
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); /* Get the port pins position */

/*----------------GPIO Mode Configuration ------------------*/ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;

if (currentpin == pos)
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & {
((uint32_t)0x0F); pos = pinpos << 2;
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10))
!= 0x00) /* Clear the corresponding low control register bits */
{
/* Check the parameters */ pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)) /* Write the mode configuration in the corresponding bits */
; tmpreg |= (currentmode << pos);
/* Output mode */ /* Reset the corresponding ODR bit */
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
} {
GPIOx->BRR = (((uint32_t)0x01) << pinpos);
}
else
{
 /* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
} } } }
GPIOx->CRL = tmpreg; }

/*-------GPIO CRH Configuration ------*/ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)

/* Configure the eight high port pins */ {
if (GPIO_InitStruct->GPIO_Pin > 0x00FF) GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
{ }
tmpreg = GPIOx->CRH; }
for (pinpos = 0x00; pinpos < 0x08; pinpos++) }
{ GPIOx->CRH = tmpreg;
pos = (((uint32_t)0x01) << (pinpos + 0x08)); }
/* Get the port pins position */ }
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding high control register bits */
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
}
/* Set the corresponding ODR bit */

Chap 4: interruptions
// Configurer les lignes EXTI 0 et 4 en mode interruption sur front montant
EXTI_InitStructure.EXTI_Line = EXTI_Line0 | EXTI_Line4;
EXTI0 & EXTI4 EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init ( &EXTI_InitStructure);
// Initialiser la structure (registres) relative au module EXTI

//Configuration NVIC
NVIC_InitTypeDef NVIC_InitStruct ;
// Déclarartion d’une structure de type NVIC_InitTypeDef
NVIC_InitStruct .NVIC_IRQChannel = FLASH_IRQn; // L’identifiant de l’interruption générée par le Flash. NVIC_InitStruct.
NVIC_IRQChannelPreemptionPriority = 15; // Le groupe ayant la priorité la plus basse.
NVIC_InitStruct. NVIC_IRQChannelSubPriority = 0; // un seul niveau d’interruption est disponible (0).
NVIC_InitStruct. NVIC_IRQChannelCmd = ENABLE; // autoriser l’interruption.
NVIC_Init (&NVIC_InitStruct); // Initialiser le NVIC avec les nouveaux paramètres

Chap 6: DMA
 // LES REGISTRES DMA1 …

//COMMENT SAVOIR LE NUM DU CANAL

Configuration des DMA par accès registre

//Les valeurs possibles pour la config du DMA (DMA_CRRx)
//Chap 7 : UART / USART
 roles :
DMA / USART / UART : responsable pour le transfert de donnée
DMA is used for large amount of data
USART/UART for small amount of data, send en serie
USART synchrone != UART async
//The right way to send/receive data using the USART
 // Configure USART2 to Transmit Data Using Interrupts // Configure USART1 to Receive and Store Data Using DMA Channel

void Config_USART2_TX_WITH_INT(void) void Config_USART1_RX_WITH_DMA(void)

{ {
/* Configure USART2 Tx (PA2) as alternate function /* Enable USART1 and DMA1 clocks */
push-pull */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 |
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; RCC_AHBPeriph_DMA1, ENABLE);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure); /* Configure USART1 Rx (PA10) as input floating */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
/* Enable USART2 clock */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, GPIO_Init(GPIOA, &GPIO_InitStructure);
ENABLE);
/* === USART2 configuration =======*/ /* ====== USART1 configuration ===========*/
/* USART2 configured as follow: /* - BaudRate = 9600 baud - Word Length = 8 Bits- One Stop Bit - No parity
- BaudRate = 9600 baud - Word Length = 8 Bits - One Stop - Receive enabled */
Bit- No parity USART_InitStructure.USART_BaudRate = 9600;
- Transmit enabled USART_InitStructure.USART_WordLength = USART_WordLength_8b;
*/ USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_BaudRate = 9600; USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_WordLength = USART_InitStructure.USART_HardwareFlowControl =
USART_WordLength_8b; USART_HardwareFlowControl_None;
USART_InitStructure.USART_StopBits = USART_InitStructure.USART_Mode = USART_Mode_Rx;
USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No; USART_Init(USART1, &USART_InitStructure);
USART_InitStructure.USART_HardwareFlowControl =
USART_HardwareFlowControl_None; /*Enable Rx DMA Request (s) on USART1*/
USART_InitStructure.USART_Mode = USART_Mode_Tx; USART_DMACmd(USART1, USART_DMAReq_Rx, ENABLE);
USART_Init(USART2, &USART_InitStructure);
/*Enable TX Interrupt (s) on USART2*/ /* Enable the USART1*/
// USART_ITConfig(USART2, USART_IT_TXE, ENABLE); USART_Cmd(USART1, ENABLE);
/* Enable the USARTx */ /* ========= DMA configuration ===============*/
USART_Cmd(USART2, ENABLE);
/* Enable and set USART2 Interrupt */ // DMAx channelx (UART1 RX) configuration */
NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn; // DMA_DeInit(DMA1_Channel5);
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&USART1->DR;
3; ;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)Receive_Buffer;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
NVIC_Init(&NVIC_InitStructure); DMA_InitStructure.DMA_BufferSize = 20;
} DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize =
DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;

DMA_Init(DMA1_Channel5, &DMA_InitStructure);
// /* Enable DMAx Channely Transfer Complete/ Half Transfer interrupts */
DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
/* Enable DMA1 Channelx transfer */
DMA_Cmd(DMA1_Channel5, ENABLE);
// /* Enable and set DMAx Channel y Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel5_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
 int i;
int txcount = 0; extern char Receive_Buffer[20];
extern char Transmit_Buffer[]; extern char Compare_Buffer[20];
void USART2_IRQHandler(void) void DMA1_Channel5_IRQHandler(void)
{ {
// Test on USART2 TX Interrupt /* Test on DMAx Channely Transfer Complete interrupt */
if (USART_GetITStatus(USART2, USART_IT_TXE)) if (DMA_GetITStatus(DMA1_IT_TC5))
{ {
// Code a ajouter pour assurer le fonctionnement désiré /* Code a ajouter pour assurer le fonctionnement désiré */
if (txcount < 8) if (stringCompare(Receive_Buffer, Compare_Buffer, 20))
{ {
USART_SendData(USART2, Transmit_Buffer[txcount]); GPIO_SetBits(GPIOA, GPIO_Pin_5);
txcount++; USART_ITConfig(USART2, USART_IT_TXE, ENABLE);
} }
else else
{ {
USART_ITConfig(USART1, USART_IT_TXE, DISABLE); GPIO_SetBits(GPIOA, GPIO_Pin_5);
} Delay(0xFFFFF);
} GPIO_ResetBits(GPIOA, GPIO_Pin_5);
} Delay(0xFFFFF);
GPIO_SetBits(GPIOA, GPIO_Pin_5);
Delay(0xFFFFF);
GPIO_ResetBits(GPIOA, GPIO_Pin_5);
Delay(0xFFFFF);
}
/* Clear DMAx Channely TC interrupt pending bit */
DMA_ClearITPendingBit(DMA1_IT_TC5);
}
}
Chap 6 POO
Exemple Code