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TD3 Solutions

This document provides VHDL code examples for implementing multiplexers with 2, 4, and 8 inputs. It includes code using parallel logic implementations, "when...else" selections, and "with...select" statements. The code examples demonstrate how to multiplex both single bit and vector inputs and outputs. Tables of truth for the 2, 4, and 8-input multiplexers are also provided.

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Nina Asoma
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98 views7 pages

TD3 Solutions

This document provides VHDL code examples for implementing multiplexers with 2, 4, and 8 inputs. It includes code using parallel logic implementations, "when...else" selections, and "with...select" statements. The code examples demonstrate how to multiplex both single bit and vector inputs and outputs. Tables of truth for the 2, 4, and 8-input multiplexers are also provided.

Uploaded by

Nina Asoma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Centre Universitaire de Tipaza Abdallah Morsli

Institut des sciences


Département D’Electronique
1ère année Master, Option: Instrumentation
Module: Électronique numérique avancée : VHDL – FPGA

TD 3 (Solutions): Fonctions Combinatoires complexes

Exercice 1:

Sel O
0 I0
1 I1

Table 1: Table de vérité

Code. 1: Implémentation parallèle (flot de données)


library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity Mux_2_1 is
Port ( I0 : in STD_LOGIC ;
I1 : in STD_LOGIC ;
Sel : in STD_LOGIC ;
O : out STD_LOGIC );
end Mux_2_1 ;

architecture Behavioral of Mux_2_1 is

begin
O <=(( not Sel ) and I0 ) or ( Sel and I1 );

end Behavioral ;

Code. 2: Implémentation (when ... else)


library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity Mux_2_1 is
Port ( I0 : in STD_LOGIC ;
I1 : in STD_LOGIC ;
Sel : in STD_LOGIC ;
O : out STD_LOGIC );
end Mux_2_1 ;

1 F.CHABNI
Centre Universitaire de Tipaza Abdallah Morsli
Institut des sciences
Département D’Electronique
1ère année Master, Option: Instrumentation
Module: Électronique numérique avancée : VHDL – FPGA
architecture Behavioral of Mux_2_1 is
begin
O <= I0 when Sel = ’0 ’ else I1 ;

end Behavioral ;

Code. 3: Implémentation (with ...select)


library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity Mux_2_1_select is
Port ( I0 : in STD_LOGIC ;
I1 : in STD_LOGIC ;
Sel : in STD_LOGIC ;
O : out STD_LOGIC );
end Mux_2_1_select ;

architecture Behavioral of Mux_2_1_select is


begin
with Sel select
O <= I0 when ’0 ’ , I1 when others ;
end Behavioral ;

2 F.CHABNI
Centre Universitaire de Tipaza Abdallah Morsli
Institut des sciences
Département D’Electronique
1ère année Master, Option: Instrumentation
Module: Électronique numérique avancée : VHDL – FPGA
Exercice 2:

Sel(1) Sel(0) O
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Table 2: Table de vérité

Code. 4: Implémentation parallèle (flot de données)


library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity Mux_4_1 is
Port ( I0 : in STD_LOGIC ;
I1 : in STD_LOGIC ;
I2 : in STD_LOGIC ;
I3 : in STD_LOGIC ;
Sel : in STD_LOGIC_VECTOR (1 downto 0);
O : out STD_LOGIC );
end Mux_4_1 ;

architecture Behavioral of Mux_4_1 is


signal O0 , O1 , O2 , O3 : STD_LOGIC ;
begin

O0 <= not Sel (0) and not Sel (1) and I0 ;


O1 <= Sel (0) and not Sel (1) and I1 ;
O2 <= not Sel (0) and Sel (1) and I2 ;
O3 <= Sel (0) and Sel (1) and I3 ;
O <= O0 or O1 or O2 or O3 ;
end Behavioral ;

Code. 5: Implémentation (when ... else)

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity Mux_4_1 is
Port ( I0 : in STD_LOGIC ;
I1 : in STD_LOGIC ;
I2 : in STD_LOGIC ;
I3 : in STD_LOGIC ;
Sel : in STD_LOGIC_VECTOR (1 downto 0);
O : out STD_LOGIC );
end Mux_4_1 ;

3 F.CHABNI
Centre Universitaire de Tipaza Abdallah Morsli
Institut des sciences
Département D’Electronique
1ère année Master, Option: Instrumentation
Module: Électronique numérique avancée : VHDL – FPGA
architecture Behavioral of Mux_4_1 is

begin

O <= I3 when Sel ="11" else


I2 when Sel ="10" else
I1 when sel ="01" else
I0 ;
end Behavioral ;

Code. 6: Implémentation (with ...select)


library IEEE ;

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity Mux_4_1 is
Port ( I0 : in STD_LOGIC ;
I1 : in STD_LOGIC ;
I2 : in STD_LOGIC ;
I3 : in STD_LOGIC ;
Sel : in STD_LOGIC_VECTOR (1 downto 0);
O : out STD_LOGIC );
end Mux_4_1 ;

architecture Behavioral of Mux_4_1 is

begin

with Sel select


O <= I3 when "11" ,
I2 when "10" ,
I1 when "01" ,
I0 when others ;

end Behavioral ;

4 F.CHABNI
Centre Universitaire de Tipaza Abdallah Morsli
Institut des sciences
Département D’Electronique
1ère année Master, Option: Instrumentation
Module: Électronique numérique avancée : VHDL – FPGA
Exercice 3:

Sel(1) Sel(0) O(3:0)


0 0 I0(3:0)
0 1 I1(3:0)
1 0 I2(3:0)
1 1 I3(3:0)

Table 3: Table de vérité

Code. 7: Implémentation parallèle (flot de données)

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity Mux_4_1 is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0));
end Mux_4_1 ;

architecture Behavioral of Mux_4_1 is


signal O0 , O1 , O2 , O3 : STD_LOGIC_VECTOR (3 downto 0) ;
begin

O0 (0) <= not Sel (0) and not Sel (1) and I0 (0);
O1 (0) <= Sel (0) and not Sel (1) and I1 (0);
O2 (0) <= not Sel (0) and Sel (1) and I2 (0);
O3 (0) <= Sel (0) and Sel (1) and I3 (0);
O (0) <= O0 (0) or O1 (0) or O2 (0) or O3 (0);

O0 (1) <= not Sel (0) and not Sel (1) and I0 (1);
O1 (1) <= Sel (0) and not Sel (1) and I1 (1);
O2 (1) <= not Sel (0) and Sel (1) and I2 (1);
O3 (1) <= Sel (0) and Sel (1) and I3 (1);
O (1) <= O0 (1) or O1 (1) or O2 (1) or O3 (1);

O0 (2) <= not Sel (0) and not Sel (1) and I0 (2);
O1 (2) <= Sel (0) and not Sel (1) and I1 (2);
O2 (2) <= not Sel (0) and Sel (1) and I2 (2);
O3 (2) <= Sel (0) and Sel (1) and I3 (2);
O (2) <= O0 (2) or O1 (2) or O2 (2) or O3 (2);

O0 (3) <= not Sel (0) and not Sel (1) and I0 (3);
O1 (3) <= Sel (0) and not Sel (1) and I1 (3);

5 F.CHABNI
Centre Universitaire de Tipaza Abdallah Morsli
Institut des sciences
Département D’Electronique
1ère année Master, Option: Instrumentation
Module: Électronique numérique avancée : VHDL – FPGA
O2 (3) <= not Sel (0) and Sel (1) and I2 (3);
O3 (3) <= Sel (0) and Sel (1) and I3 (3);
O (3) <= O0 (3) or O1 (3) or O2 (3) or O3 (3);
end Behavioral ;

Code. 8: Implémentation (when ... else)

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity Mux_4_1 is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0));
end Mux_4_1 ;

architecture Behavioral of Mux_4_1 is


begin
O <= I3 when Sel ="11" else
I2 when Sel ="10" else
I1 when Sel ="01" else
I0 ;
end Behavioral ;

Code. 9: Implémentation (with ...select)


library IEEE ;

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

library IEEE ;
use IEEE . STD_LOGIC_1164 . ALL ;

entity Mux_4_1 is
Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0);
I1 : in STD_LOGIC_VECTOR (3 downto 0);
I2 : in STD_LOGIC_VECTOR (3 downto 0);
I3 : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0));
end Mux_4_1 ;

architecture Behavioral of Mux_4_1 is

6 F.CHABNI
Centre Universitaire de Tipaza Abdallah Morsli
Institut des sciences
Département D’Electronique
1ère année Master, Option: Instrumentation
Module: Électronique numérique avancée : VHDL – FPGA
begin

with Sel select


O <= I3 when "11" ,
I2 when "10" ,
I1 when "01" ,
I0 when others ;

end Behavioral ;

7 F.CHABNI

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