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Assignment III VLSI

This document is an assignment for a VLSI Design course. It contains 12 questions related to topics in VLSI design including RC delay models, Cascode Voltage Switch Logic, linear delay models, pseudo NMOS and ganged CMOS gates, Elmore delay models, skewed gates, resettable latches, pass transistor circuits, D flip-flops, dynamic shift registers, dynamic CMOS logic and ratioless synchronous dynamic logic. Students are asked to answer all questions, which test various cognitive levels, and submit their responses by December 24th for a maximum of 10 marks.

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Akshaykumar Patil
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46 views

Assignment III VLSI

This document is an assignment for a VLSI Design course. It contains 12 questions related to topics in VLSI design including RC delay models, Cascode Voltage Switch Logic, linear delay models, pseudo NMOS and ganged CMOS gates, Elmore delay models, skewed gates, resettable latches, pass transistor circuits, D flip-flops, dynamic shift registers, dynamic CMOS logic and ratioless synchronous dynamic logic. Students are asked to answer all questions, which test various cognitive levels, and submit their responses by December 24th for a maximum of 10 marks.

Uploaded by

Akshaykumar Patil
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Jain College of Engineering, Belagavi

Department of Electronics and Communication Engineering

Assignment - III
Course Name: VLSI Design   Course Code: 18EC72
Semester : 7 A, B, C
th
  Maximum Marks : 10
Date: 17/12/2022   Submission Date: 24/12/2022

P
Q. No. Question CO RBT
O
Develop the RC delay model to compute the delay of the logic circuit and L1,L2
1 CO3 1,2 ,L3
calculate the delay of unit sized inverter driving another unit size inverter.
Explain Cascode Voltage Switch Logic (CVSL). Also realise two input AND / L1,L2
2 CO3 1,2 ,L3
NAND using CVSL.
Explain linear delay model. Compare the logical efforts of the following gates
with the help of schematic diagrams: L1,L2
3 CO3 1,2
i) Two input NAND gate ,L3
ii) Three input NOR gate
Explain
i) Pseudo nMOS L1,L2
4 CO3 1,2
ii) Ganged CMOS ,L3
With necessary circuit examples.
Explain tpdf and tpdr of a 3 input NAND gate if the output is loaded with h L1,L2
5 CO3 1,2 ,L3
identical gates. Use Elmore delay model.
L1,L2
6 Explain skewed gates with an example. CO3 1,2 ,L3
With necessary circuit diagrams, explain resettable latches with
L1,L2
7 i) Synchronous reset CO4 1,2 ,L3
ii) Asynchronous reset
Compute the output voltage Vout in the following pass transistor circuits.
Assume Vt = 0.7V.

L1,L2
8 CO4 1,2 ,L3
Circuit 1

Circuit 2
With necessary diagram, explain a D flipflop with two phase non L1,L2
9 CO4 1,2 ,L3
overlapping clocks.
With necessary circuit diagram explain 3 bit dynamic shift register with L1,L2
10 CO4 1,2 ,L3
depletion load.
Realize F= A 1 A 2 A 3+ B1 B 2 using dynamic CMOS logic. Also explain the L1,L2
11 CO4 1,2 ,L3
cascading problem in dynamic logic with necessary examples.
Explain the general structure of ratioless synchronous dynamic logic with L1,L2
12 CO4 1,2 ,L3
relevant diagram
Jain College of Engineering, Belagavi
Department of Electronics and Communication Engineering

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