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Atpg Scripts

The document contains commands for setting up and running simulations, ATPG, and fault analysis on a design called dig_top using EDA tools. It reads in design files from a library, compiles the design, runs DRC checks, adds fault models, runs ATPG to generate test patterns, and reports fault coverage. It also contains commands for path delay fault analysis.

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VENKATRAMAN
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© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
286 views

Atpg Scripts

The document contains commands for setting up and running simulations, ATPG, and fault analysis on a design called dig_top using EDA tools. It reads in design files from a library, compiles the design, runs DRC checks, adds fault models, runs ATPG to generate test patterns, and reports fault coverage. It also contains commands for path delay fault analysis.

Uploaded by

VENKATRAMAN
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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set_messages -log logs/run1a.log -replace set_messages -log logs/Lab2a.log -replace set_messages -log logs/Lab2b.

log -replace

set_build -black_box adc0808 set_netlist -max_errors 10 set_build -black_box adc0808

read_netlist read_netlist read_netlist


/tools/libraries/28nm/SAED32_EDK/lib/pll/verilog/ /tools/libraries/28nm/SAED32_EDK/lib/pll/verilog/ /tools/libraries/28nm/SAED32_EDK/lib/pll/verilog
PLL.v -library PLL.v -library /PLL.v -library

read_netlist read_netlist #read_netlist


/tools/libraries/28nm/SAED32_EDK/lib/sram/verilo /tools/libraries/28nm/SAED32_EDK/lib/sram/verilo /tools/libraries/28nm/SAED32_EDK/lib/sram/veri
g/saed32sram.v -library g/saed32sram.v -library log/saed32sram.v -library

read_netlist read_netlist read_netlist


/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt /tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt /tools/libraries/28nm/SAED32_EDK/lib/stdcell_hv
/verilog/saed32nm_hvt.v -library /verilog/saed32nm_hvt.v -library t/verilog/saed32nm_hvt.v -library

read_netlist read_netlist read_netlist


/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/ /tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/ /tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt
verilog/saed32nm_lvt.v -library verilog/saed32nm_lvt.v -library /verilog/saed32nm_lvt.v -library

read_netlist read_netlist read_netlist


/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/ /tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/ /tools/libraries/28nm/SAED32_EDK/lib/stdcell_rv
verilog/saed32nm.v -library verilog/saed32nm.v t/verilog/saed32nm.v -library

read_netlist inputs/dig_top_scan_inserted.v read_netlist input/dig_top_scan_inserted.v read_netlist input/dig_top_scan_inserted.v

run_build_model dig_top run_build_model dig_top

run_drc inputs/dig_top_scan_inserted.spf set_build -black_box adc0808 run_drc input/dig_top_scan_inserted.spf

add_faults -module clk_gate set_build -delete_unused_gates #Analyse scan chain blockage:

set_faults -report uncollapsed run_build_model dig_top #open gui using gui_start

report_faults -summary run_drc input/dig_top_scan_inserted.spf #The failing instance will be displayed in schematic
viewer,
report_faults -all > reports/report_faults.txt

set_faults -report collapsed #set_faults -model Stuck

report_faults -summary #add_faults -all

report_faults -all #report_faults –summary


set_messages -log logs/Lab2c.log -replace Lab 4A

set_build -black_box adc0808 set_messages -log logs/run_tdf.log -replace add_faults -all

read_netlist set_build -black_box adc0808 report_faults -summary


/tools/libraries/28nm/SAED32_EDK/lib/pll/verilog
read_netlist run_atpg -auto_compression
/PLL.v -library
/tools/libraries/28nm/SAED32_EDK/lib/pll/verilog
write_patterns outputs/dig_top_tdf.stil -format stil
read_netlist /PLL.v -library
-replace
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hv
read_netlist
t/verilog/saed32nm_hvt.v -library write_patterns outputs/dig_top_tdf_serial.stil -
/tools/libraries/28nm/SAED32_EDK/lib/sram/veri
format stil -serial -replace
read_netlist log/saed32sram.v -library
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lv write_faults outputs/dig_top_tdf_fault_list.rpt -all -
read_netlist
t/verilog/saed32nm_lvt.v -library replace
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hv
read_netlist t/verilog/saed32nm_hvt.v -library #coverage check
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rv
read_netlist #set_atpg -patterns 500000
t/verilog/saed32nm.v -library
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lv
read_netlist input/dig_top_scan_inserted.v t/verilog/saed32nm_lvt.v -library #run_atpg –auto

run_build_model dig_top read_netlist


/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rv
run_drc input/dig_top_scan_inserted.spf
t/verilog/saed32nm.v
set_faults -model Stuck
read_netlist input/dig_top_scan_inserted.v
add_faults -all
run_build_model dig_top
report_faults -summary
set_delay -launch_cycle system_clock -
set_atpg -patterns 100 nopi_changes

run_atpg #system_clock ----> LOC

write_patterns outputs/dig_top.stil -format stil - #last_shift ---> LOS


replace
#extra_shift ----> LOES
write_patterns outputs/dig_top_serial.stil -format
add_po_masks -all
stil -serial -replace
set_faults -model Transition
write_patterns outputs/dig_top_chain.stil -format
stil -serial -exclude atpg_patterns set_atpg -capture_cycles 2

set_atpg -patterns 100

run_drc input/dig_top_scan_inserted.spf
LAB 4B: Lab 4C

set_messages -log logs/run_lab4b.log -replace set_messages -log logs/pdf.log -replace

set_build -black_box adc0808 set_build -black_box adc0808

read_netlist
/tools/libraries/28nm/SAED32_EDK/lib/pll/verilog
read_netlist
/PLL.v -library
/tools/libraries/28nm/SAED32_EDK/lib/pll/verilog
/PLL.v -library read_netlist
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hv
read_netlist
t/verilog/saed32nm_hvt.v -library
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hv
t/verilog/saed32nm_hvt.v -library read_netlist
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lv
read_netlist
t/verilog/saed32nm_lvt.v -library
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lv
t/verilog/saed32nm_lvt.v -library read_netlist/tools/libraries/28nm/SAED32_EDK/
lib/stdcell_rvt/verilog/saed32nm.v
read_netlist
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rv read_netlist input/dig_top_scan_inserted.v
t/verilog/saed32nm.v
run_build_model dig_top
read_netlist input/dig_top_compr.v
run_drc input/dig_top_scan_inserted.spf
run_build_model dig_top
set_delay -nopi_changes
set_rules c4 warning
set_delay -nopo_measures
run_drc input/dig_top.spf
add_delay_paths pdf_paths
set_faults -model Stuck
set_faults -model path_delay
add_faults -all
add_faults -all
report_faults -summary
report_faults -summary
set_atpg -patterns 100
set_atpg -patterns 100
set_atpg -parallel_strobe_data_file
run_atpg -auto
outputs/dig_top_lab4b.psd -replace
report_faults -class AU
run_atpg -auto
write_patterns outputs/dig_top_pdf.stil -format stil
write_patterns outputs/dig_top_lab4b.stil -format
stil –replace write_faults outputs/dig_top_pdf_fault_list.rpt -all
-replace

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