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UNIT 5 RISC Architecture

RISC processors have simple instruction sets with simple addressing modes. Each RISC instruction engages a single word in memory and executes in one clock cycle. RISC architectures emphasize the use of registers over memory and have hardwired control units to speed up instruction execution. Common advantages of RISC processors include simpler instructions that execute faster, fewer instructions in the instruction set, and easier pipelining due to uniform instruction size.

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UNIT 5 RISC Architecture

RISC processors have simple instruction sets with simple addressing modes. Each RISC instruction engages a single word in memory and executes in one clock cycle. RISC architectures emphasize the use of registers over memory and have hardwired control units to speed up instruction execution. Common advantages of RISC processors include simpler instructions that execute faster, fewer instructions in the instruction set, and easier pipelining due to uniform instruction size.

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KESSAVAN.M ECE20
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Overview of RISC Processor

RISC is an abbreviation of Reduced Instruction Set Computer. RISC processor has ‘instruction
sets’ that are simple and have simple ‘addressing modes’. A RISC style instruction engages “one
word” in memory. Execution of the RISC instructions are faster and take one clock cycle per
instruction.

Although the forerunners of RISC computers were seen in 1960. But, due to the popularity of
CISC microprocessors which were implemented by the manufacturers in calculators, video
games, stereos, etc; RISC architecture was overshadowed. According to modern concept dates
RISC computers were particularly introduced in the 1980s.

RISC Processor Architecture (Block diagram)

RISC processor is implemented using the hardwired control unit. The hardwired control unit
produces control signals which regulate the working of processors hardware. RISC architecture
emphasizes on using the registers rather than memory.

This is because the registers are the ‘fastest’ available memory source. The registers are
physically small and are placed on the same chip where the ALU and the control unit are placed
on the processor. The RISC instructions operate on the operands present in processor’s registers.
Observe one thing here, we don’t have the “microprogram control store” or the “control
memory” like we have seen in the CISC architecture in our previous content.

It is just because all instructions in RISC are simple and execute one instruction per cycle. So,
here the instructions are hardwired and there is no need for control store. For each operation, we
will have as defined hardwire. Making an instruction hardwired is making a function or
operation in instruction permanent using connected circuits.

Advantages and Disadvantages of RISC Processor

Advantages of RISC Processor

1. RISC instructions are simpler machine instruction.


2. RISC instructions are hardwired to fasten the execution.
3. There are very fewer instructions in s RISC instruction set.
4. RISC instruction has simple addressing modes.
5. RISC instruction executes faster because most of instruction operates on processor register and
there is no need to access memory for each instruction.
6. It is easy to pipeline RISC instruction as all instruction is of fixed size and opcode and operand
are located in the same position in the word.
7. RISC instructions execute one instruction per clock cycle.
Disadvantages of RISC Processor

1. RISC instruction size is reduced but more instructions are required to perform an operation when
compared with CISC. So, we can say that the length of the program is increased.
2. The machine instructions are hardwired in RISC so, it would cost if any instruction needs
modification.
3. It finds is difficulty in processing complex instruction and complex addressing mode.
4. RISC instructions do not allow direct memory to memory transfer, it requires Load and Store
instructions to do so.

Examples of RISC processors

MIPS, SPARC, IBM POWER instruction set, Alpha, RISC-V, ARM architecture.

RISC and CISC Union: Hybrid Architecture

Features of RISC Processors:


The standard features of RISC processors are listed below:
1. RISC processors use a small and limited number of instructions.
RISC processors only support a small number of primitive and essential instructions. This puts
emphasis on software and compiler design due to the relatively simple instruction set.
2. RISC machines mostly uses hardwired control unit.
Most of the RISC processors are based on the hardwired control unit design approach. In
hardwired control unit, the control units use fixed logic circuits to interpret instructions and
generate control signals from them. It is significantly faster than its counterpart but are rather
inflexible.
3. RISC processors consume less power and have high performance.
RISC processors have been known to be heavily pipelined this ensures that the hardware
resources of the processor are utilized to a maximum giving higher throughput and also
consuming less power.
4. Each instruction is very simple and consistent.
Most instructions in a RISC instruction set are very simple that get executed in one clock cycle.

5. RISC processors use simple addressing modes.


RISC processors don’t have as many addressing modes and the addressing modes these
processors have are rather very simple. Most of the addressing modes are for register operations
and do not refer memory.
6. RISC instruction is of uniform fixed length.
The decision of RISC processor designers to provide simple addressing modes leads to uniform
length instructions. For example, instruction length increases if an operand is in memory as
opposed to in a register. a. This is because we have to specify the memory address as part of
instruction encoding, which takes many more bits. This complicates instruction decoding and
scheduling.
7. Large Number of Registers.
The RISC design philosophy generally incorporates a larger number of registers to prevent in
large amounts of interactions with memory
BASIC PERFORMANCE ISSUES IN PIPELINING
• Pipelining increases the CPU instruction throughput—the number of instructions completed per
unit of time-but it does not reduce the execution time of an individual instruction.
• The increase in instruction throughput means that a program runs faster and has lower total
execution time, even though no single instruction runs faster!
• In fact, it usually slightly increases the execution time of each instruction due to overhead in
the control of the pipeline.
• Pipeline overhead arises from the combination of pipeline register delay and clock skew.
• The pipeline registers add setup time, which is the time that a register input must be stable
before the clock signal that triggers a write occurs, plus propagation delay to the clock cycle.
• Clock skew, which is maximum delay between when the clock arrives at any two registers, also
contributes to the lower limit on the clock cycle.
• Once the clock cycle is as small as the sum of the clock skew and latch overhead, no further
pipelining is useful, since there is no time left in the cycle for useful work
• Although it is critical to ensure that instructions in the pipeline do not attempt to use the
hardware resources at the same time, we must also ensure that instructions in different stages of
the pipeline do not interfere with one another.
• This separation is done by introducing pipeline registers between successive stages of the
pipeline, so that at the end of a clock cycle all the results from a given stage are stored into a
register
Pipeline Conflicts
There are some factors that cause the pipeline to deviate its normal performance. Some of these
factors are given below:
1. Timing Variations
All stages cannot take same amount of time. This problem generally occurs in instruction
processing where different instructions have different operand requirements and thus
different processing time.
2. Data Hazards
When several instructions are in partial execution, and if they reference same data then the
problem arises. We must ensure that next instruction does not attempt to access data before
the current instruction, because this will lead to incorrect results.
3. Branching
In order to fetch and execute the next instruction, we must know what that instruction is. If
the present instruction is a conditional branch, and its result will lead us to the next
instruction, then the next instruction may not be known until the current one is processed.
4. Interrupts
Interrupts set unwanted instruction into the instruction stream. Interrupts effect the execution
of instruction.
5. Data Dependency
It arises when an instruction depends upon the result of a previous instruction but this result
is not yet available.

Advantages of Pipelining
 Instruction throughput increases.
 Increase in the number of pipeline stages increases the number of instructions executed
simultaneously.
 Faster ALU can be designed when pipelining is used.
 Pipelined CPU’s works at higher clock frequencies than the RAM.
 Pipelining increases the overall performance of the CPU.

Disadvantages of Pipelining
 Designing of the pipelined processor is complex.
 Instruction latency increases in pipelined processors.
 The throughput of a pipelined processor is difficult to predict.
 The longer the pipeline, worse the problem of hazard for branch instructions.

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