High Efficiency Power Converter with SiC Power MOSFETs

For Pulsed Power Applications

Ruxi Wang1, Juan Sabate1, Xiaohu Liu2, Krishna Mainali1
1. General Electric Global Research 2. Busek Co. Inc
Niskayuna, New York, 12308, USA 11 Tech Circle, Natick, MA, 01760, USA
Email: [email protected]

Abstract:-- This paper presents a high efficiency SiC power when compared with similarly rated Si counterparts.
converter in pulsed power applications. SiC Power However, even though the SiC device switching loss
MOSFETs have 7~10 times lower switching loss than
(@higher current) is much lower than the Silicon device,
Silicon counterparts. However, because of the large
depletion capacitance, the SiC device switching loss will be the SiC depletion capacitance is much higher than the
higher than silicon device at zero current. Therefore, loss silicon device with similar voltage rating which will
reduction method is proposed to further improve SiC make the silicon carbide power converter less efficient
gradient driver efficiency. A 2700V, 1300A SiC gradient
driver prototype is designed, fabricated and tested
when regulating very small current. This paper will focus
on increasing the SiC gradient driver efficiency in pulsed
Index Terms:-- Silicon Carbide, Pulsed Power, Low Stray power application where regulating very small load
Inductance, High Efficiency current is a common operating mode.

I. INTRODUCTION II. DEPLETION

CAPACITANCE OF SILICON
Pulsed power as shown in Figure 1 is a unique CARBIDE POWER MOSFET
technology that can compress energy into a short but Silicon power devices with higher breakdown voltages
intense burst to create extreme conditions without the have considerably high on-resistance per unit area. Thus,
demand for a very large energetic power source [1]. The IGBTs have been mainly used in devices with voltage of
pulsed power has been widely utilized in many 600V or higher. IGBTs achieve lower on-resistance than
applications like military, healthcare and some other MOSFETs by injecting minority carriers into the drift
industrial area [2]. Typically, the pulsed energy is stored region which is called conductivity modulation. Minority
either within electrostatic fields via capacitors or carrier will generate tail current when IGBT are turning
magnetic fields via inductors. In a Magnetic Resonance off resulting in high switching loss. SiC devices do not
Imaging (MRI) system, the gradient drivers are need conductivity modulation to achieve low
configured to excite gradient coils located around an on-resistance since they have much lower drift-layer
object, for example a patient, to generate magnetic field resistance than Silicon devices. Therefore, the switching
gradients along X-axes direction, Y-axes direction and loss could be much lower. Meanwhile, since SiC has
Z-axes direction [3-5]. The gradient coil is typically dielectric breakdown field strength 10 times higher than
considered as an air-core inductor and its inductance is that of Si, high breakdown voltage devices can be
on the range of several hundred ȝH to a mH. To generate achieved with a thin drift layer with high doping
enough gradient magnetic fields, high current more than concentration. This means, at the same breakdown
1000A through the gradient coil is required. Meanwhile, voltage, SiC devices have quite low specific
to have good image quality, the gradient coil current need on-resistance (on-resistance per unit area).
to be controlled with high accuracy and fidelity, which However, the thin drift layer with high doping can create
usually requires higher switching frequency for higher high depletion capacitance of the SiC device compared
control bandwidth (>10kHz). with silicon counterpart with similar voltage level.
The new wide band gap Silicon Carbide (SiC) devices, Figure 2 shows the cross section of the SiC MOSFET
such as MOSFETs, offer multiple benefits beyond model. Since we know that the depletion capacitance
state-of-the-art Si-based IGBTs. SiC MOSFETs achieve varies non-linearly with the applied voltage, the
much lower on-resistance and faster switching speed depletion capacitance can be calculated as (1).

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 Figure.1: Pulsed power system block diagram

dQ A j ε semi A j 2qε semi N d

Cj = = = (1)
dV Wj 2 Vds + Vbi

Where A j is the device junction area, W j is the device

depletion width, ε semi is the semiconductor dielectric
constant, q is fundamental electronic charge, N d is
the drift doping density, Vds is the device channel
voltage and Vbi is build-in junction potential. For
similar voltage range, the doping density of the SiC
device is almost two orders of magnitude higher and
therefore, the device depletion width is almost 10 times
lower than the silicon devices. Figure. 3 Depletion capacitance comparison
between silicon and SiC

The charge that stored in the depleting capacitors for

both top and bottom device need to be dissipated through
the device channel during one switching period if the
load current is very small. It’s quite common to regulate
the load current with very small value in pulsed power
application. Therefore, it’s desired to increase the pulsed
power efficiency with SiC devices when regulating small
current.

Figure. 2 Cross section of SiC MOSFET model

Figure 3 shows the comparison between the depletion

width and depletion capacitance per area between silicon
(bipolar device) and silicon carbide (unipolar device).
For example, with similar voltage range like 1.7kV
devices, the SiC depletion width is around 13μm and
silicon device is about 130 μm. Meanwhile, SiC and
silicon device shares similar dielectric constant
like ε SiC = 11.8 × ε 0 and ε Si = 9.7 × ε 0 . Therefore,
the equivalent depletion capacitance per area of SiC Figure. 4 Junction capacitances of 1.7kV, 480A SiC Module
device is almost 10 times higher than the silicon devices.
Assuming the SiC device normally can be rated at higher Figure 4 shows junction capacitance of one 1700V, 480A
current density, the real depletion capacitance of SiC SiC MOSFETs power module. This power module can
device with same current rating could be slightly lower. be considered as one phase leg composed of top and
bottom devices. Each device is composed of twelve

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1700V, 40A 4.5mm by 4.5 mm GE SiC MOSFET chips.
The SiC MOSFET body diode is utilized as the
freewheeling diode. The junction capacitance can be
curve fitted as analog equations versus applied voltage
and the charge stored in the depletion capacitance can be
calculated as (2). Switching loss with no load can be
calculated accordingly.
dv
Q = ³ i ⋅ dt = ³ C DS ⋅ dt = ³ C DS ⋅ dv (2)
dt
(b) Pulse test setup
Three power modules are placed in parallel to compose
of one phase leg as shown in Figure 5 in a pulse test
schematic. The output terminals of three modules are
electrically connected but not connected to any inductive
or other type of load. Three modules share one gate
driver board. To calculate the total charge dissipated
from the depletion capacitance to the channel, both top
and bottom gate drivers are pulsed with complemented
gate driver signal with a deadtime. Current shunt was
utilized to measure the transient current charged and
discharged to the depletion capacitance during the
transition. One of the test waveform with 1350V DC link
is shown in Figure 5 (C) and the total charge transferred (c) Test waveform
from DC side to the depletion capacitance is 10.24ȝC. Figure. 5 Depletion capacitance charge pulse
The tested results are compared with calculated results test schematic and setup
from the datasheet and summarized in Table I. The
experimental results match well with the calculated Table I. Calculated and tested junction charge
results and we can use the datasheet to evaluate the
switching loss of the power converter while regulating Charge/Switch 500V 1000V 1350V
the zero current. Calculated 5.31ȝC 7.8ȝC 9.54ȝC
Experimental 6.28ȝC 9.04ȝC 10.24ȝC

III. PROPOSED CONTROL ALGORITHM AND TEST

RESULTS

(a) Schematic

Figure 6. Power converter with two cascaded H-bridge

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The gradient driver structure demonstrated in this paper
is shown in Figure 6. Two stages H-bridges are cascaded
together to drive the inductive load which could be the
gradient coil. The gradient driver system can be
considered as a pulsed power application and the typical
load current is shown is shown in Figure 7. During the
Ton, the load current is controlled in a certain pattern
(trapezoidal, triangle, sinusoidal, etc). During the Toff,
both the current amplitude and the current change rate Figure. 8 Proposed control algorithms
are very small (The current can be in the range of few
amperes). The current pattern is repeated in the period of In the test, the switching frequency is 31.25kHz during
TR. As mentioned in the above section, the SiC depletion the high frequency mode (HF) and 15.625kHz during the
capacitance is typically much higher than silicon device low frequency mode (LF). ǻT1 is 100μs and ǻT2 is 1ms.
which will make the power converter switching loss With the proposed control algorithm, the switching
higher during the Toff period. For example, each of the frequency during the Toff will be reduced and the
phase leg in Figure 6 is composed of three 1.7kV SiC switching loss will be reduced accordingly.
MOSFETs modules in parallel as shown in Figure 5 (a). The output of the gradient amplifier is high voltage
If the switching frequency of each device is 31.25kHz PWM waveform which contains high frequency
and the DC link voltage is 1350V, the total switching loss harmonic content that may contaminate radio frequency
during the Toff period is around 3.2kW. (RF) signals that will be sensed by RF coils, and lead to a
significant degradation of the MR image quality. This
will be more severe in SiC gradient amplifier with fast
switching speed in the range of less than 50ns. To reduce
the dv/dt applied to the gradient coil, an output filter
stage is required as indicated in Figure 6. Since the
gradient driver output ripple frequency is much higher
than the carrier frequency, the high carrier ratio leads to a
concentrated harmonic energy distribution around the
ripple frequencies which enables the utilization of ripple
cancellation circuit.

Figure 7. Typical pulsed power load current

To reduce the higher switching loss of the SiC converter

during Toff in such pulsed power application, control
algorithm is proposed and shown in Figure 8. Different
frequencies are implemented per the predetermined load
current reference. When the current slew rate (di/dt) is
lower than certain value, low switching frequency mode
(LF) will be enabled because of lower bandwidth
requirement. In our demo, we use 0.05A/μs as the
Figure 9 Two stages double notch output filter topology
transition condition criterial. Meanwhile, all the
transition happed at LF range which is small duty cycles
The switching ripple is canceled by selecting the
to mitigate the disturbance. ǻT1 is the look-ahead time
auxiliary inductance and capacitance to form a resonant
from LF to HF and ǻT2 is the waiting time from HF to
trap that highly attenuates a selected narrow band that
LF.
contains switching harmonics. In our applications, the

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switching frequency is reduced from 31.25 kHz to
15.625 kHz during the low slew rate range of the load
current. Therefore, the total ripple frequency reduces
from 125 kHz to 62.5 kHz which requires two notch
filters to be implemented. Meanwhile, compared with
single stage, multiple stages low pass filters are more
suitable for high frequency attenuation. Therefore, two
stages and double notch output filter topology is
proposed in Figure 9 for this application.

(b) Load current and output voltage before filter

Figure 10 Output filter transfer gain measurement comparison

The measured output filter transfer gain is compared

with single stage and shown in Figure 10. Obvious high
frequency attenuation benefit with two stages structure (c) Zoom in waveform from LF to HF
Figure 11. Test waveforms with scaled down power (1050V DC
can be observed.
for each stage, peak current 450A)
A bipolar two-trapezoidal waveform was utilized as
example to test the proposed algorithm. The load IV. POWER LOSS COMPARISON BETWEEN SIC
inductance is around 500μH. The ripple frequency of the POWER CONVERTER AND SI POWER CONVERTER
output voltage before the filter changes from 62.5kHz to
Power stage loss between silicon converter and SiC
125kHz when changing from LF mode to HF mode.
converter is conducted with the selected waveform
shown in Figure 12.

(a) Tested waveform load current and gate drive

(a) Selected waveform for comparison

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 power loss and increase the system efficiency at high
power and therefore reduce the energy consumption
and cooling installation cost. However, because of the
large depletion capacitance, the SiC device switching
loss will be higher than silicon device at zero current.
Therefore, loss reduction method is proposed to
further improve SiC gradient driver efficiency. A
2700V, 1300A SiC gradient driver prototype is
designed, fabricated and tested.

(b) Comparison results between SiC and Si converters REFERENCES

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V. CONCLUSIONS
In this paper, high efficiency two stages cascaded
H-bridge gradient driver design with 1700V SiC
MOSFET is presented. SiC Power MOSFETs have
7~10 times lower switching loss than Silicon
counterparts. The SiC gradient driver reduces the total

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