Design of Analog

Integrated Circuit
VO TUAN MINH
Faculty of Electronics and Telecommunication Engineering
University of Science and Technology - The University of Danang
 Chủ đề
2

 Giới thiệu Thiết kế vi mạch & Đặc tính của MOSFET

 Mạch khuếch đại đơn
 Mạch khuếch đại vi sai
 Mạch gương dòng
 Bộ chuyển đổi tương tự/số
 Vòng khóa pha

DN, 2020 V.T.M

 Overview
3

1. General Considerations
2. Common-Source Amplifiers
3. Common-Drain (Source-Follower) Amplifiers
4. Common-Gate Amplifiers
5. Cascode Amplifiers

DN, 2020 V.T.M

 Why Amplifiers?
4

 Amplifiers are essential building blocks of both analog and digital

systems.

 Amplifiers are needed for variety of reasons including:

 To amplify a weak analog signal for further processing
 To reduce the effects of noise of the next stage
 To provide a proper logical levels (in digital circuits)

 Amplifiers also play a crucial role in feedback systems

 We first look at the low-frequency performance of amplifiers.

Therefore, all capacitors in the small-signal model are ignored!

DN, 2020 V.T.M

 Amplifier Characteristics
5

 Ideally, we would like that the output of an amplifier be a linear

function of the input, i.e., the input times a constant gain:
𝑦 𝑡 = 𝛼0 + 𝛼1 𝑥(𝑡)
y
𝛼0
x
 In real world the input-output characteristics is typically a
nonlinear function:
𝑦(𝑡) = 𝛼0 + 𝛼1 𝑥(𝑡) + 𝛼2 𝑥 2 (𝑡) + ⋯ + 𝛼𝑛 𝑥 𝑛 (𝑡)

DN, 2020 V.T.M

 Analog Design Trade-offs
6

DN, 2020 V.T.M

 Overview
7

1. General Considerations
2. Common-Source Amplifiers
3. Common-Drain (Source-Follower) Amplifiers
4. Common-Gate Amplifiers
5. Cascode Amplifiers

DN, 2020 V.T.M

 Common Source (CS) Basics
8

 In common-source amplifiers, the input is (somehow!) connected

to G and the output is (somehow!) taken from D.

 We can divide CS amplifiers into two groups:

 Without source degeneration (no

body effect for the main transistor)

 With source degeneration (with

body effect for the main transistor)

DN, 2020 V.T.M

 Common Source Basics
9

 Different types of loads can be used in an amplifier

 Resistive Load
 Diode-Connected Load
 Current-Source Load

 The following parameters of amplifiers are very important

 Small-signal gain
 Voltage swing

DN, 2020 V.T.M

 Resistive Load
10

 The region of operation of M1 depends on its size and the values

of Vin and RD.
 We are interested in the small-signal gain and the headroom
(which determines the maximum voltage swing).
 We will calculate the gain using two different methods

 Large-signal analysis

 Small-signal model

DN, 2020 V.T.M

 Resistive Load - Large-Signal Analysis
11

 For M1, VGS = Vin, VDS = Vout

 If Vin < VTH, M1 is off and Vout = VDD = VDS

 If Vin becomes slightly larger than VTH, M1 turns on and goes into
saturation, because of VDS = Vout > VGS – VTH
1 𝑊
𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝑅𝐷 𝐼𝐷 = 𝑉𝐷𝐷 − 𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 𝑉𝑖𝑛 − 𝑉𝑇𝐻 2
2 𝐿
𝜕𝑉𝑜𝑢𝑡 𝜕𝐼𝐷
𝐴𝑣 = = −𝑅𝐷 = −𝑅𝐷 𝑔𝑚
𝜕𝑉𝑖𝑛 𝜕𝑉𝐺𝑆
 M1 converts an input voltage change DVin to a drain current
change gmDVin, and hence an output voltage change DVout = −gm
RDDVin

DN, 2020 V.T.M

 Resistive Load - Large-Signal Analysis
12

 As Vin > Vin1, VDS decreases and M1 goes into triode region.
2
𝑊 𝑉𝑜𝑢𝑡
𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 𝑉𝑖𝑛 − 𝑉𝑇𝐻 𝑉𝑜𝑢𝑡 −
𝐿 2
𝜕𝑉𝑜𝑢𝑡
=> 𝐴𝑣 = : complicated
𝜕𝑉𝑖𝑛

 If Vin increases further, M1 goes into deep triode

region if Vout << 2(Vin – VTH).

𝑅𝑜𝑛 𝑉𝐷𝐷
𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 =
𝑅𝑜𝑛 + 𝑅𝐷 1 + 𝑅 𝜇 𝐶 𝑊 𝑉 − 𝑉
𝐷 𝑛 𝑜𝑥 𝐿 𝑖𝑛 𝑇𝐻

DN, 2020 V.T.M

 Resistive Load - Large-Signal Analysis
13

 The value of Vin that makes M1 switch its region of operation

1 𝑊 2
𝑉𝑖𝑛1 − 𝑉𝑇𝐻 = 𝑉𝐷𝐷 − 𝑅𝐷 𝜇𝑛 𝐶𝑜𝑥 𝑉𝑖𝑛1 − 𝑉𝑇𝐻
2 𝐿

DN, 2020 V.T.M

 Resistive Load - Small-Signal Model
14

 Assuming that the transistor is in saturation region and channel

length modulation is ignored

G D

S
 Output Voltage:
𝑉𝑜𝑢𝑡 = −𝑔𝑚 𝑉1 𝑅𝐷 = −𝑔𝑚 𝑉𝑖𝑛 𝑅𝐷
 Small-signal Gain:
𝐴𝑣 = −𝑔𝑚 𝑅𝐷

DN, 2020 V.T.M

 Resistive Load - Example
15

 Sketch ID and gm of M1 as a function of Vin.

𝑾
VRD 𝒈𝒎 = 𝝁𝒏 𝑪ox 𝑽ov
𝑳

Vin1

 gm depends on Vin so if Vin changes by a large amount then the

small-signal approximation will not be valid anymore.
 In order to have a linear amplifier, the gain should not depend on
parameters like gm since this parameter depends on the input
signal.

DN, 2020 V.T.M

 Resistive Load
16

𝑊 𝑉𝑅𝐷
𝐴𝑣 = − 2𝜇𝑛 𝐶𝑜𝑥
𝐿 𝐼𝐷
 Increase the gain by increasing W / L or VRD or decreasing ID if
other parameters are constant
 Increasing W / L leads to greater device capacitances
 Increasing VRD limits the voltage swing
 Decreasing ID leads to a greater time constant at the output
node since RD is increased
 Trade-offs between gain, bandwidth, and voltage swings, in
particular, with lower supply voltages

DN, 2020 V.T.M

 Resistive Load – Channel Length Modulation
17

 Channel length modulation becomes more significant as RD

increases?
 Using the Small-Signal Model because of its simplicity
G D

S
𝑟𝑂 𝑅𝐷 𝑟𝑂 𝑅𝐷
𝑉𝑜𝑢𝑡 = −𝑔𝑚 𝑉1 𝑅𝐷 ||𝑟𝑂 = −𝑔𝑚 𝑉𝑖𝑛 ⇒ 𝐴𝑣 = −𝑔𝑚
𝑟𝑂 + 𝑅𝐷 𝑟𝑂 + 𝑅𝐷
 If RD ≈ ∞ (current source as load) => Av ≈ -gmrO: intrinsic gain

 Today’s short-channel CMOS technology, gmrO is between roughly

5 and 10 => 1/gm << rO.
DN, 2020 V.T.M
 Example
18

 Assuming that M1 in the figure below is biased in saturation,

calculate the small-signal voltage gain of the circuit.

DN, 2020 V.T.M

 Example
19

 Suppose the common-source stage of the figure below is to

provide an output swing from 1 V to 2.5 V. Assume that VTH0 = 0.7
V, W / L = 50 / 0.5, RD = 2 kW and λ = 0.
 Calculate the input voltages that yield Vout = 1 V and 2.5 V.
 Calculate ID and gm of M1 for both cases.
 How much does the small-signal gain, gmRD, vary as the output
goes from 1 V to 2.5 V? (Variation of small-signal gain can be
viewed as nonlinearity.)

DN, 2020 V.T.M

 Diode-Connected Load
20

 Often, it is difficult to fabricate resistors with tightly controlled

values or reasonable sizes on chip => replace RD with MOSFET
Body
Effect Rx (λ≠0) Rx (λ=0)

1 1
NO 𝑅𝑥 = 𝑟𝑂 || 𝑅𝑥 =
𝑔𝑚 𝑔𝑚

1 1
YES 𝑅𝑥 = 𝑟𝑂 || 𝑅𝑥 =
𝑔𝑚 + 𝑔𝑚𝑏 𝑔𝑚 + 𝑔𝑚𝑏

DN, 2020 V.T.M

 Diode-Connected Load
21

Body Effect

D
NO G
S

G D

YES S

DN, 2020 V.T.M

 NMOS Diode-Connected Load
22

 This is a CS configuration with M2 being the load.

 Body effect of M2 needs to be considered. Rx
 Replacing RD in the Resistive load CS by Rx
𝐴𝑣 = −𝑔𝑚1 𝑅𝑥 ||𝑟𝑂1
1
= −𝑔𝑚1 (𝑟𝑂2 || ||𝑟𝑂1 )
𝑔𝑚2 +𝑔𝑚𝑏2
 Ignoring the channel length modulation (rO1 = rO2 = ∞), we have:
1 𝑔𝑚1 1
𝐴𝑣 = −𝑔𝑚1 = −
𝑔𝑚2 +𝑔𝑚𝑏2 𝑔𝑚2 1+𝜂2
𝑊/𝐿 1 1
=−
𝑊/𝐿 2 1+𝜂2

DN, 2020 V.T.M

 Diode-Connected Load
23

 If the variation of 𝜂 with Vout is neglected, Av is independent of the

bias currents and voltages (so long as M1 stays in saturation) =>
the input-output characteristic is relatively linear.
 Av is a weak function (square root) of the transistor sizes =>
change the dimensions by a considerable amount so as to
increase the gain.
 The voltage swing is constrained by both the required overdrive
voltages and the threshold voltage of the diode-connected
device.
𝑀1 : 𝑉𝑜𝑢𝑡 > 𝑉𝑖𝑛1 − 𝑉𝑇𝐻1 ; 𝑀2 : 𝑉𝑜𝑢𝑡 < 𝑉𝐷𝐷 − |𝑉𝑇𝐻2 |
 A high amplifier gain Av leads to a high overdrive voltage Vov for
the diode-connected device which limits the voltage swing.

DN, 2020 V.T.M

 Example
24

 Consider the circuit shown in the figure below. In some cases, we

are interested in the impedance seen looking into the source, RX.
Determine RX if λ = 0.

DN, 2020 V.T.M

 PMOS Diode-Connected Load
25

 This is a CS configuration with M2 being the load without body

effect.
 Replacing RD in the Resistive load CS by Rx, then Rx
𝐴𝑣 = −𝑔𝑚1 𝑅𝑥 ||𝑟𝑂1
1
= −𝑔𝑚1 (𝑟𝑂2 || ||𝑟𝑂1 )
𝑔𝑚2

 Ignoring the channel length modulation (rO1 = rO2 = ∞), we have:

𝑔𝑚1 𝜇𝑛 𝑊/𝐿 1 |𝑉𝐺𝑆2 − 𝑉𝑇𝐻2 |
𝐴𝑣 = − =− =
𝑔𝑚2 𝜇𝑝 𝑊/𝐿 2 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1

DN, 2020 V.T.M

 Diode-Connected Load - Example
26

 Find the gain of the following circuit if M1 is biased in saturation region

and Is = 0.75I1. Assume λ = 0.
𝑔𝑚1 4𝜇𝑛 𝑊/𝐿 1
 Since 𝐼𝐷2 = 𝐼1 /4 ⇒ 𝐴𝑣 = − =−
𝑔𝑚2 𝜇𝑝 𝑊/𝐿 2

𝑊 2 𝑊 2
 Or, 𝜇𝑛 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 = 4𝜇𝑝 𝑉𝐺𝑆2 − 𝑉𝑇𝐻2
𝐿 1 𝐿 2

4|𝑉𝐺𝑆2 − 𝑉𝑇𝐻2 |
⇒ |𝐴𝑣 | =
𝑉𝐺𝑆1 − 𝑉𝑇𝐻1
- For fixed transistor sizes, using the current source increases Av by 2
- For fixed overdrive voltages, using the current source increases Av by 4
- For a given gain, using the current source allows us to make the size or the
overdrive voltage of the diode-connected load 4 times smaller => increases the
headroom for voltage swing

DN, 2020 V.T.M

 Example
27

 Assuming a constant L, plot the intrinsic gain of a saturated

device versus the gate-source voltage if (a) the drain current is
constant, (b) W is constant.
 Assuming a constant L, plot the intrinsic gain of a saturated
device versus W/L if (a) the gate-source voltage is constant, (b)
the drain current is constant.

DN, 2020 V.T.M

 Current-Source Load
28

 Using current-source as load to increase the load

impedance without dropping a large DC voltage
𝐴𝑣 = −𝑔𝑚1 𝑟𝑂1 ||𝑟𝑂2 Constant
 For large gain at given power, we want large rO
 Since,
1 1 𝐿2
𝑟𝑂 ≈ ∝ =
𝜆𝐼𝐷 1 𝑊 𝑊
∙
𝐿 𝐿
=> Increase L and W keeping the aspect ratio constant (so rO
increases while ID remains constant). However, this approach
increases the capacitance of the output node.
 DC voltage of Vout is not well-defined
 Vin – VTH1 < Vout < VDD – |Vov2|

DN, 2020 V.T.M

 Current-Source Load - Example
29

 Compare the maximum output voltage swings of CS stages with

resistive and current-source loads.

DN, 2020 V.T.M

 Source Degeneration
30

 Lemma: In linear systems, the voltage gain is equal to −𝐺𝑚 𝑅𝑜𝑢𝑡

where 𝐺𝑚 = 𝜕𝐼𝑜𝑢𝑡 /𝜕𝑉𝑖𝑛 .

𝑔𝑚 𝑔𝑚 𝑅𝐷
𝐺𝑚 = ⇒ 𝐴𝑣 = −
1 + 𝑔𝑚 𝑅𝑆 1 + 𝑔𝑚 𝑅𝑆

G D

DN, 2020 V.T.M

 Source Degeneration
31

 For large values of Vin

 ID / Vin of the input device becomes more linear
 Gm approaches 1/RS
𝑔𝑚 𝑔𝑚
𝐺𝑚 = ⇒ 𝐼𝐷 = 𝑉
1 + 𝑔𝑚 𝑅𝑆 1 + 𝑔𝑚 𝑅𝑆 𝑖𝑛

w/o Source Degeneration w/i Source Degeneration

DN, 2020 V.T.M

 Source Degeneration
32
G D
𝑔𝑚 𝑟𝑂
𝐺𝑚 =
𝑅𝑆 + 1+ 𝑔𝑚 +𝑔𝑚𝑏 𝑅𝑆 𝑟𝑂
S

G D
𝑅𝑜𝑢𝑡 = 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑆 𝑟𝑂 + 𝑅𝑆
= 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑟𝑂 𝑅𝑆 + 𝑟𝑂 S

DN, 2020 V.T.M

 Example
33

 Assuming λ = γ = 0, calculate the small-signal gain of the

circuit shown in the figure below (a).

𝑅𝐷
𝐴𝑣 = −
1 1
+
𝑔𝑚1 𝑔𝑚2

DN, 2020 V.T.M

 Example
34

 Calculate the voltage gain of the circuit shown in the

figure below. Assume that I0 is ideal.

DN, 2020 V.T.M

 Overview
35

1. General Considerations
2. Common-Source Amplifiers
3. Common-Drain (Source-Follower) Amplifiers
4. Common-Gate Amplifiers
5. Cascode Amplifiers

DN, 2020 V.T.M

 Why Buffers?
36

 CS amplifiers needs a large-impedance load to achieve high

voltage gain. If the load is low-impedance, a buffer is used.
 Source-Follower (SF) amplifiers can be used as buffers.
 Ideal Buffer: Rin = ∞, Rout = 0, Av = 1

ZL

DN, 2020 V.T.M

 Resistive Load
37

 Examine the Source follower amplifier with two different loads:

 Resistive Load
 Current-Source Load
 Resistive Load
 M1 never enters triode region as long as Vin < VDD + VTH.

DN, 2020 V.T.M

 Resistive Load – Small-Signal Analysis
38
G D
 𝑉1 = 𝑉𝑖𝑛 − 𝑉𝑜𝑢𝑡 ; 𝑉𝑏𝑠 = −𝑉𝑜𝑢𝑡
𝑉𝑜𝑢𝑡
 = 𝑔𝑚 𝑉𝑖𝑛 − 𝑉𝑜𝑢𝑡 − 𝑔𝑚𝑏 𝑉𝑜𝑢𝑡
𝑅𝑆
𝑉𝑜𝑢𝑡 𝑔𝑚 𝑅𝑆 S
⇒ 𝐴𝑣 = =
𝑉𝑖𝑛 1+ 𝑔𝑚 +𝑔𝑚𝑏 𝑅𝑆

𝛾
1. As Vin increases, gm increases and 𝜂=
𝑔𝑚 1 2 2∅𝐹 + 𝑉𝑆𝐵
the gain becomes: 𝐴𝑣 = =
𝑔𝑚 +𝑔𝑚𝑏 1+𝜂
2. As Vout increases, η decreases, the
maximum gain increases.
3. Even if RS = ∞, Av is less than 1
4. Av depends heavily on the DC level of Vin (nonlinear amplifier).

DN, 2020 V.T.M

 Current-Source Load
39

 To avoid the problem of

nonlinear voltage gain, we
can use a current-source as
the load.
 The output resistance is:
Constant
1
𝑅𝑜𝑢𝑡 = 𝑅𝑀1 ||𝑅𝑀2 = (𝑟𝑂1 || ||𝑟𝑂2 )
𝑔𝑚1 + 𝑔𝑚𝑏1
 If channel length modulation is ignored (rO1 = rO2 = ∞):
1
𝑅𝑜𝑢𝑡 =
𝑔𝑚1 + 𝑔𝑚𝑏1
=> The body effect reduces the output impedance of the SF
amplifiers.

DN, 2020 V.T.M

 Advantages and Disadvantages
40

 Source followers have typically moderate output impedance,

large input impedance. However, avoid using because:
 Source followers are nonlinear because of body effect
 Variable bias current which can be resolved if we use a

current-source to bias the SF => Dependence of rO on VDS in

submicron devices.
 Body effect can be resolved for PMOS devices, because each

PMOS transistor can have a separate n-well. However,

because of low mobility, PMOS devices have higher output
impedance. (In more advanced technologies, NMOS in a
separate p-well can be implemented)

DN, 2020 V.T.M

 Advantages and Disadvantages
41

 SFs have voltage headroom limitations

due to level shift. Consider the circuit that
a CS is followed by a SF

 If there is only the CS stage

𝑉𝑋 > 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1
 With the SF stage, 𝑉𝑋 > 𝑉𝐺𝑆3 − 𝑉𝑇𝐻3 + 𝑉𝐺𝑆2 .
 Therefore, adding the SF will reduce the allowable voltage
swing at node X.

DN, 2020 V.T.M