MANAKULA VINAYAGAR INSTITUTE OF TECHNOLOGY

KALITHEERTHAL KUPPAM, PUDUCHERRY-605107

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

LAB MANUAL

CS P33
DIGITAL DESIGN LABORATORY
II YEAR/III SEMESTER
 Tutorial Practical
Subject Lectures
Subject Name (Periods (Periods
Code (Periods)
) )

CS P33 DIGITAL DESIGN LABORATORY - - 3

LIST OF EXPERIMENTS

1. Verification of DeMorgan’s theorems using basic logic gates.

2. Design and implementation of adders and subtractors.
3. Design and implementation of Parity Generator/Checkers.
4. Design and implementation of Priority encoders using logic gates.
5. Design and implementation of simplified Boolean expressions using
Multiplexers.
6. Design and implementation of simplified Boolean expressions using
Decoders.
7. Design and implementation of Magnitude Comparators.
8. Study of clocked RS, D, and JK Flip-Flops.
9. Design and implementation of Serial Input Parallel Output (SIPO) and
Parallel Input Serial Output (PISO) Shift Registers.
10.Design and implementation of ripple and synchronous counters.
11.Simulation of a combinational logic using HDL.
12.Simulation of a sequential logic using HDL.
EXPT NO. :1(A)
DATE :
STUDY OF LOGIC GATES

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY
1. Quad 2 input AND gate IC 7408 1
2. Quad 2 input OR gate IC 7432 1
3. NOT gate IC 7404 1
4. Quad 2 input NAND gate IC 7400 1
5. Quad 2 input NOR gate IC 7402 1
6. Quad 2 input X-OR gate IC 7486 1
7. 3 input NAND gate IC 7410 1
8. IC Trainer kit -  1
9. Patch Cord  - As required

THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate has
one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs
is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are
low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
The output is low when one or both inputs are high.

X-OR GATE:

The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.

AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:

NOT
GATE:

SYMBOL:

PIN
DIAGRAM:

XOR GATE :

SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE

NOR GATE:
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Switch ON the digital lab trainer kit
(iii) Inputs are given using the toggle switch
(iv) Observe the output and verify the truth table

RESULT:
Thus the functions of all logic gates are studies and verified.
EXPT NO. :1(B)
DATE :
VERIFICATION OF DEMORGAN’S THEOREM

AIM:
To study and verification of DeMorgan’s theorems using basic logic gates.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY
1. Quad 2 input AND gate IC 7408 1
2. Quad 2 input OR gate IC 7432 1
3. NOT gate IC 7404 1
4. IC Trainer kit -  1
5. Patch Cord  - As required

THEORY:

DeMorgan’s suggested tow theorems that form an important part of Boolean

algebra. In the equation form, they are:

1) AB = A’ + B’

The complement of a product is equal to the sum of the complements.

2) A+B = A’.B’

The complement of a sum is equal to the product of the complements.

CIRCUIT DIAGRAM:

Truth Table

1) AB = A’ + B’

A B AB A’+B’
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

2) A+B = A’.B’

A B A+B A’.B’
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables

RESULT:

Thus the Demorgan’s Theorem is designed and implemented and the output is verified.
EXPT NO. :2(A) 2(B)
DATE :

STUDY OF ADDERS AND SUBTRACTORS

AIM:
To study by design and construct half adder, full adder, half subtractors and full
subtractors circuits and verify their truth tables using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. Quad 2 input AND gate IC 7408 1
2. Quad 2 input X-OR gate IC 7486 1
3. Hex 1 input NOT gate IC 7404 1
4. Quad 2 input OR gate IC 7432 1
3. IC Trainer kit - 1
4. Patch Cords - As required

THEORY:

HALF ADDER:

A half adder is a combinational circuit needs two binary inputs and two binary outputs.
The input variables designate the augend and addend bits, the output variables produce the sum
and carry. The half-adder can be implemented with an exclusive –OR and an AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time. In full adder
sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.

HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be applied
using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.
FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor
the logic circuit should have three inputs and two outputs. The two half subtractor put together
gives a full subtractor .The first half subtractor will be C and A B. The output will be difference
output of full subtractor. The expression AB assembles the borrow output of the half subtractor
and the second term is the inverted difference output of first X-OR.

HALF ADDER

TRUTH TABLE:

Inputs Outputs

A B CARRY SUM
0 0 0 0
0 01 0 01
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

=
LOGIC DIAGRAM:

FULL ADDER

FULL ADDER USING TWO HALF ADDER:

TRUTH TABLE:

Inputs Outputs
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM: K-Map for CARRY:

SUM = A’B’C + A’BC’ + ABC’ + ABC CARRY = AB + BC + AC

= C(A’B’+AB) + C’(A’B+AB’)
=
LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:

Inputs Outputs
A B BORROW DIFFERENCE
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE: K-Map for BORROW:

DIFFERENCE = A’B + AB’ BORROW = A’B

=
LOGIC DIAGRAM:

FULL SUBTRACTOR

TRUTH TABLE:

Inputs Outputs
A B C BORROW DIFFERENCE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference: K-Map for Borrow:

Difference = A’B’C + A’BC’ + AB’C’ + ABC Borrow = A’B + BC + A’C

= A’ (B’C+BC’) +A (B’C’+BC)
=
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Switch ON the digital lab trainer kit
(iii) Inputs are given using the toggle switch
(iv) Observe the output and verify the truth table.

RESULT:

Thus the Combinational circuit for Adder/Subtractor is designed and implemented and
the output is verified.
EXPT NO. :3
DATE :

DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND CHECKER

AIM:

To design and verify a combinational logic circuits of a 3 bit parity generator and checker.

APPARATUS REQUIRED:
Sl No. COMPONENT SPECIFICATION QTY
1 Quad 2 input X-OR gate IC 7486 1
2 IC trainer kit -  1
3 Patch cord  - As required

THEORY:

Parity is used for purpose of detecting errors and transmission of binary information.
A parity bit is an extra bit included with a binary message to make the number of 1’s either odd
or even.
The message including the parity bit is transmitted and then checked out the receiving end for
errors.
An errors is detected if the checked parity does not correspond with the one transmitted.
The circuit generator the parity bit in the transmitted is called a parity generator.

The digital information is in binary form. If it is transmitted from one digital system to
another system an error may occur due to transients, noise and other disturbances. This means a
signal corresponding to a may change to 1 or vice versa. To catch these errors, a parity bit(0 or1)
is usually transmitted along with the original bits. The circuit used for generating parity bit is
called parity generator.
TRUTH TABLE:

Inputs Outputs
A B C ODD PARITY(PO) EVEN PARITY(PE)
0 0 0 1 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
 1 1 1 0 1
K- MAP FOR EVEN PARITY

PE=

K- MAP FOR ODD PARITY

PO=

LOGIC DIAGRAM:
PROCEDURE:

(i) Connections are given as per the circuit diagram.

(ii) Switch ON the digital lab trainers kit
(iii) Inputs are given using the toggle switch and output are verified by the LED
arrangement
(iv) Then the truth table is verified.

RESULT:

Thus the Combinational circuit for Parity checker and generator is designed and
implemented and the output is verified.
EXPT NO. :4
DATE :

DESIGN AND IMPLEMENTATION OF PRIORITY ENCODERS USING LOGIC

GATES

Aim:
To design and implement a 4 line to 2 line priority encoder.

Theory:
 The priority Encoder is a circuit that implements that if two or more inputs arrive at the
same time, the input having the highest priority will take place.
 In the truth table the ‘X’s designate don’t care conditions. Input I0 has the highest priority.
So regardless the values of other input, when this input is 1, the output generates an
output xy=00. Next I1 has the second highest level of priority.
 The output 01 if I1 =1 provided that I0 =0, regardless of the values of the other two lower
priority inputs. The output for I2 is generated only if higher priority inputs are 0, and so
on down the priority level. Inputs are 0, and so on down the priority level. Inputs are 0,
and so on down the priority level.
 The Interrupt Status IST is set only one or more inputs are equal to 1. If all the inputs are
0, IST is cleared to 0 and the other outputs of the encoder are not used, so they are
marked with don’t care conditions.
 This is because vector address is not transferred to the CPU when IST=0. The Boolean
function listed in the table specifies the internal logic of the encoder. Usually a computer
will have more than four interrupt sources.
 A priority Encoder with 8 inputs, for example an output of three bits.
 The priority encoder output is used to form part of the vector address for each interrupt
source. The other bits of the vector address can be assigned any value. For example, the
 vector address can be performed by appending 6 zeros to x and y outputs of the encoder.
With this choice the interrupt vectors for the 4 I/O devices are assigned binary numbers 0,
1, 2, 3.
TRUTH TABLE:

INPUTS OUTPUTS

I0 I1 I2 I3 X Y V

1 X X X 0 0 1

0 1 X X 0 1 1

0 0 1 X 1 0 1

0 0 0 1 1 1 1

0 0 0 0 X X 0

KARNAUGH MAP:
I2I3 I2I3
00 01 11 10 00 01 11 10
I0I1 I0I1
00 X 1 1 1 00 X 1

01 01 1 1 1 1

11 11

10 10

X= I0'.I1' Y=I0'.I1+I0'I2'

I2I3
00 01 11 10
I0I1
00 1 1 1

01 1 1 1 1

11 1 1 1 1

10 1 1 1 1

V= I0+I1+I2+I3

LOGIC DIAGRAM:
I0
X
I1

I2
I3
Y

V= I0+I1+I2+I3

PROCEDURE:

(i) Connections are given as per the circuit diagram.

(ii) Switch ON the digital lab trainers kit
(iii) Inputs are given using the toggle switch and output are verified by the LED
arrangement
(iv) Then the truth table is verified.
RESULT:

Thus a 4 line to 2 line priority encoder is designed and the output is verified successfully.
EXPT NO. :5
DATE :

DESIGN AND IMPLEMENTATION OF SIMPLIFED BOOLEAN EXPRESSION USING

MULTIPLEXER

AIM:
To study, design and implementation of multiplexer using logic gates.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 input AND gate IC 7411 2
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
2. IC trainer kit - 1
3. Patch cords - As required

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2 n input line and
n selection lines whose bit combination determine which input is selected.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
Select inputs Data inputs Output
S1 S0 D0 D1 D2 D3 Y
0 0 1 0 0 0 1
0 1 0 1 0 0 1
1 0 0 0 1 0 1
1 1 0 1 0 0 1

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:
INPUTS OUTPUTS
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus the Combinational circuit for Multiplexer is designed and implemented and the
output is verified.
EXPT NO. :6
DATE :

DESIGN AND IMPLEMENTATION OF SIMPLIFED BOOLEAN EXPRESSIONS

USING DECODERS

AIM:
To study, design and implement decoder using logic gates.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 input NAND gate IC 7410 2
2. OR gate IC 7432 3
3. NOT gate IC 7404 1
2. IC trainer kit - 1
3. Patch cords - As required

THEORY:
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has fewer
bits than the output code. Each input code word produces a different output code word i.e there is
one to one mapping can be expressed in truth table. In the block diagram of decoder circuit the
encoded information is present as n input producing 2 n possible outputs. 2n output values are
from 0 through out 2n – 1.

TRUTH TABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
LOGIC DIAGRAM FOR DECODER:

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
 Thus the design and implementation of simplified Boolean expressions using decoders
are studies and verified.
EXPT. NO: 7
DATE :

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND gate IC 7408 2
2. X-OR gate IC 7486 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. 4-bit magnitude IC 7485 2
comparator
6. IC trainer kit - 1
7. Patch cords - As required

THEORY:

The comparison of two numbers in an operation that determines if one number is greater
that, less than or equal to the other number. A magnitude comparator is combinational circuits
that compares the two number A and B, and determine their relative magnitudes. The outcome of
the comparison is specified by three binary variables that indicate whether A>B, A=B or A<B.
The circuit for comparing two n-bit numbers has 2 n entries in the truth table and becomes
other hand as one may suspect a comparator circuit posses a certain amount of regularity. Digital
functions which posses on inheriting well defined regularity can usually are designed by mean of
an algorithmic procedure if one is found to exist.
An algorithm is a procedure that specifies a finite set of steps which if followed give the
solution to the problem. The algorithm is a direct application of the procedure a person uses to
compare the relative magnitude of the two numbers. Consider two number A and B. write the co-
efficients of the number with descending significance as follows:
A = A1A0
B = B1B0
The two numbers are equal i.e., if A1 = B1 and A0 = B0. The equality of the two
numbers a and B is displayed in a combinational circuit by an output binary variable which we
designate is equal to 1. If the input numbers, A and B are equal and its equal to 0 otherwise. For
equality conditions to exist, all xi variables must be equal to 1.
Xi = AiBi +Ai’Bi’[I = 0,1]. If the two digit are equal we compare the next lower
siginificant pair of digits. This comparison continues until a pair of unequal digits is reached.
If the corresponding digit of A is 1 and B is 0, we conclude that A>B. if the
corresponding digit of A is 0 and Bis 1.
(A>B) = A1B1’+A0B1’B0’ + A1A0B0’
(A<B) = A1B1’ + A1’B0A0’ + A0’A1B0

TRUTH TABLE:

Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM:

8-BIT MAGNITUDE COMPARATOR:

TRUTH TABLE:

A B A>B A=B A<B

0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the design and implementation Magnitude comparator is studied and verified
EXPT. NO: 8
DATE :
STUDY OF FLIP-FLOPS

AIM:

To verify the characteristic table of RS, JK and D Flip flops.      

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. Digital IC trainer kit 1
2. D-Flipflop IC 7474 1
3. JK-Flipflop IC 7476 1
4. NAND gate IC 7400 1
6. Connecting wires As required

THEORY:

A Flip Flop is a sequential device that samples its input signals and changes its output
states only at times determined by clocking signal.  Flip Flops may vary in the number of inputs
they possess and the manner in which the inputs affect the binary states.

RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse.  When the clock pulse is high the S and R
inputs reach the second level NAND gates in their complementary form.   The Flip Flop is reset
when the R input is high and S input is low.  The Flip Flop is set when the S input is high and R
input is low.  When both the inputs are high the output is in an indeterminate state. 

D FLIP FLOP:

To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when
both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the
same time.  This is obtained by making the two inputs complement of each other.
JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop.  JK inputs
behave like S and R inputs to set and reset the Flip Flop.  The output Q is ANDed with K input
and the clock pulse, similarly the output Q’ is ANDed with J input and the Clock pulse.  When
the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their
previous values.  When the clock pulse is high, the J and K inputs reach the NOR gates.  When
both the inputs are high the output toggles continuously.  This is called Race around condition
and this must be avoided.

RS FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:
CHARACTERISTIC TABLE:

CLOCK INPUT PRESENT NEXT

PULSE S R STATE (Q) STATE(Q+1)
1 0 0 0 0
2 0 0 1 1
3 0 1 0 0
4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 X
8 1 1 1 X

D FLIP FLOP

PIN DIAGRAM:
CHARACTERISTIC TABLE:

CLOCK
INPUT (D) OUTPUT (Q)
PULSE
0 0 0
0 1 1
1 0 1
1 1 0

JK FLIP FLOP

PIN DIAGRAM:
CHARACTERISTIC TABLE:

CLOCK INPUTS OUTPUT(Q)

PULSE J K
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

PROCEDURE:

(i) Connections are given as per the circuit diagrams.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the status of all the flip flops.

RESULT:

Thus the function of all flip-flops are studies and verified.

EXPT. NO: 9
DATE :
DESIGN AND IMPLEMENATION OF SHIFT REGISTER.

AIM:
To study and implement shift register in various modes of operation
(i) Serial in parallel out (SIPO)
(ii) Parallel in serial out (PISO)
(iii) Serial in Serial out (SISO)
(iv) Parallel in Parallel out (PIPO)

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit - 1
4. Patch cords - As required

THEORY:
SHIFT REGISTER:
The Shift Register is another type of sequential logic circuit that is used for the storage or
transfer of data in the form of binary numbers and then "shifts" the data out once every clock
cycle, hence the name "shift register". It basically consists of several single bit "D-Type Data
Latches", one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement so
that the output from one data latch becomes the input of the next latch and so on.
The data bits may be fed in or out of the register serially, i.e. one after the other from
either the left or the right direction, or in parallel, i.e. all together. The number of individual data
latches required to make up a single Shift Register is determined by the number of bits to be
stored with the most common being 8-bits (one byte) wide, i.e. eight individual data latches. The
individual data latches that make up a single shift register are all driven by a common clock
(Clk) signal making them synchronous devices.
 Shift register IC's are generally provided with a “clear” or “reset” connection so that they
can be "SET" or "RESET" as required. Generally, shift registers operate in one of four different
modes with the basic movement of data through a shift register being:

Serial-in to Serial -out (SISO):

In this register the data shifts from one flip flop to another till eight clock pulses were given.
And only at the eighth clock pulse we will be getting the
output.

Serial-in to Parallel-out (SIPO):

  The register is loaded with serial data, one bit at a time, with the stored data being
available in parallel form.

Parallel-in to Serial-out (PISO):

The parallel data is loaded into the register simultaneously and is shifted out of the
register serially one bit at a time under clock control.

Parallel-in to Parallel -out (PIPO):

For parallel in - parallel out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits.  

PIN DIAGRAM:
SERIAL IN SERIAL OUT

TRUTH TABLE:
CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC
QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

TRUTH TABLE:
Parallel Outputs
CLK Serial QA QB QC QD
inputs
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 0
4 1 1 0 0 1
 LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

TRUT
H TABLE:
Parallel Inputs Serial
CLK
Q3 Q2 Q1 Q0 Output
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
 Thus the function of sequential circuits for SIPO & PISO are studied and verified by
truth table.
EXPT. NO: 11
DATE :

DESIGN AND IMPLEMENTATION OF RING AND SYNCHRONOUS COUNTERS

AIM:
To design and implement Ring and Johnson counters.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D-Flipflop IC 7474 4
2. IC Trainer Kit - 1
3. Patch Cords - As required

THEORY:
COUNTERS:
A shift register counter is basically a shift register with the serial output connected back
to the serial input to produce special sequences. These devices are often classified as counters
because they exhibit a specified sequence of states. Two of the most common types of shift
register counters, the Johnson counter and the ring counter.

RING COUNTERS:
A ring counter is basically a circulating shift register in which the output of the most
significant stage is fed back to the input of the least significant stage.  The 4-bit ring counter is
constructed from D flip-flops.  The output of each stage is shifted into the next stage on the
positive edge of a clock pulse.  If the CLEAR signal is high, all the flip-flops except the first one
FF0 are reset to 0.  FF0 is preset to 1 instead.

Since the count sequence has 4 distinct states, the counter can be considered as a mod-4
counter.  Only 4 of the maximum 16 states are used, making ring counters very inefficient in
terms of state usage.  But the major advantage of a ring counter over a binary counter is that it is
self-decoding.  No extra decoding circuit is needed to determine what state the counter is in.

JOHNSON COUNTERS:
Johnson counters are a variation of standard ring counters, with the inverted output of the
last stage fed back to the input of the first stage.  They are also known as twisted ring counters.
An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to be
a mod-2ncounter.

LOGIC DIAGRAM:
RING COUNTER:

TRUTH TABLE:
Clock Pulse Q0 Q1 Q2 Q3
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
LOGIC DIAGRAM:
JOHNSON COUNTER:

TRUTH TABLE:
Clock Pulse Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

Synchronous Counter:

 In synchronous counter common clock pulse trigger all flip flops at same
time. A binary ripple counter consists of series flip flop & the output flip flop connected
to clock input for next FF.
 A complementing flip flop used in T flip flop or JK flip flop where J&K tied. The flip
flop holder LSB receives clock pulse when there is negative transmission from 1 to 0. If
A0 goes from 1 to 0 then A1 is completed.
 The flip flop changes at a time and signal propagated in ripple fashion.
 In synchronous counter clock pulse applied to all function flip flop.
 The decision whether output of flip flop is complemented is determined by J & K if J = K
= 0 then no change in output if J = K = 1 then complemented.
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Clock pulse is given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus the sequential circuit for synchronous and Ring counters are studied and verified by
truth table.
EXPT NO: 12
DATE :

SIMULATION OF COMBINATIONAL LOGIC USING HDL

AIM:
To write Verilog code to describe the functions of a full adder.

TOOLS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY

P IV processor, 1GB RAM with good

1. Desktop – PC with 1
configuration

2. Altera Quartus EDA tool Version above 7.0 1

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1
Verilog code for Full adder

module fadd(a,b,c,s,cout);
input a;
input b;
input i;
output s;
output cout;
assign s = (a ^ b) ^ c;
assign cout = (a & b)|( b & c)|(c & a);
end module

SIMULATED TIMING WAVEFORM:

RESULT:

The full adder has been realized and simulated using Verilog codes.
EXPT NO: 13
DATE :
SIMULATION OF SEQUENTIAL LOGIC USING HDL

AIM:

To develop the Verilog codes for the following flip-flops: D, J-K, T Flip-Flops.

TOOLS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY

P IV processor, 1GB RAM with good

1. Desktop – PC with 1
configuration

2. Altera Quartus EDA tool Version above 7.0 1

TRUTH TABLE:

D-FLIP FLOP:

J-K FLIP FLOP:

T – FLIP FLOP:

Verilog code for JK flip flop

module jkff(jk,pst,clr,clk,qp,qbar);
input [1:0] jk; input pst,clr,clk;
output qp,qbar;
reg qp; wire q;
always @ (posedge clk)
if (pst)
qp= 1;
else
begin
if (clr)
qp= 0;
else
begin
case (jk)
2'b00: qp=q;
2'b01 : qp = 1'b0;
2'b10 : qp =1'b1;
2'b11 : qp = ~q;
default qp =0;
endcase
end
end
assign qbar = ~q;
assign q = qp;
end module
SIMULATED TIMING WAVEFORM:

Verilog code for D flip flop:

module dff(d,clk,q,qbar);
input d;
input clk;
output q,qbar;
reg q, qbar;
always @ (posedge clk)
begin
q = d;
qbar = ~d;
end
endmodule

SIMULATED TIMING WAVEFORM:

Verilog code for T flip flop:
module tffeq(t,rst, clk,qp, qbar);
input t,rst, clk;
output qp, qbar;
wire q;
reg qp;
always @ (posedge clk)
if (rst)
qp=0;
else
qp = q ^ t;
assign qbar = ~ qp;
end module

SIMULATED TIMING WAVEFORM:

RESULT:
Thus the D, J-K, T-Flip Flop has been implemented and realized using Verilog codes.