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LAB#1

This document provides information about a digital systems design lab on gate-level modeling and simulation using Verilog. The objectives are to understand basic Verilog programming, module instantiation for structural description, and simulating combinational circuits at the gate level. Students will use an online simulator to model a 2-bit comparator from a textbook example and its test vectors, observing the output waveforms. The exercise is to design a full adder with a test bench providing sample input vectors and observe the sum and carry outputs on the waveforms.

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Unsa Jan Abdul Qayyum
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© © All Rights Reserved
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49 views

LAB#1

This document provides information about a digital systems design lab on gate-level modeling and simulation using Verilog. The objectives are to understand basic Verilog programming, module instantiation for structural description, and simulating combinational circuits at the gate level. Students will use an online simulator to model a 2-bit comparator from a textbook example and its test vectors, observing the output waveforms. The exercise is to design a full adder with a test bench providing sample input vectors and observe the sum and carry outputs on the waveforms.

Uploaded by

Unsa Jan Abdul Qayyum
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of

Electrical Engineering

Digital System Design (ESE-412)

Handout#01
Gate-Level Modelling and Simulation
Instructor: Engr Irsa Jan

Lab Learning Objectives:

After completing this session, student should be able to:


• Understand basics of Verilog programming.
• Get familiar with structural description (module instantiation).
• Simulate basic combinational circuits using gate-level modelling.
Note: Submit the lab report (solved activities and exercises) before the next lab.

Lab Hardware and Software Required:

1. Desktop/Laptop Computer with internet connection.

Background Theory:

Gate-level Modelling:
Verilog is both a structural and behavioural language. Internals of each module can be
defined at four levels of abstraction, depending on the need of the design. There are four
levels of abstraction which include switch-level, gate-level, data flow, and behavioural or
algorithm level.

The switch-level is the lowest abstraction level, where module can be implemented
in terms of switches, storage nodes, and interconnections between them.

The gate-level modelling is implemented in terms of logic gates and


interconnections between these gates. This design method is like describing a
design in terms of a gate-level logic diagram.

Verilog allows the designer to mix and match all four levels of design methodologies in
design. The modules behave identically to the external world identically irrespective of
the level of abstraction at which module is described. Therefore, internals of the module
can be changed without any change in the environment.

In the digital design community, the term register transfer level (RTL) is used for Verilog
description that uses a combination of behavioural and data flow modelling. Normally, the
higher level of abstraction, design will be more flexible and technology independent.
Although, the lower-level description provides high performance therefore as the design
matures, high level modules are replaced with the gate-level modelling.
Lab Activity:
We are going to use testbench listing 1.7 (2-bit comparator design and its test vector) you
have covered in chapter#1 of the textbook.

Steps:
1. Open https://www.edaplayground.com/.
2. Write your testbench code at the left and required modules on the right.
3. Add these two lines after initial begin
$dumpfile("eq2_tb.vcd"); // simulator generates output file for the waveforms data

$dumpvars;
Also, replace $stop with $finish.

4. Select Icarus Verilog as your simulator.


5. Enable “Open EPWave after run”.
6. Run the coding.
7. After successful run, select signals to show waveforms.
Fig#1: EDA playground testbench programming and initial settings
Exercise:

Design a full adder circuit along with its test bench. You may give four input vectors (from
the table) in the test bench and observe the output from waveforms.
a b c_in sum c_out
1 0 0 1
2 1 1 0
3 1 0 1
4 1 1 1

Additionally, you are required to attach the input and output waveforms in your lab report.

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