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Integrated Lab1

The document describes a student named Talha Mustafa completing several tasks in their EE-380L lab. The tasks involve using hardware description language to model and simulate various logic gates, including AND, OR, NAND, NOR, and NOT gates. Circuit diagrams, truth tables, and code are provided for each gate.

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Talha Mustafa Jutt
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19 views10 pages

Integrated Lab1

The document describes a student named Talha Mustafa completing several tasks in their EE-380L lab. The tasks involve using hardware description language to model and simulate various logic gates, including AND, OR, NAND, NOR, and NOT gates. Circuit diagrams, truth tables, and code are provided for each gate.

Uploaded by

Talha Mustafa Jutt
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Name: Talha Mustafa Course Code: EE-380L

Roll No: 2020-EE-060 Section: B

LAB No: 01
Object:
Follow the methodology behind the hardware design using hardware descriptive language.
Task 01:
To Design AND gate by using gate level modeling.

Circuit Diagram:
a
x
b

Truth Table:

Input OutPut
a b c
0 0 0
0 1 0
1 0 0
1 1 1

Coding:
//design module
module gate(x,a,b);
input a,b;
output x;
and a1(x,a,b);
endmodule

//Stimulus module
module Talha;

Electronic Engineering Department


Sir Syed University Of Engineering And Technology
Name: Talha Mustafa Course Code: EE-380L
Roll No: 2020-EE-060 Section: B

reg a,b;
wire x;
gate g1(x,a,b);
initial
begin
a=1'b0; b=1'b0;
#20
a=1'b0; b=1'b1;
#20
a=1'b1; b=1'b0;
#20
a=1'b1; b=1'b1;
#20
$finish;
end
endmodule

Result:

Electronic Engineering Department


Sir Syed University Of Engineering And Technology
Name: Talha Mustafa Course Code: EE-380L
Roll No: 2020-EE-060 Section: B
Task:02
To Design OR gate by using gate level modeling.
Circuit Diagram:
a
x
b

Truth Table:
Input OutPut
a b x
0 0 0
0 1 1
1 0 1
1 1 1

Coding:

//design module
module gate(x,a,b);
input a,b;
output x;
or a1(x,a,b);
endmodule

//stimulus module
module Talha;
reg a,b;
wire x;
gate g1(x,a,b);
Electronic Engineering Department
Sir Syed University Of Engineering And Technology
Name: Talha Mustafa Course Code: EE-380L
Roll No: 2020-EE-060 Section: B
initial
begin
a=1'b0; b=1'b0;
#30
a=1'b0; b=1'b1;
#30
a=1'b1; b=1'b0;
#30
a=1'b1; b=1'b1;
#30
$finish;
end
endmodule

Result:

Electronic Engineering Department


Sir Syed University Of Engineering And Technology
Name: Talha Mustafa Course Code: EE-380L
Roll No: 2020-EE-060 Section: B

Task 3: To design NAND gate using gate level modeling.


Circuit Diagram:
a
x
b
Truth Table:

Input OutPut
a b x
0 0 1

0 1 1

1 0 1

1 1 0

Coding:
//design module
module gate(x,a,b);
input a,b;
output x;
nand a1(x,a,b);
endmodule

//stimulus module
module Talha;
reg a,b;
wire x;

Electronic Engineering Department


Sir Syed University Of Engineering And Technology
Name: Talha Mustafa Course Code: EE-380L
Roll No: 2020-EE-060 Section: B
gate g1(x,a,b);
initial
begin
a=1'b0; b=1'b0;
#30
a=1'b0; b=1'b1;
#30
a=1'b1; b=1'b0;
#30
a=1'b1; b=1'b1;
#30
$finish;
end
endmodule

Result:

Electronic Engineering Department


Sir Syed University Of Engineering And Technology
Name: Talha Mustafa Course Code: EE-380L
Roll No: 2020-EE-060 Section: B

Task 4: To design NOR gate using gate level modeling.


Circuit Diagram:

a
x
b

Truth Table:
Input OutPut
a b x
0 0 1

0 1 0

1 0 0

1 1 0

Coding:
//design module
module gate(x,a,b);
input a,b;
output x;
nor a1(x,a,b);
endmodule

//stimulus module
module Talha;

Electronic Engineering Department


Sir Syed University Of Engineering And Technology
Name: Talha Mustafa Course Code: EE-380L
Roll No: 2020-EE-060 Section: B
reg a,b;
wire x;
gate g1(x,a,b);
initial
begin
a=1'b0; b=1'b0;
#30
a=1'b0; b=1'b1;
#30
a=1'b1; b=1'b0;
#30
a=1'b1; b=1'b1;
#30
$finish;
end
endmodule

Result:

Electronic Engineering Department


Sir Syed University Of Engineering And Technology
Name: Talha Mustafa Course Code: EE-380L
Roll No: 2020-EE-060 Section: B

Task 5: To design NOT gate using gate level modeling.


Circuit Diagram:

a Out

Truth Table:
Input OutPut
a Out
0 1

1 0

Coding:
//design module
module gate(out,a);
input a;
output out;
not a1(out,a);
endmodule
//stimulus module
module wasif;
reg a;
wire out;
gate g1(out,a);
initial

Electronic Engineering Department


Sir Syed University Of Engineering And Technology
Name: Talha Mustafa Course Code: EE-380L
Roll No: 2020-EE-060 Section: B
begin
a=1'b0;
#30
a=1'b1;
#30
$finish;
end
endmodule

Result:

Electronic Engineering Department


Sir Syed University Of Engineering And Technology

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