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This document contains VHDL code for several basic digital logic components: 1) A 2-input decoder with outputs S0, S1, S2 that are individually activated depending on the 2-bit input E. 2) A comparator that outputs a signal egal which is high if its two 8-bit inputs A and B are equal. 3) A frequency divider that takes a clock signal hor as input and outputs a divided signal sort with half the frequency. It implements this using an integer counter and flip-flop. 4) A D-type flip-flop with asynchronous reset and a 3-stage shift register made by connecting three of these flip-flops.

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43 views4 pages

Prepa Exam

This document contains VHDL code for several basic digital logic components: 1) A 2-input decoder with outputs S0, S1, S2 that are individually activated depending on the 2-bit input E. 2) A comparator that outputs a signal egal which is high if its two 8-bit inputs A and B are equal. 3) A frequency divider that takes a clock signal hor as input and outputs a divided signal sort with half the frequency. It implements this using an integer counter and flip-flop. 4) A D-type flip-flop with asynchronous reset and a 3-stage shift register made by connecting three of these flip-flops.

Uploaded by

HAHA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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https://www.enib.fr/~kerhoas/vhdl_cours_pwm.

html

decodeur :

library IEEE;
use IEEE.std_logic_1164.all;

entity decodeur is
port( E : in std_logic_vector(1 downto 0);
S0,S1,S2 : out std_logic);
end decodeur;

architecture arch_decodeur of decodeur is


begin
S0<='1' when E="00" else '0';
S1<='1' when E="01" else '0';
S2<='1' when E="10" else '0';
end arch_decodeur;

comparateur :

library IEEE;
use IEEE.std_logic_1164.all;

entity comparateur is
port( A,B : in std_logic_vector(7 downto 0);
egal : out std_logic);
end comparateur;

architecture arch_comparateur of comparateur is


begin
egal <= '1' when A=B else '0';

end arch_comparateur;

diviseur_10

-- div_10.vhd
entity div_10 is
port( hor : in bit ;
sort : buffer bit );
end div_10 ;
architecture piege of div_10 is
begin
diviseur : process
variable compte : integer range 0 to 5 := 0 ;
begin
wait until hor = '1' ;
compte := compte + 1 ;
if compte = 5 then
compte := 0 ;
sort <= not sort ;
end if ;
end process diviseur ;
end piege ;
architecture perverse of div_10 is
signal compte : integer range 0 to 4 := 0 ;
begin
diviseur : process
begin
wait until hor = '1' ;
compte <= compte + 1 ;
if compte = 4 then
compte <= 0 ;
sort <= not sort ;
end if ;
end process diviseur ;
end perverse ;

architecture correcte of div_10 is


signal compte : integer range 0 to 4 := 0 ;
begin
diviseur : process
begin
wait until hor = '1' ;
if compte = 4 then
compte <= 0 ;
sort <= not sort ;
else
compte <= compte + 1 ;
end if ;
end process diviseur ;
end correcte ;

exercice google :
Soit une bascule D avec remise à zéro RST asynchrone

library ieee;
use ieee.std_logic_1164.all;
entity bascule is
port (
rst,H,D : in std_logic;
Q : out std_logic);
end bascule;
architecture arch of bascule is
begin
process(H,rst)
begin
if rst<='1' then
Q<='0';
elsif H'event and H='1' then
Q<=D;
end if;
end process;
end arch;

3 bascule (decalage)

library ieee;
use ieee.std_logic_1164.all;
entity decalage is
port (
E,clk, rst : in std_logic;
Q1, Q2, Q0 : out std_logic);
end decalage;
architecture arch of decalage is
component bascule
port (
rst,H,D : in std_logic;
Q : out std_logic);
end component;
signal S1,S2 : std_logic;
Q0<=S1;
Q1<=S2;
U1 : bascule port map( E,clk,rst,S1);
U2 : bascule port map(clk,rst,S1,S2);
U3 : bascule port map(clk,rst,S2,Q2);
end arch;

implusion de periode 40 ns
ARCHITECTURE simple OF hor_simple IS
BEGIN
horloge: PROCESS
BEGIN
WAIT FOR 20 ns;
hor <= NOT hor;
END PROCESS horloge;
END simple;

Boucle :

when else (MUX)


X=A when C1 else
B when C2 else
C when C3 else
D;

with select (on ecrit le variable par ex c avec 4 bit de 0 a 3


puis on met with c select cad la variation de c
c va prendre 0 , 1 , 2 , 3 un variable va changer a chaque fois que c
change)

combinatoire=l'ordre n'est pas important

7segment:
entity decod7seg is
port(
InSeg : IN std_logic_vector(3 downto 0);
OutSeg : OUT std_logic_vector(6 downto 0)
);
end decod7seg;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
--definition de l'architecture
architecture arch_dec_7seg of decod7seg is
-- definition d'un nouveau type
-- tableau de 16 elements de 7 bits
type MemROM is array(15 downto 0) of
std_logic_vector(6 downto 0);
--initialisaion du tableau
-- tableau vu comme une memoire(LUT)
signal Tableau : MemROM := (
"1000000","1111001","0100100","0110000","0011001",
"0010010","0000010","1111000","0000000","0011000","
0001000","0000011" ,"1000110","0100001","0000110","
0001110");
begin
-- pour indexer tableau il faut un entier
-- fonction de conversion conv_integer dans
IEEE.std_logic_unsigned.all
OutSeg <= Tableau(conv_integer(InSeg));
end arch_dec_7seg;

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