Programmable Peripheral Interfacing Chips 415 Delay subrout:in UPi: Mov CX, 800ch UP2: LOOP UP2 DEC BL INZ PL RET Delay ENDP CODE ENDS END Start ALE = LA ADy-ADis a 6.6.5) 8 & 8 WRE—a 2 © ROL 415 pecoder Pr] RD 5 EP) 8 tom} +c TS 6 iow Pay Control signal generator Even por Ay Ay oo 6, 6.6.5] As Oh oe Reset TKO Decoder t ~c 3 Clock Chip select ogie enerator oo Figure 12.31 Interfacing of Example 12.10 12.9 INTERFACING OF STEPPER MOTOR Stepper motor is a device used to obtain an accurate position control of rotating shafts. ‘A stepper motor employs rotation of its shaft in terms of steps. rather than continuous rotation as in case of AC or DC motor. To rotate the shaft of the stopper motor, a sequence of pulses is needed to be applied to the windings of the stepper motor, in proper sequence. The numbers416 Microprocessor 808¢—Atrchitecture, Programming ane Interfacing of pulses required for complete rotation of the shaft of the stepper motor are equal to the number of internal tecth on its rotor. The stator teeth and the rotor teeth lock with each other to fix a position of the shaft. With a pulse applied to the winding input, the rotor rotates by cone teeth position or an angle x. The angle x may be calculated as: 3600/mumber of rotor teeth After the rotation of the shaft by an angle x, the rotor locks itself with the next tooth of the stator. The diagram of a stepper motor with four windings is shown in Figure 12.32, Pha Permanent magnet Figure 12.32 Cross-section of a two-phase hybrid motor ‘The stepper motors have been designed to work with digital circuits. Binary level pulses of 0-5 V are required at its winding inputs to obtain the rotation of the shafts. The sequence of the pulses can be decided, depending upon the required motion of the shal By suitable sequence of the pulses, the motor can be used cither in full stepping or in half stepping, In full stepping the motor moves 1,8 degrees and to do these two bits are changed simultancously. One such arrangement of bits is shown in Table 12.6. Table 12.6 Bit patter in fell stepping Me Steps A BC D_ Hex value 1 00 1 Os 2 01 1 0 Ost Clockwise | 3 1 1G 0 0ck 4 10 0 1 OOH 5 00 1 os er 2 10 0 1 OSH Anticlockwise] 3. 1-10 4 old) 590 0 0Programmable Peripheral Interfacing Chips 417 In half stepping bit is changed at a time and the motor moves by 0.9 degrees. The bit pattern for half stepping is shown in Table 12.7. Table 12.7 Bit pattern in half stepping ‘Motion Steps A tod 2 41 31 400 Clockwise 450 6 0 7 0 Boo Pet 14 2 0 30 40 Anticlockwise} $0 an) 7 4 Bo a4 Working o ° 0 0 Hex value 0A os 09 ol 05 oa 06 02 0A OA 02 06 o4 0s o1 09 08 OA 8255 is interfaced with 8086 in IO mapped 10, Port C (PCo, PC), PC, and PC;) is used to sive pulse sequence to stepper motor. The 8255 provides very less current which will not be able to drive stepper motor coils so each of the winding of stepper motor needs to be interfaced using coil driver. Figure 1 32 shows the interfacing of stepper motor with 8255 EXAMPLE 12.12 To interface stepper motor to $086 using 8255, write the assembly language program to rotate stepper motor in clockwise and anticlockwise directions Solution Let the addresses of the ports and the CWR are’ Even port ASH = Port A AAH = Port B ACH = Port C AEH = CWR Assembly language program to rotate stepper motor in clockwise direction START: MOV AL CHR OUT AEH, AL @O: MOV AL, O3H : Load CAR in AL418 Microprocessor 8086—srchitecture, Programming and Interfacing ALE ve pe AL AD-AD., oP Latch FAs Deb, Vee i 8 a aresy 2 Pha wet —fa' ox SL J aver 8 RD 1B pecoter PE] 80 rf PTO hve ULN 2 12 Pow p>} 2003 8 Cont signal generate — AA tif | as, os A ag Reset 8 Decoer t jc 5 ‘Clock Chipset og erect 84 Figure 12.33 Interfacing of stepper motor OUT ACH, AL MOV CX, OFFFFH WP: L00P WP + Introduce delay WOW AL, GH OUT ACH, AL MOV CX, OFFFFH UP1: LOOP UP1 : Introduce delay MOV AL, OCH OUT ACH, AL MOV OX, OFFFFH UP2: LOOP UP2 : Introduce delay MOV AL, OSHProgrammable Peripheral Interfacing Chips 419 OUT ACH, AL MOV CX, OFFFFH UP3: LOOP UP3 We INT 03H END START : Introduce delay + Reoeat outout sequence Assombly language program to rotate stepper motor in anticlockwise direction START: MOV AL, CAR OUT AEH, AL @O: MOV AL, O3H OUT ACH, AL MOV CX, OFFFFH UP: LOOP UP MOV AL; OSH OUT ACH, AL MOV OX, OFFFFH UP1: LOOP UPA MOV AL, ODH OUT ACH, AL MOV CX, OFFFFH UP2: LOOP UP2 MOV AL, O6H OUT ACH, AL MOV CX, OFFFFH UP3: LOOP UP3 We 00 INT 03H END START : Load CAR in AL : Introduce delay + Introduce delay 1 Introduce delay : Introduce delay + Reveat outout sequerce 12.9.1 Interfacing of DAC 0800 ‘The DAC 0808 is a monolithic 8-bit high speed current output digital to analog converter. It also features high compliance complementary current outputs to allow differential output voltage. Features of DAC 0800 1, Settling output current 100 ns Full scale error + 1 LSB 2. Full scale error = I LSB420 Microprocessor 808¢—Atrchitecture, Programming ane Interfacing Non linearity over temperature + 0.1% ‘omplementary current outputs Can be interfaced directly with TIL, CMOS, etc. 6. Wide power supply range 4 4.5 V to 418 V 7. Low power consumption 33 mW at +5 V 8. Allows differential output voltages of 20 V pp with simple resistive loads. 4. 5 Pin configuration and block diagram of DAC 0800 ‘The pin configuration of DAC 0800 is shown in Figure 12.34. It consists of 16 pins tmestatd to oo cont Vie] LS compensation lu] LS Vass vl ly, lon 3 our] DAC [Vv wisen 3} 0800 Lp. op 24 Lp, a [w,, 8 9 Bo LB, Figure 12.34 Pin configuratio ‘As shown in Figure 12.34 this chip outputs two currents, i.e, -ve Ioy.7 and +ve Ioqrps so to convert these current signals we have fo use a current to voltage converter as shown in Figure 12.35. nv -2Vv Figure 12.38 DAC 0800 with an op-amp based current to voltage converterProgrammable Peripheral Interfacing Chips 421 ‘The block diagram of DAC 0800 is shown in Figure 12.36 Msp LsB Vo Ve By BoB BB BB ts fi fs Jo Jr Js fo fro_fu_foo Bias 4a network lot Content " vtheld b switches P+ Tove 3 13 vie REE AMP DACOB ie come Figure 12.36 Block diagram of DAC 0800 When chip select of DAC is enabled, then DAC will convert digital input value given through portliness PB,-PB, to analog value. The analog output from DAC is a current quantity This current is converted to voltage using OPAMP based current-to-vollage converter. The voltage outputs (+/- 5 V for bipolar, 0 to 5 V for unipolar mode) of OPAMP may be connected to CRO to see the waveform. EXAMPLE 12.13 Interface an 8-bit DAC from 0808 to 8086 through 8255 in IO mapped 10 technique, Write the following programs for this interface: (a) Assembly language program to generate square wave (b) Assembly language program to generate triangular wave (c) Assembly language program to generate ramp wave (@) Assembly language program to gencrate staircase wave. Solution The interfacing is shown in Figure 12.37, ‘The port addresses and the address of the CWR may be decoded from this interfacing as A Ag As Ay As AS AL A, 10 0 1 1 0 0 0 = 98H = Port A 10 0 1 1 0 1 0 = 9AH = Pot B 10 0 1 1 1 0 0 =9CH = Port C 10 0 1 1 1 1 0 = 98H = CWR Decided by chip select logic ‘The control word will be 80H422 Microprocessor 808¢—Atrchitecture, Programming ane Interfacing ALE AD GAD ery — Pee 5, OG arg | 2 |. 2H Il WRE—FA ag 5 aVctk —-& 8 Rot 45 . ->————>\ap- 5 son peter fae or an pro Ti ® cow Giosk ‘ cont sgl generis, enor ven port ex Reset Goce Chip sea Tosi snr me Figure 12.37 Interfacing of Example 12.13, grams: (a) Assembly language program to generate the square wave shown in Figure 12.38, Figure 12.38 Square wave MOV AL, 80H : Initialize all ports as output OUT 9EH; AL : Loads CHR UP: MOV AL, OOH OUT 9AH, AL : Output 00 for OV level CALL DELAY =: Call delayProgrammable Peripheral Interfacing Chips 423 MOV AL, FF : Output FF for 5V level OUT 9AH, AL CALL DELAY = Call delay ye we (b) Assembly language program to generate the triangular wave shown in Figure 12.39. sv ov ASAIN Figure 12.39 Tunguar wave Initialize all ports as outgut Loads ChR Output co for o V level Output co for 0 V level NOV AL, 80H OUT SEH, Al BEGIN: MOV AL, ooH UP: OUT 9AM, AL INC AL To raise wave fror 0 V to 5 V increment A MP AL, ocH iNz : Jump UP till rising edge is reached, i.e. sv MOV AL, FFH UP1: QUT 9AH, AL DEC AL : To fall wave from 5 V to 0 V decrement AL MP AL, FFH INZ WPA : Juro UP till falling edge is reached, ives ov IMP BEGIN (©) Assembly language program to generate the ramp wave as shown in Figure 12.40, WINN ov Figure 1240, Ramp wave. NOV AL, 80H: Initialize all ports as outout OUT SEH, AL : Loads ChR MOV BL, FFH : Take FFH in B analog equivalent to 5 V RAWP: MOV AL; BL : Cosy to AL QUT 9AH, AL And cutout it on the port DEC BL : To generate rap wave this 5 V is continuously decreased till o424 Microprocessor 8086—Atrchitecture, Programming ane Interfacing JNZ RAP: Juma to RAMP if not 0 MOV BL, FFH : To generate the sane wave tris procedure is repeated INP RAYP HLT (@ Assembly language program to generate the staircase wave as shown in Figure 12.41 sv asv ov. Figure 12.41 Staircase wave MOV AL, 80H : Initialize all ports as output OUT SEH, AL : Loads Ch UP: MOV AL, OOH CALL OUT: And wait for sone tine MOV AL, FFH : Outout FF for 5 V level CALL OUT: And wait for sone tine MOV AL, O7FH : Outout 7F for 265 V level CALL OUT =: And wait for sone tine PP OUT: OUT Ak, AL MOV CX, FFH DELAY: LOOP DELAY : To add DELAY HUT 12.9.2. Interfacing of ADC0800 8-Bit A/D Converter The ADCO80O is an 8-bit monolithic A/D converter using P channel ion-implanted MOS technology. It contains a high input impedance comparator, 256 series resistors and analog switches, control logic and output latches. Conversion is performed using a successive approximation technique where the unknown analog voltage is compared to the resistor tic points using analog switches. When the appropriate tie point voltage matches the unknown voltage, conversion is complete and the digital outputs contain an 8-bit complementary binary word corresponding to the unknown. Operation The ADCO800 contains a network with 256-300 Q resistors in series. Analog switch taps are ‘made at the junction of each resistor and at each end of the network. In operation, a reference (10.00 V) is applied across this network of 256 resistors. An analog input (V;x) is first compared to the centre point of the ladder via the appropriate switch. If Vix is larger thanProgrammable Peripheral Interfacing Chips 425 ‘Vaup/2, the intemal logic changes the switch points and now compares Vix and 3/4 Vy This process, known as successive approximation, continues until the best match of Viy and ‘Vup!N is made. N now defines a specific tap on the resistor network. When the conversion is complete, the logic loads a binary word corresponding to this tap into the output latch and an end of conversion (EOC) logic level appears. The output latches hold this data valid until ‘a new conversion is completed and new data is loaded into the latches. The data transfer ‘occurs in about 200 ns so that valid data is present virtually all the time in tho latches. ‘The data outputs are activated when the output enable is high, and in tri-state when output enable is low. The devico may be operated in the free running mode by connecting the start conversion line to the end of conversion line. However, to ensure start-up under all possible conditions, an external start conversion pulse is required during power up conditions. ‘The block diagram of ADC 0800 is shown in Figure 12.42 Newwork Vos ‘op (MOS body) 5 qo Hs cock 6 fe} So stant Selection and contol logic Sond of (oc) Beit atch Ig, enable (Comparator Se Digital z FPS TSAI ground Vin MsB. LsB analog input Complementary digital output Figure 12.42 Block diagram of ADCO800 8-bit A/D converter ship.426 Microprocessor 808¢—Atrchitecture, Programming ane Interfacing ‘The reference applied across the 256 resistor network determines the analog input range Vey = 10.00 V with the top of the R-nctwork connected to SV and the bottom connected to-5 V gives a range of -5 V to +5 V. The reference can be level shifted between Vs and Veo, However, the voltage, applied tothe top of the R-network (pin 15), must not exceed Vs to prevent forward biasing the on-chip parasitic silicon diodes exist between the Pediffused resistors (pin 15) and the N-type body (pin 10, Vg). The use of a standard logic power supply for Vz can cause problems, both due to initial voltage tolerance and changes over temperature. A solution is to power the Vg line (15 mA max drain) from the output of the op amp that is usod to bias the top of the Renctwork (pin 15). The analog input voltage and the voltage that is applied to the bottom of the R-network (pin 5) must be at least 7 V above the Veg supply voltage to ensure adequate voltage drive to the analog switches. Other reference voltages may be used (such as 10.24 V). If'a 5 V reference is used, the analog range will be $V and accuracy will be reduced by a factor of 2. Thus, for maximum accuracy, it is desirable to operate with at least a 10 V reference. For TTL logic levels, this requires 5 V and 5 V for the Renetwork. CMOS can operate at the 10 Vz. Vss level and a single 10 Vp, reference can be used. All digital voltage levels for both inputs and outputs will be from ground to Vss A start pulse that occurs while the A/D is busy will reset the SAR and start a new conversion with the EOC signal remaining in the low state until the end of this new conversion. ‘When the conversion is complete, the EOC line will go to the high voltage state. An additional 4 clock periods must be allowed to elapse after EOC goos high, before a new conversion cycle is requested. Start conversion pulses that occur during this last 4 clock period interval may be ignored. The transfer of the new digital data to the output is initiated when BOC goes to the high voltage state ADGos08, ADCOBO9 ‘The ADCO808, ADCO809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control, logic, The 8-bit A/D converter uses successive approximation as the conversion technique ‘The converter features a high impedance chopper stabilized comparator, a 256 R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. The device climinates the need for external zero and full-scale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL tri-state outputs. ‘The design of the ADCO808, ADCO809 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The ADC0808, ADCO809 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. The block diagram and the pin diagram of ADC 0808 are shown in Figures 12.43 and in 12.44, ‘The device contains an 8-channel single-ended analog signal multiplexer, A particular input channol is selected by using the addross decoder. Table 12.8 shows the input states for the address lines to select any channel, The address is latched into the decoder on the low- to-high transition of the address latch enable signal,Programmable Peripheral Interfacing Chips 427 Start Clock [etna 1 | a / Sine Foner ectomis | | | Ele multiplexing | i 3). | imtos + us] —t ay oni fo oe “ | Comparator wa | | BY Se) EB} ect oupus 7 | pM) a ES ! (pa ie + Switch wee Saal L 2 (Pacts | 4 adress Jateh and | 5 [ae 4 L [255 Kriss Address tli tah cit | eae SBE 500 kik} CLK oF} — 5.000V—]Vuy — BoC 0.000 pisos, sn on, Tbs, aD, —Ja oy | $e Sd.—fo. sncome [2 2 A Je Aneowes SF 3P8 > fee, iss SV supply Veo TV | Ground —]GND 0-5V analog, input range Typ —Va9 | gure 12.44 Pin diagram of ADCOSO8, ADCO8OY converter ebip.428 Microprocessor 808¢—Atrchitecture, Programming ane Interfacing ‘Table 12.8 Selection analog inputs by multiplexer Selected analog channel ‘Address line B IN, 1 LoL IN L Low IN, L HOOL IN, L HOH IN, HOLL IN, HOOL oH IN HOH OL IN, HOH oH ‘The heart of this single chip data acquisition system is its 8-bit analog-to-digital converter. ‘The converter is designed to give fast, accurate, and repeatable conversions over a wide range of temperatures. The converter is partitioned into three major sections: the 256 R ladder network, the successive approximation register, and the comparator, The converter’s digital ‘outputs are positive true. The 256 R ladder network approach was chosen over the conventional RY2R ladder because of its inherent monotonicity, which guarantees no missing digital codes. ‘Monotonicity is particularly important in closed loop feedback control systems. A non-monotonic relationship can cause oscillations that will be catastrophic for the system, Additionally, the 256R network docs not cause load variations on the reference voltage. ‘The bottom resistor and the top resistor of the ladder networks are not the same value as the remainder of the nctwork. The difference in these resistors causes the output characteristic to be symmetrical with the zero and full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached +1/2 LSB and succeeding output transitions occur every 1 LSB later up to full-scale, ‘The successive approximation register (SAR) performs 8 iterations to approximate the input voltage, For any SAR type converter, n-iterations are required for an n-bit converter. In the ADCO808, ADCO809, the approximation technique is extended to 8-bits using the 256 R network. The A/D converter’s successive approximation register (SAR) is reset om the positive edge of the start conversion start pulse. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the end-of- conversion (EOC) output to the SC input. If used in this mode, an external start conversion pulse should be applied after power up. End-of-conversion will go low between 0 and 8 clock pulses after the rising edge of start conversion, The most important section of the A/D converter is tho comparator. It is this section which is responsible for the ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the repeatability of the device, A chopper-stabilized comparator provides the most effective method of satisfying all the converter requirements, ‘The chopper-stabilized comparator converts the DC input signal into an AC signal, ‘This signal is then fed through a high gain AC amplifier and has the DC level restored This technique limits the drift component of th amplifier since the drift is a DC componentProgrammable Peripheral Interfacing Chips 429 which is not passed by the AC amplifier. This makes the entire A/D converter extremely insensitive to temperature, long-term drift and input offset errors, EXAMPLE 12.14 Draw an interfacing diagram to interface an 8-bit analog to digital converter from 8255 to 8086. Write a program to take samples of input analog signal at an interval of 2s, convert it into digital and save it at memory location 9000H, Solution While interfacing an ADC to 8255 we must know the signals which are available in 0800 ADC which are to be interfaced. Here we have three signals, which control the conversion operation. These are’ SOC (start of conversion): ‘This signal is input to the 0800 and tells the convertor when to start the conversion process EOC (end of conversion): ‘This is an output from the convertor and tells that conversion process ends. OE (output enable): This signal is also input to the 0800 and tells the convertor when to output the converted digital signal In this interfacing diagram the SOC and OE signals are interfaced to the PB, and PB, pins of 8255 and the EOC is interfaced through the PC, pin of 8255, The digital output is made available through the port PA. ‘The addresses to the ports and the CWR are A, Ag Ag Ay A, AS AL Ay 10 0 1 1 0 G 0 =98H = Porta 10 0 1 1 0 1 0 = 9AH = Port B 10 0 1 1 1 0 0 =9CH = Porc 10 0 1 1 1 1 0 = 9EH = CWR Decided by chip select logic ‘The control word format and the control word is shown in Figure 12.45 D, b> [>> [>> oI To pnt, top {+9 port = oxtpt ____ somos orc, Ls port cy =toput oy ry bp port top ____s00 od of, (_________+: 0 tose430 Microprocessor 8086—Atrchitecture, Programming ane Interfacing ‘The data to start the conversion process, end the conversion process and to make the output available are: D, Dy 0 0 0 0 oo D, Hex Code Process 0 01H soc 0 02H OB 1 01H EOC igure 12.46. Dd, 0 I 0 coop ALE AD,-AD), Late C pak] 0,0, DeD, pa,-—ssoc loc P38, sor i ADC 0800 PC —f Eo 6, 6,0 6,5] wr}—+]a se ck RD}—+1B Decoder Ro t rr afc wR om row Clock ‘Control signal generator generator Even port Clock Chip select logic fener Figure 12.46 Interfacing of Example 12.14 Program: NOV SI, 2000H —: Initialize menory pointer NOV AL, 99H OUT 9A, AL : Initialize 9255Programmable Peripheral Interfacing Chips 431 UP: MOV AL, 1H OUT 9A, AL : Send SOC LooP: IN AL, 9cH Check for the EOC signal AND AL, ott Nask other bits except PCO HP AL, nH 2 Check PCO bit INZ_ LOOP : Is PCO = 4, if not go to loop MOV AL, 02H OUT AH, AL : Send OE signal IN AL, 98H Input digital data mov [SI], AL Store the result in menory INC ST : Increase the menory pointer by 1 CALL Delay : Introduce the 2s delay IMP OP Multiple Choice Questions 1, In 8255, under the 1/0 mode of operation we have ... modes. @3 (b) 2 o4 @3 2. Under which mode will have the following features, (i) A 5-bit control port is available. (i) Throe 1/0 lines are available at port C. (a) Mode 2 (b) Mode 2 (©) Mode 3 (@) Mode 2 3. BSR mode, ie, bit setireset made is present in (@) 8255 (b) 8155 (©) 8237 @) 8036, 4. The 8255 consists of ... IO ports @ 2 ) 3 @4 @ 5 5S. BSR mode in 8255 is for (@) Port A (b) Port B (©) Port C (a) All of these. 6. For the selection of the port A the address lines A, and A, must be (@) 00 (b) ol ©) 10 @u 7. For the selection of the port B the address lines A, and Ay must be (@) 00 (b) o1 © 10 @u