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Lab 9 Excess-3 To Gray Code Conversion Using Nand Gates

This document describes an open-ended lab assignment on designing an excess-3 to Gray code converter using NAND gates. The lab has two parts - first, students are asked to implement the converter in hardware and second, model the circuit in Verilog. The pre-lab tasks involve making truth tables for excess-3 and Gray codes, deriving the Boolean equations, and drawing logic diagrams using various gates. The lab tasks require building the NAND gate implementation and simulating the Verilog model with test vectors to verify functionality.

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Zuha Fatima
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
359 views

Lab 9 Excess-3 To Gray Code Conversion Using Nand Gates

This document describes an open-ended lab assignment on designing an excess-3 to Gray code converter using NAND gates. The lab has two parts - first, students are asked to implement the converter in hardware and second, model the circuit in Verilog. The pre-lab tasks involve making truth tables for excess-3 and Gray codes, deriving the Boolean equations, and drawing logic diagrams using various gates. The lab tasks require building the NAND gate implementation and simulating the Verilog model with test vectors to verify functionality.

Uploaded by

Zuha Fatima
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Department of Electrical Engineering

Faculty Member: ____________________ Dated: ________________

Semester: __________________________ Section: ________________

Group No.:

EE-221: Digital Logic Design

Lab 09: Excess-3 to Gray Code Conversion using Nand Gates (Open Ended
Lab)

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7


Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performance of data in Tool Usage Safety and Team marks
Lab Report Work Obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

EE221: Digital Logic Design Page 1


Lab 09: Excess-3 to Gray Code Conversion using Nand Gates

This Open ended Lab has been divided into two parts:
In first part you are required to design and implement a Excess-3 to gray code converter.
The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you first
part.
Objectives:

 Understand steps involved in design of combinational circuits


 Understand binary codes for decimals and their hardware realization
 Write code for combinational circuits using Verilog Gate Level Modeling
 Design a circuit in Verilog by calling different modules

Lab Instructions

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva
session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The
students will get hard copy of lab report, complete the Pre-lab task before coming to
the lab and deposit it with teacher/lab engineer for necessary evaluation.
 The students will start lab task and demonstrate design steps separately for step-
wise evaluation(course instructor/lab engineer will sign each step after ascertaining
functional verification).
 Remember that a neat logic diagram with pins numbered coupled with nicely
patched circuit will simplify trouble-shooting process.
 After the lab, students are expected to unwire the circuit and deposit back
components before leaving.
 The students will complete lab task and submit complete report to Lab Engineer
before leaving lab.
 There are related questions at the end of this activity. Give complete answers.

EE221: Digital Logic Design Page 2


Pre-Lab Tasks: (To be done before coming to the lab)

1. In the lab you would be implementing an Excess-3 to gray code converter. Make a truth
table for both the codes by filling in the following tables and Simplify the expressions for
W,X,Y,Z in terms of A,B,C,D.( Use backside of the page if necessary). Use unused
combinations as don’t care conditions. Hint, u can take help from
http://engineeringproblemsandanswers.blogspot.com/2015/03/logic-circuits-1-digit-decimal-in-
excess-3-to-gray-code-converter.html

(2Marks- Individual. and Team Work)


HINT:
Dec Excess 3 code Gray Code
Our inputs and outputs are of 4-bit decimal
A B C D W X Y Z
values. You will have to make 4 K-Maps
(Consider W as independent function of
input variables A,B,C,D, Make K-Map and
simplify it). Arrive at the simplest
0 0 1 0 x x x x
expression for each output. Show your k-
0 0 0 1 1 mapping and equation simplification in
1 your lab report. Don’t copy and paste from
2 this link, other-wise you will get zero.

3
W=
4
5
X=
6 Y=
7
Z=
8
9
1 1 0 1 X X X X

EE221: Digital Logic Design Page 3


2. Draw the logic diagram for Excess-3 to gray code converter using AND, OR and NOT
gates in the space provided below. You can use 2,3,4 input gates if required. (2 Marks-
Modern tool usage)

3. Draw the logic diagram for Excess-3 to gray code converter using only NAND gates in
the space provided below, you can use 2,3,4 input Nand gates if required (3 Marks-
Individual. and Team Work)

4. Draw the logic diagram for Excess-3 to gray code converter using only NOR gates in
the space provided below, you can use 2,3,4 input Nor gates if required (3 Marks-
Individual. and Team Work)

EE221: Digital Logic Design Page 4


Lab Tasks: (To be completed in the lab)

Lab Task 1:

Implement Excess-3 to gray code converter using only NAND gates on hardware. Paste the
complete circuit diagram, depicting hardware results. (5 Marks - Analysis)

Dec Excess 3 Gray Code


Hardware result
A B C D W X Y Z
0
1
2
3
4
5
6
7
8
9

EE221: Digital Logic Design Page 5


Lab Task2:

Design and simulate the circuit k-map equations you obtained in Pre-lab task 1 in Verilog
dataflow modeling. Give the code and testbench and waveform in the space provided below.
(3Marks – Modern tool
usage)

EE221: Digital Logic Design Page 6

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