High Speed Op-amp Design: Compensation and

Topologies for Two-Stage Designs

Vishal Saxena
Department of Electrical and Computer Engineering
Boise State University
1910 University Dr., MEC 108
Boise, ID 83725
[email protected] and [email protected]

Saxena
Outline

Introduction
Two-stage Op-amp Compensation
Conclusion

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 INTRODUCTION

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Op-amps and CMOS Scaling

 The Operational Amplifier (op-amp) is a fundamental building

block in Mixed Signal design.
 Employed profusely in data converters, filters, sensors, drivers etc.
 Continued scaling in CMOS technology has been challenging
the established paradigms for op-amp design.
 With downscaling in channel length (L)
 Transition frequency increases (more speed).
 Open-loop gain reduces (lower gains).
 Supply voltage is scaled down (lower headroom) [1].

Saxena
 CMOS Scaling Trends

 VDD is scaling down but VTHN is almost constant.

 Design headroom is shrinking faster.
 Transistor open-loop gain is dropping (~10’s in nano-CMOS)
 Results in lower op-amp open-loop gain. But we need gain!
 Random offsets due to device mismatches.
[3], [4].

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Analog Design Getting Squeezed With Scaling

[5]

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Integration of Analog into Nano-CMOS?

 Design low-VDD op-amps.

 Replace vertical stacking (cascoding) by horizontal cascading of gain
stages (see the next slide).
 Explore more effective op-amp compensation techniques.
 Offset tolerant designs.
 Also minimize power and layout area to keep up with the
digital trend.
 Better power supply noise rejection (PSRR).

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 Cascoding vs Cascading in Op-amps
A Telescopic Two-stage Op-amp
A Cascade of low-VDD
Amplifier Blocks.
(Compensation not shown here)

VDD VDD VDD VDD VDD VDD

VDD

2 n-1

1
vm vp n vout

CL
Vbiasn Vbiasn Vbiasn

Stage 1 Stage 2 Stage (n-1) Stage n

VDDmin>4Vovn+Vovp+VTHP with VDDmin=2Vovn+Vovp+VTHP.

wide-swing biasing. [1]

 Even if we employ wide-swing biasing for low-voltage designs, three- or

higher stage op-amps will be indispensable in realizing large open-loop DC
gain.
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 TWO-STAGE OP-AMP COMPENSATION

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 Direct (or Miller) Compensation
 Compensation capacitor (Cc)
between the output of the gain stages
VDD
causes pole-splitting and achieves
VDD
VDD dominant pole compensation.
M3 M4
1
M7
 An RHP zero exists at
220/2
750Ω  Due to feed-forward component of
vm vp iC fb
vout the compensation current (iC).
M1 M2

iC ff CC 10pF 2 CL  The second pole is located at

30pF

M6TL
Vbias3
100/2
 The unity-gain frequency is
M6TR M8T

M6BL
Vbias4  A benign undershoot in step-
100/2
M6BR M8B response due to the RHP zero
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2. x10

All the op-amps presented have been designed in AMI C5N 0.5μm CMOS process with scale=0.3 μm and Lmin=2.
The op-amps drive a 30pF off-chip load offered by the test-setup.

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Drawbacks of Direct (Miller) Compensation

VDD VDD  The RHP zero decreases phase

VDD margin
M7
M3 M4
1  Requires large CC for
220/2
compensation (10pF here for a
vm
M1 M2
vp CC
vout
30pF load!).
10pF 2 CL  Slow-speed for a given load, CL.
30pF
Vbias3  Poor PSRR
M6TL 100/2
M6TR M8T
Vbias4  Supply noise feeds to the output
M6BL 100/2
M6BR M8B through CC.
Unlabeled NMOS are 10/2.
 Large layout size.
Unlabeled PMOS are 22/2.
x10

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 Indirect Compensation

VDD VDD VDD

VDD
 The RHP zero can be eliminated by
M3 M4 M9
blocking the feed-forward compensation
1 M7
220/2 current component by using
vm ic
 A common gate stage,
M1 M2 Cc
MCG
A
2 vout
CL
 A voltage buffer,
vp
Vbias3
30pF  Common gate “embedded” in the
M6TL
M6TR M10T M8T
100/2
cascode diff-amp, or
Vbias4
M6BL
M6BR M10B M8B
100/2
 A current mirror buffer.
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
 Now, the compensation current is fed-
x10
back from the output to node-1 indirectly
An indirect-compensated op-amp through a low-Z node-A.
using a common-gate stage.
 Since node-1 is not loaded by CC, this
results in higher unity-gain frequency
(fun).

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 Indirect Compensation in a Cascoded Op-amp
VDD VDD
M4T
M3T
A
ic VDD
M4B
Vbias2
M3B M7
110/2
1

vm vp CC CC
M1 M2 vout vout
2 CL CL
1.5pF vm vp
30pF

Vbias3
M6TL 50/2
M6TR M8T
Vbias4
M6BL 50/2
M6BR M8B

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 44/2.

Indirect-compensation using Indirect-compensation using

cascoded current mirror load. cascoded diff-pair.

 Employing the common gate device “embedded” in the cascode structure

for indirect compensation avoids a separate buffer stage.
 Lower power consumption.
 Also voltage buffer reduces the swing which is avoided here.
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Analytical Modeling of Indirect Compensation

The compensation
current (iC) is indirectly
fed-back to node-1.
Block Diagram

vout
ic 
1 sCc  Rc

RC is the resistance
attached to node-A.

Small signal analytical model

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Derivation of the Small-Signal Model

Resistance roc is
assumed to be large.

The small-signal model

for a common gate
indirect compensated op-
amp topology is
approximated to the
simplified model seen in
the last slide.

gmc>>roc-1, RA-1,
CC>>CA

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 Analytical Results for Indirect Compensation
j

 un


p3 p2 z1 p1

Pole-zero plot
LHP zero

 Pole p2 is much farther away from fun.

 Can use smaller gm2=>less power!
 LHP zero improves phase margin.
 Much faster op-amp with lower
power and smaller CC.
 Better slew rate as CC is smaller.

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Indirect Compensation Using Split-Length Devices

 As VDD scales down, cascoding is becoming tough. Then how to realize

indirect compensation as we have no low-Z node available?
 Solution: Employ split-length devices to create a low-Z node.
 Creates a pseudo-cascode stack but its really a single device.
 In the NMOS case, the lower device is always in triode hence node-A is a
low-Z node. Similarly for the PMOS, node-A is low-Z.

Split-length 44/4(=22/2)
NMOS PMOS PMOS layout

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Split-Length Current Mirror Load (SLCL) Op-amp
VDD VDD
VDD
M3T M4T ic
A 220/2
M3B M4B M7T

220/2
1
M7B
vm vp CC
M1 M2 vout
2pF 2 CL
30pF
Vbias3
M6TL 50/2
M6TR M8T Frequency Response
M6BL
Vbias4
50/2
M6BR M8B

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 22/2. ts

 The current mirror load devices are

split-length to create low-Z node-A.
 Here, fun=20MHz, PM=75° and
ts=60ns. Small step-input settling in follower
configuration

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 SLCL Op-amp Analysis
1 1 1
gmp gmp gmp
g m1
A  v A
gm1v s + gmp s
-
2 Cc Cc

1 vout 1 vout
id2 id1 2 id1 2
vs vs vs

2 2
CL CL
2

v=0
(a) (b)

rop A
Cc 2
1

+ +
gm1v s
+ 1 1
v1 vsgA vout
2 gmp gmp
R1 C1 gmpvsgA - CA gm2v1 R2 C2
gm 1
-  v -
gmp s

1 2  Here fz1=3.77fun
+ +
Cc
 LHP zero appears at a higher
v1 vout
frequency than fun.
g m1v s 1
R1 C1 ic gm2v1 R2 gmp C2

- -
vout
ic  1 1

sCc gmp

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 Split-Length Diff-Pair (SLDP) Op-amp
VDD VDD
VDD
M3 M4
M7
1 110/2
M1T vp
vm M2T
20/2 20/2 ic vout
A
2pF 2 CL
20/2 20/2 CC 30pF
M1B M2B

Vbias3
M6TL
M6TR M8T
50/2 Frequency Response
M6BL
Vbias4
50/2
M6BR M8B

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 22/2.

 The diff-pair devices are split-length to

create low-Z node-A.
 Here, fun=35MHz, PM=62°, ts=75ns.
Small step-input settling in follower
 Better PSRR due to isolation of node-A configuration
from the supply rails.
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 SLDP Op-amp Analysis

vout vout
vs vs
 vs
2 2 2

1 1
gmn v s 1
gmn gmn id 2   gmn
4

Cc

A ron 1
2

+ +
1
gmn
vA
1
gmn
+
vgs1 vout
 Here fz1=0.94fun,
- gmnvgs1 R1 C1 gm2v1 R2 C2
CA
 LHP zero appears slightly before
gmn v s
4
- vs -
2
fun and flattens the magnitude
1 2 response.
+ +
gmn v s
Cc
 This may degrade the phase
v1
2
R1 C1 ic gm2v1 R2
1
gmn
vout
C2 margin.
-
vout
-
 Not as good as SLCL, but is of
ic  1

1
sCc gmn great utility in multi-stage op-amp
design due to higher PSRR.
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Test Chip 1: Two-stage Op-amps

Miller 3-Stage Indirect

SLDP
SLCL Indirect
Indirect

Miller with Rz

 AMI C5N 0.5μm CMOS, 1.5mmX1.5mm die size.

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Test Results and Performance Comparison
Performance comparison of the op-amps for CL=30pF.

Miller with Rz (ts=250ns)

SLCL Indirect (ts=60ns)  10X gain bandwidth (fun).

 4X faster settling time.
 55% smaller layout area.
 40% less power consumption.

SLDP Indirect (ts=75ns)

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 Effect of LHP-zero on Settling
Bode Diagram
80

 In certain cases with indirect 60

Magnitude (dB)
40

compensation, the LHP-zero (ωz,LHP) 20

shows up near fun.

0

-20

 Causes gain flattening and degrades PM

-40
180

 Hard to push out due to topology

135

Phase (deg)
90

restrictions 45

 Ringing in closed-loop step response 0

10
2

Frequency
10
4

Response 10
6
10
8

Frequenc y (Hz )

 This ringing is uncharacteristic of the 2nd

order system.
Closed Loop Step Response
1

0.9

 Used to be a benign undershoot with the 0.8

RHP zero, here it can be pesky

0.7

0.6

Amplitude
 Is this settling behavior acceptable? 0.5

0.4

 Watch out for the ωz,LHP for clean settling 0.3

0.2

behavior! 0.1

0
0 0.2 0.4 0.6 0.8 1 1.2
Time (sec) -7
x 10

Small step-input settling in follower

configuration
Saxena
References

[1] Baker, R.J., “CMOS: Circuit Design, Layout, and Simulation,” 2nd Ed., Wiley Interscience, 2005.
[2] Saxena, V., “Indirect Compensation Techniques for Multi-Stage Operational Amplifiers,” M.S. Thesis, ECE Dept., Boise
State University, Oct 2007.
[3] The International Technology Roadmap for Semiconductors (ITRS), 2006 [Online]. Available:
http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm
[4] Zhao, W., Cao, Yu, "New Generation of Predictive Technology Model for sub-45nm Design Exploration" [Online].
Available: http://www.eas.asu.edu/~ptm/
[5] Slide courtesy: bwrc.eecs.berkeley.edu/People/Faculty/jan/presentations/ASPDACJanuary05.pdf
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IEEE Journal of Solid State Circuits, vol.32, no.12, Dec 1997.
[8] Grasso, A.D., Marano, D., Palumbo, G., Pennisi, S., "Improved Reversed Nested Miller Frequency Compensation
Technique with Voltage Buffer and Resistor," IEEE Transactions on Circuits and Systems-II, Express Briefs, vol.54, no.5,
May 2007.
[9] Lee, H., Mok, P.K.T., "Advances in Active-Feedback Frequency Compensation With Power Optimization and Transient
Improvement," IEEE Transactions on Circuits and Systems I, Fundamental Theory and Applications, vol.51, no.9, Sep
2004.
[10] Eschauzier, R.G.H., Huijsing, J.H., "A 100-MHz 100-dB operational amplifier with multipath Nested Miller
compensation," IEEE Journal of Solid State Circuits, vol. 27, no. 12, pp. 1709-1716, Dec. 1992.
[11] Leung, K. N., Mok, P. K. T., "Nested Miller compensation in low-power CMOS design," IEEE Transaction on Circuits and
Systems II, Analog and Digital Signal Processing, vol. 48, no. 4, pp. 388-394, Apr. 2001.
[12] Leung, K. N., Mok, P. K. T., Ki, W. H., Sin, J. K. O., "Three-stage large capacitive load amplifier with damping factor
control frequency compensation," IEEE Journal of Solid State Circuits, vol. 35, no. 2, pp. 221-230, Feb. 2000.

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References contd.

[13] Peng, X., Sansen, W., "AC boosting compensation scheme for low-power multistage amplifiers," IEEE Journal of Solid
State Circuits, vol. 39, no. 11, pp. 2074-2077, Nov. 2004.
[14] Peng, X., Sansen, W., "Transconductances with capacitances feedback compensation for multistage amplifiers," IEEE
Journal of Solid State Circuits, vol. 40, no. 7, pp. 1515-1520, July 2005.
[15] Ho, K.-P.,Chan, C.-F., Choy, C.-S., Pun, K.-P., "Reverse nested Miller Compensation with voltage buffer and nulling
resistor," IEEE Journal of Solid State Circuits, vol. 38, no. 7, pp. 1735-1738, Oct 2003.
[16] Fan, X., Mishra, C., Sanchez-Sinencio, "Single Miller capacitor frequency compensation technique for low-power
multistage amplifiers," IEEE Journal of Solid State Circuits, vol. 40, no. 3, pp. 584-592, March 2005.
[17] Grasso, A.D., Palumbo, G., Pennisi, S., "Advances in Reversed Nested Miller Compensation," IEEE Transactions on
Circuits and Systems-I, Regular Papers, vol.54, no.7, July 2007.
[18] Shen, Meng-Hung et al., "A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward
Compensation," IEEE Asian Solid-State Circuits Conference, 2006, p 171-174.

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