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CS2252

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MICROPROCESSORS

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&
MICROCONTROLLERS
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IT DEPARTMENT
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PREPARED BY
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S. THENMOZHI,
AP / ECE
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UNIT I

THE 8085 AND 8086 MICROPROCESSORS

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1.1 History of microprocessor
The invention of the transistor in 1947 was a significant development in the world of
technology. It could perform the function of a large component used in a computer in the early

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years. Shockley, Brattain and Bardeen are credited with this invention and were awarded the Nobel
prize for the same. Soon it was found that the function this large component was easily performed
by a group of transistors arranged on a single platform. This platform, known as the integrated chip
(IC), turned out to be a very crucial achievement and brought along a revolution in the use of
computers. A person named Jack Kilby of Texas Instruments was honored with the Nobel Prize for

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the invention of IC, which laid the foundation on which microprocessors were developed. At the
same time, Robert Noyce of Fairchild made a parallel development in IC technology for which he
was awarded the patent.
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ICs proved beyond doubt that complex functions could be integrated on a single chip with a
highly developed speed and storage capacity. Both Fairchild and Texas Instruments began the
manufacture of commercial ICs in 1961. Later, complex developments in the IC led to the addition
of more complex functions on a single chip. The stage was set for a single controlling circuit for all
the computer functions. Finally, Intel corporation's Ted Hoff and Frederico Fagin were credited
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with the design of the first microprocessor.

The work on this project began with an order from a Japanese calculator company Busicom to Intel,
for building some chips for it. Hoff felt that the design could integrate a number of functions on a
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single chip making it feasible for providing the required functionality. This led to the design of Intel
4004, the world's first microprocessor. The next in line was the 8 bit 8008 microprocessor. It was
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developed by Intel in 1972 to perform complex functions in harmony with the 4004.

This was the beginning of a new era in computer applications. The use of mainframes and huge
computers was scaled down to a much smaller device that was affordable to many. Earlier, their use
was limited to large organizations and universities. With the advent of microprocessors, the use of
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computers trickled down to the common man. The next processor in line was Intel's 8080 with an 8
bit data bus and a 16 bit address bus. This was amongst the most popular microprocessors of all
time.
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Very soon, the Motorola corporation developed its own 6800 in competition with the Intel's 8080.
Fagin left Intel and formed his own firm Zilog. It launched a new microprocessor Z80 in 1980 that
was far superior to the previous two versions. Similarly, a break off from Motorola prompted the
design of 6502, a derivative of the 6800. Such attempts continued with some modifications in the
base structure.

The use of microprocessors was limited to task-based operations specifically required for company
projects such as the automobile sector. The concept of a 'personal computer' was still a distant
dream for the world and microprocessors were yet to come into personal use. The 16 bit
microprocessors started becoming a commercial sell-out in the 1980s with the first popular one
being the TMS9900 of Texas Instruments.

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Intel developed the 8086 which still serves as the base model for all latest advancements in the
microprocessor family. It was largely a complete processor integrating all the required features in it.
68000 by Motorola was one of the first microprocessors to develop the concept of microcoding in

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its instruction set. They were further developed to 32 bit architectures. Similarly, many players like
Zilog, IBM and Apple were successful in getting their own products in the market. However, Intel

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had a commanding position in the market right through the microprocessorera.

The 1990s saw a large scale application of microprocessors in the personal computer applications
developed by the newly formed Apple, IBM and Microsoft corporation. It witnessed a revolution in

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the use of computers, which by then was a household entity.

This growth was complemented by a highly sophisticated development in the commercial use of
microprocessors. In 1993, Intel brought out its 'Pentium Processor' which is one of the most popular
processors in use till date. It was followed by a series of excellent processors of the Pentium family,

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leading into the 21st century. The latest one in commercial use is the Pentium Dual Core
technology and the Xeon processor. They have opened up a whole new world of diverse
applications. Supercomputers have become common, owing to this amazing development in
microprocessors. no
1.2 Introduction TO 8085

As discussed earlier, 8085 microprocessor was introduced by Intel in the year 1976. This
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microprocessor is an update of 8080 microprocessor. The 8080 processor was updated with
Enable/Disable instruction pins and Interrupt pins to form the 8085 microprocessor. Let us discuss
the architecture of 8085 microprocessor in detail.

Features of 8085 microprocessor

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Before knowing about the 8085 architecture in detail, lets us briefly discuss about the basic
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features of 8085 processor.

8085 microprocessor is an 8-bit microprocessor with a 40 pin dual in line package. The
address and data bus are multiplexed in this processor which helps in providing more control
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signals. 8085 microprocessor has 1 Non-maskable interrupt and 3 maskable interrupts. It provides
serial interfacing with serial input data (SID) and serial output data (SOD).

It has a set of registers for performing various operations. The various registers include
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· Accumulator (register A)

· Registers: B, C, D, E, H and L

· Stack pointer

· Program Counter

· Temporary register

· Instruction register

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1.3 .1 Architecture of 8085 microprocessor

8085 consists of various units and each unit performs its own functions. The various units of a

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microprocessor are listed below
· Accumulator

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· Arithmetic and logic Unit
· General purpose register
· Program counter
· Stack pointer

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· Temporary register
· Flags
· Instruction register and Decoder
· Timing and Control unit
· Interrupt control

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· Serial Input/output control
· Address buffer and Address-Data buffer
· Address bus and Data bus

Accumulator
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Accumulator is nothing but a register which can hold 8-bit data. Accumulator aids in storing
two quantities. The data to be processed by arithmetic and logic unit is stored in accumulator. It
also stores the result of the operation carried out by the Arithmetic and Logic unit.The accumulator
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is also called an 8-bit register. The accumulator is connected to Internal Data bus and ALU
(arithmetic and logic unit). The accumulator can be used to send or receive data from the Internal
Data bus.
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Arithmetic and Logic Unit

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There is always a need to perform arithmetic operations like +, -, *, / and to perform logical
operations like AND, OR, NOT etc. So there is a necessity for creating a separate unit which can
perform such types of operations. These operations are performed by the Arithmetic and Logic Unit
(ALU). ALU performs these operations on 8-bit data.

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But these operations cannot be performed unless we have an input (or) data on which the
desired operation is to be performed. So from where do these inputs reach the ALU? For this
purpose accumulator is used. ALU gets its Input from accumulator and temporary register. After
processing the necessary operations, the result is stored back in accumulator.

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General Purpose Registers

Apart from accumulator 8085 consists of six special types of registers called General Purpose
Registers. What do these general purpose registers do?
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These general purpose registers are used to hold data like any other registers. The general
purpose registers in 8085 processors are B, C, D, E, H and L. Each register can hold 8-bit data.
Apart from the above function these registers can also be used to work in pairs to hold 16-bit data.
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They can work in pairs such as B-C, D-E and H-L to store 16-bit data. The H-L pair works as a
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memory pointer. A memory pointer holds the address of a particular memory location. They can
store 16-bit address as they work in pair.

Program Counter and Stack Pointer

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Program counter is a special purpose register.

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Consider that an instruction is being executed by processor. As soon as the ALU finished
executing the instruction, the processor looks for the next instruction to be executed. So, there is a
necessity for holding the address of the next instruction to be executed in order to save time. This is

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taken care by the program counter. A program counter stores the address of the next instruction to
be executed. In other words the program counter keeps track of the memory address of the
instructions that are being executed by the microprocessor and the memory address of the next
instruction that is going to be executed.

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Microprocessor increments the program whenever an instruction is being executed, so that
the program counter points to the memory address of the next instruction that is going to be
executed. Program counter is a 16-bit register. Stack pointer is also a 16-bit register which is used
as a memory pointer. A stack is nothing but the portion of RAM (Random access memory).
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So does that mean the stack pointer points to portion of RAM?
Yes. Stack pointer maintains the address of the last byte that is entered into stack.
Each time when the data is loaded into stack, Stack pointer gets decremented. Conversely it is
incremented when data is retrieved from stack.
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Temporary Register:

As the name suggests this register acts as a temporary memory during the arithmetic and
logical operations. Unlike other registers, this temporary register can only be accessed by the
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microprocessor and it is completely inaccessible to programmers. Temporary register is an 8-bit

register. In the next article let us discuss about the
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FLAGS
TIMING AND CONTROL UNIT
INTERRUPT CONTROL
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Flags

Flags are nothing but a group of individual Flip-flops. The flags are mainly associated with
arithmetic and logic operations. The flags will show either a logical (0 or 1) (i.e.) a set or reset
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depending on the data conditions in accumulator or various other registers. A flag is actually a latch
which can hold some bits of information. It alerts the processor that some event has taken place.

But why are they called flags?

The possible solution is from the small flags which are found on the mail boxes in America. The
small flag indicates that there is a mail in the mail box. Similarly this denotes that an event has
occurred in the processor.

Intel processors have a set of 5 flags.

Carry flag

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Parity flag
Auxiliary carry flag
Zero flag
Sign flag

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Consider two binary numbers.

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For example:
1100 0000
1000 0000
When we add the above two numbers, a carry is generated in the most significant bit. The number

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in the extreme right is least significant bit, while the number in extreme left is most significant bit.
So a ninth bit is generated due to the carry. So how to accommodate 9 th bit in an 8 bit register? For
this purpose the Carry flag is used. The carry flag is set whenever a carry is generated and reset
whenever there is no carry.But there is an auxiliary carry flag? What is the difference between the
carry flag and auxiliary carry flag?

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Let‟s discuss with an example. Consider the two numbers given below
0000 0100, 0000 0101
When we add both the numbers a carry is generated in the third bit from the least significant
bit. This sets the auxiliary carry flag. When there is no carry, the auxiliary carry flag is reset. So
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whenever there is a carry in the most significant bit Carry flag is set. While an auxiliary carry flag
is set only when a carry is generated in bits other than the most significant bit. Parity checks
whether it‟s even or add parity. This flag returns a 0 if it is odd parity and returns a 1 if it is an even
parity. Sometimes they are also called as parity bit which is used to check errors while data
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transmission is carried out. Zero flag shows whether the output of the operation is 0 or not. If the
value of Zero flag is 0 then the result of operation is not zero. If it is zero the flag returns value 1.
Sign flag shows whether the output of operation has positive sign or negative sign. A value 0 is
returned for positive sign and 1 is returned for negative sign.
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Instruction Register and Decoder

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Instruction register is 8-bit register just like every other register of microprocessor. Consider
an instruction. The instruction may be anything like adding two data's, moving a data, copying a
data etc. When such an instruction is fetched from memory, it is directed to Instruction register. So
the instruction registers are specifically to store the instructions that are fetched from memory.
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There is an Instruction decoder which decodes the informations present in the Instruction register
for further processing.

Timing and Control Unit

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Timing and control unit is a very important unit as it synchronizes the registers and flow of
data through various registers and other units. This unit consists of an oscillator and controller
sequencer which sends control signals needed for internal and external control of data and other
units. The oscillator generates two-phase clock signals which aids in synchronizing all the registers
of 8085 microprocessor.

Signals that are associated with Timing and control unit are:

Control Signals: READY, RD‟, WR‟, ALE

Status Signals: S0, S1, IO/M‟

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DMA Signals: HOLD, HLDA

RESET Signals: RESET IN, RESET OUT

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Interrupt Control

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As the name suggests this control interrupts a process. Consider that a microprocessor is
executing the main program. Now whenever the interrupt signal is enabled or requested the
microprocessor shifts the control from main program to process the incoming request and after the
completion of request, the control goes back to the main program. For example an Input/output

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device may send an interrupt signal to notify that the data is ready for input. The microprocessor
temporarily stops the execution of main program and transfers control to I/O device. After
collecting the input data the control is transferred back to main program.

Interrupt signals present in 8085 are:

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INTR
RST 7.5
RST 6.5
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TRAP

Of the above four interrupts TRAP is a NON-MASKABLE interrupt control and other three are
maskable interrupts. A non-maskable interrupt is an interrupt which is given the highest priority in
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the order of interrupts. Suppose you want an instruction to be processed immediately, then you can
give the instruction as a non-maskable interrupt. Further the non-maskable interrupt cannot be
disabled by programmer at any point of time.Whereas the maskable interrupts can be disabled and
enabled using EI and DI instructions. Among the maskable interrupts RST 7.5 is given the highest
priority above RST 6.5 and least priority is given to INTR.
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Serial I/O control

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The input and output of serial data can be carried out using 2 instructions in 8085.
SID-Serial Input Data
SOD-Serial Output Data
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Two more instructions are used to perform serial-parallel conversion needed for serial I/O devices.
SIM
RIM

Address buffer and Address-Data buffer

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The contents of the stack pointer and program counter are loaded into the address buffer and
address-data buffer. These buffers are then used to drive the external address bus and address-data
bus. As the memory and I/O chips are connected to these buses, the CPU can exchange desired data
to the memory and I/O chips.The address-data buffer is not only connected to the external data bus
but also to the internal data bus which consists of 8-bits. The address data buffer can both send and
receive data from internal data bus.

Address bus and Data bus:

We know that 8085 is an 8-bit microprocessor. So the data bus present in the
microprocessor is also 8-bits wide. So 8-bits of data can be transmitted from or to the

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microprocessor. But 8085 processor requires 16 bit address bus as the memory addresses are 16-bit
wide. The 8 most significant bits of the address are transmitted with the help of address bus and the
8 least significant bits are transmitted with the help of multiplexed address/data bus. The eight bit
data bus is multiplexed with the eight least significant bits of address bus. The address/data bus is

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time multiplexed. This means for few microseconds, the 8 least significant bits of address are
generated, while for next few seconds the same pin generates the data. This is called Time

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multiplexing. But there are situations where there is a need to transmit both data and address
simultaneously. For this purpose a signal called ALE (address latch enable) is used. ALE signal
holds the obtained address in its latch for a long time until the data is obtained and so when the
microprocessor sends the data next time the address is also available at the output latch. This

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technique is called Address/Data demultiplexing.

1.3 .2 PIN CONFIGURATION OF 8085

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8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows

1. Power supply and clock signals

2. Address bus
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4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports
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1. Power supply and Clock frequency signals:

Vcc + 5 volt power supply

Vss Ground
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X1, X2 : Crystal or R/C network or LC network connections to set the frequency of

internal clock generator.
The frequency is internally divided by two. Since the basic operating timing frequency is 3
MHz, a 6 MHz crystal is connected externally.
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CLK (output)-Clock Output is used as the system clock for peripheral and
devices interfaced with the microprocessor.

2. Address Bus:

A8 - A15 (output; 3-state)

It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address;

3. Multiplexed Address / Data Bus:

AD0 - AD7 (input/output; 3-state)

These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus.

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During the opcode fetch operation, in the first clock cycle, the lines deliver the lower
order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
The CPU may read or write out data through these lines.

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4. Control and Status signals:

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ALE (output) - Address Latch Enable.
This signal helps to capture the lower order address presented on the multiplexed address /
data bus.

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RD (output 3-state, active low) - Read memory or IO device.
This indicates that the selected memory location or I/O device is to be read and that the data
bus is ready for accepting data from the memory or I/O device.
WR (output 3-state, active low) - Write memory or IO device.
This indicates that the data on the data bus is to be written into the selected memory location

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or I/O device.
IO/M (output) - Select memory or an IO device.
This status signal indicates that the read / write operation relates to whether the memory or
I/O device. no
It goes high to indicate an I/O operation.
It goes low for memory operations.

5. Status Signals:
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It is used to know the type of current operation of the microprocessor.
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1.4 ADDRESSING MODES

Every instruction of a program has to operate on a data.

The method of specifying the data to be operated by the instruction is called Addressing.
The 8085 has the following 5 different types of addressing.

1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
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4. Register Indirect Addressing
5. Implied Addressing

1. Immediate Addressing:

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In immediate addressing mode, the data is specified in the instruction itself. The data will be a

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part of the program instruction.

EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP,
2700H.

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2. Direct Addressing:

In direct addressing mode, the address of the data is specified in the instruction. The data will be
in memory. In this addressing mode, the program instructions and data can be stored in different

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memory.

EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator;
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3. Register Addressing:

In register addressing mode, the instruction specifies the name of the register in which the data
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is available.

EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.

4. Register Indirect Addressing:

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In register indirect addressing mode, the instruction specifies the name of the register in which
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the address of the data is available. Here the data will be in memory and the address will be in the
register pair.

EX. MOV A, M - The memory data addressed by H L pair is moved to A register.

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LDAX B.

5. Implied Addressing:

In implied addressing mode, the instruction itself specifies the data to be operated.
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EX. CMA - Complement the content of accumulator; RAL

1.5 Instruction sets

1.5.1 DATA TRANSFER INSTRUCTIONS

Move 8 bit Register

MOV Rd, Rs : This instruction copies the contents of the source M, Rs register into the destination
register; the contents of Rd, M the source register are not altered. If one of the operands is a
memory location, its location is specified by the contents of the HL registers.
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Example: MOV B, C or MOV B, M

Move immediate 8-bit

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MVI Rd, data The 8-bit data is stored in the destination register or M, data memory. If the operand
is a memory location, its location is specified by the contents of the HL registers.

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Example: MVI B, 57H or MVI M, 57H

Load accumulator

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LDA 16-bit address The contents of a memory location, specified by a 16-bit address in the
operand, are copied to the accumulator. The contents of the source are not altered.

Example: LDA 2034H

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Load accumulator indirect
LDAX B/D Reg. pair The contents of the designated register pair point to a memory location. This
instruction copies the contents of that memory location into the accumulator. The contents of either
the register pair or the memory location are not altered.
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Example: LDAX B

Load register pair immediate

LXI Reg. pair, 16-bit data The instruction loads 16-bit data in the register pair designated in the
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operand.

Example: LXI H, 2034H or LXI H, XYZ

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Load H and L registers direct

LHLD 16-bit address The instruction copies the contents of the memory location pointed out by the
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16-bit address into register L and copies the contents of the next memory location into register H.
The contents of source memory locations are not altered.

Example: LHLD 2040H

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Store accumulator direct

STA 16-bit address The contents of the accumulator are copied into the memory location specified
by the operand. This is a 3-byte instruction, the second byte specifies the low-order address and the
third byte specifies the high-order address.
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Example: STA 4350H

Store accumulator indirect

STAX Reg. pair The contents of the accumulator are copied into the memory location specified by
the contents of the operand (register pair). The contents of the accumulator are not altered.

Example: STAX B

Store H and L registers direct

SHLD 16-bit address The contents of register L are stored into the memory location specified by
the 16-bit address in the operand and the contents of H register are stored into the next memory

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location by incrementing the operand. The contents of registers HL are not altered. This is a 3-byte
instruction, the second byte specifies the low-order address and the third byte specifies the
high-order address.

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Example: SHLD 2470H

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Exchange H and L with D and E
XCHG none The contents of register H are exchanged with the contents of register D, and the
contents of register L are exchanged with the contents of register E.

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Example: XCHG

Copy H and L registers to the stack pointer

SPHL none The instruction loads the contents of the H and L registers into the stack pointer
register, the contents of the H register provide the high-order address and the contents of the L

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register provide the low-order address. The contents of the H and L registers are not altered.

Example: SPHL

Exchange H and L with top of stack

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XTHL none The contents of the L register are exchanged with the stack location pointed out by the
contents of the stack pointer register. The contents of the H register are exchanged with the next
stack location (SP+1); however, the contents of the stack pointer register are not altered.
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Example: XTHL

Push register pair onto stack

PUSH Reg. pair The contents of the register pair designated in the operand are copied onto the
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stack in the following sequence. The stack pointer register is decremented and the contents of the
high order register (B, D, H, A) are copied into that location. The stack pointer register is
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decremented again and the contents of the low-order register (C, E, L, flags) are copied to that
location.
Example: PUSH B or PUSH A

Pop off stack to register pair

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POP Reg. pair The contents of the memory location pointed out by the stack pointer register are
copied to the low-order register (C, E, L, status flags) of the operand. The stack pointer is
incremented by 1 and the contents of that memory location are copied to the high-order register (B,
D, H, A) of the operand. The stack pointer register is again incremented by 1.
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Example: POP H or POP A

Output data from accumulator to a port with 8-bit address

OUT 8-bit port address The contents of the accumulator are copied into the I/O port specified by
the operand. Example: OUT F8H Input data to accumulator from a port with 8-bit address
IN 8-bit port address The contents of the input port designated in the operand are read and loaded
into the accumulator.

Example: IN 8CH

1.5.2 ARITHMETIC INSTRUCTIONS

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Add register or memory to accumulator
ADD R The contents of the operand (register or memory) are M added to the contents of the
accumulator and the result is stored in the accumulator. If the operand is a memory location, its
location is specified by the contents of the HL registers. All flags are modified to reflect the result

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of the addition.

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Example: ADD B or ADD M

Add register to accumulator with carry

ADC R The contents of the operand (register or memory) and M the Carry flag are added to the

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contents of the accumulator and the result is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL registers. All flags are modified to
reflect the result of the addition.

Example: ADC B or ADC M

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Add immediate to accumulator
ADI 8-bit data The 8-bit data (operand) is added to the contents of the accumulator and the result is
stored in the accumulator. All flags are modified to reflect the result of the addition.
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Example: ADI 45H

Add immediate to accumulator with carry

ACI 8-bit data The 8-bit data (operand) and the Carry flag are added to the contents of the
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accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of
the addition.

Example: ACI 45H

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Add register pair to H and L registers

DAD Reg. pair The 16-bit contents of the specified register pair are added to the contents of the HL
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register and the sum is stored in the HL register. The contents of the source register pair are not
altered. If the result is larger than 16 bits, the CY flag is set. No other flags are affected.

Example: DAD H
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Subtract register or memory from accumulator

SUB R The contents of the operand (register or memory ) are M subtracted from the contents of the
accumulator, and the result is stored in the accumulator. If the operand is a memory location, its
location is specified by the contents of the HL registers. All flags are modified to reflect the result
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of the subtraction.

Example: SUB B or SUB M

Subtract source and borrow from accumulator

SBB R The contents of the operand (register or memory ) and M the Borrow flag are subtracted
from the contents of the accumulator and the result is placed in the accumulator. If the operand is a
memory location, its location is specified by the contents of the HL registers. All flags are modified
to reflect the result of the subtraction.

Example: SBB B or SBB M

Subtract immediate from accumulator

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SUI 8-bit data The 8-bit data (operand) is subtracted from the contents of the accumulator and the
result is stored in the accumulator. All flags are modified to reflect the result of the
subtraction.

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Example: SUI 45H

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Subtract immediate from accumulator with borrow
SBI 8-bit data The 8-bit data (operand) and the Borrow flag are subtracted from the contents of the
accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of
the subtraction.

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Example: SBI 45H

Increment register or memory by 1

INR R The contents of the designated register or memory) are M incremented by 1 and the result is

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stored in the same place. If the operand is a memory location, its location is specified by the
contents of the HL registers.

Example: INR B or INR M no

Increment register pair by 1
INX R The contents of the designated register pair are incremented by 1 and the result is stored in
the same place.
Example: INX H
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Decrement register or memory by 1

DCR R The contents of the designated register or memory are M decremented by 1 and the result is
stored in the same place. If the operand is a memory location, its location is specified by
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the contents of the HL registers.

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Example: DCR B or DCR M

Decrement register pair by 1

DCX R The contents of the designated register pair are decremented by 1 and the result is stored in
the same place.
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Example: DCX H

Decimal adjust accumulator

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DAA none The contents of the accumulator are changed from a binary value to two 4-bit binary
coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to perform the
binary to BCD conversion, and the conversion procedure is described below. S, Z, AC, P, CY flags
are altered to reflect the results of the operation. If the value of the low-order 4-bits in the
accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits. If
the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the
instruction adds 6 to the high-order four bits.
Example: DAA

1.5.3 BRANCHING INSTRUCTIONS

Jump unconditionally
JMP 16-bit address The program sequence is transferred to the memory location
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specified by the 16-bit address given in the operand.

Example: JMP 2034H or JMP XYZ

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Jump conditionally
Operand: 16-bit address

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The program sequence is transferred to the memory location specified by the 16-bit address given
in the operand based on the specified flag of the PSW as described below.

Example: JZ 2034H or JZ XYZ

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Opcode Description Flag Status
JC Jump on Carry CY = 1
JNC Jump on no Carry CY = 0
JP Jump on positive S = 0

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JM Jump on minus S = 1
JZ Jump on zero Z = 1
JNZ Jump on no zero Z = 0
JPE Jump on parity even P = 1 no
JPO Jump on parity odd P = 0

Unconditional subroutine call

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CALL 16-bit address The program sequence is transferred to the memory location specified by the
16-bit address given in the operand. Before the transfer, the address of the next instruction after
CALL (the contents of the program counter) is pushed onto the stack.
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Example: CALL 2034H or CALL XYZ

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Call conditionally
Operand: 16-bit address
The program sequence is transferred to the memory location specified by the 16-bit address given
in the operand based on the specified flag of the PSW as described below. Before the
transfer, the address of the next instruction after the call (the contents of the program counter) is
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pushed onto the stack.

Example: CZ 2034H or CZ XYZ

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Opcode Description Flag Status

CC Call on Carry CY = 1
CNC Call on no Carry CY = 0
CP Call on positive S = 0
CM Call on minus S = 1
CZ Call on zero Z = 1
CNZ Call on no zero Z = 0
CPE Call on parity even P = 1
CPO Call on parity odd P = 0

field flag of the PSW as described below. The two bytes from the top of the stack arecopied into
the program counter, and program execution begins at the new address.

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Example: RZ

Opcode Description Flag Status

RC Return on Carry CY = 1

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RNC Return on no Carry CY = 0
RP Return on positive S = 0

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RM Return on minus S = 1
RZ Return on zero Z = 1
RNZ Return on no zero Z = 0
RPE Return on parity even P = 1

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RPO Return on parity odd P = 0

Load program counter with HL contents

PCHL none The contents of registers H and L are copied into the program counter. The contents of
H are placed as the high-order byte and the contents of L as the low-order byte.

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Example: PCHL

Restart no
RST 0-7 The RST instruction is equivalent to a 1-byte call instruction to one of eight memory
locations depending upon the number. The instructions are generally used in conjunction with
interrupts and inserted using external hardware. However these can be used as software
instructions in a program to transfer program execution to one of the eight locations. The
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addresses are:

Instruction Restart Address

RST 0 0000H
RST 1 0008H
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RST 2 0010H
RST 3 0018H
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RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
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The 8085 has four additional interrupts and these interrupts generate RST instructions internally
and thus do not require any external hardware. These instructions and their Restart
addresses are:
Interrupt Restart Address
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TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

1.5.4 LOGICAL INSTRUCTIONS

Compare register or memory with accumulator CMP R The contents of the operand (register or
memory) are M compared with the contents of the accumulator. Both contents are preserved . The
result of the comparison is shown by setting the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
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Example: CMP B or CMP M

Compare immediate with accumulator

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CPI 8-bit data The second byte (8-bit data) is compared with the contents of the accumulator. The
values being compared remain unchanged. The result of the comparison is shown by setting

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the flags of the PSW as follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset

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Example: CPI 89H

Logical AND register or memory with accumulator ANA R The contents of the accumulator are
logically ANDed with M the contents of the operand (register or memory), and the result is placed

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in the accumulator. If the operand is a memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set.

Example: ANA B or ANA M no

Logical AND immediate with accumulator ANI 8-bit data The contents of the accumulator are
logically ANDed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P
are modified to reflect the result of the operation. CY is reset. AC is set.
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Example: ANI 86H

Exclusive OR register or memory with accumulator XRA R The contents of the accumulator are
Exclusive ORed with M the contents of the operand (register or memory), and the result is placed in
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the accumulator. If the operand is a memory location, its address is specified by the contents of HL
registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
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Example: XRA B or XRA M

Exclusive OR immediate with accumulator XRI 8-bit data The contents of the accumulator are
Exclusive ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are
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modified to reflect the result of the operation. CY and AC are reset.

Example: XRI 86H

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Logical OR register or memory with accumulator ORA R The contents of the accumulator are
logically ORed with M the contents of the operand (register or memory), and the result is placed in
the accumulator. If the operand is a memory location, its address is specified by the contents of HL
registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset.

Example: ORA B or ORA M

Logical OR immediate with accumulator

ORI 8-bit data The contents of the accumulator are logically ORed with the 8-bit data (operand)
and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.

Example: ORI 86H

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Rotate accumulator left
RLC none Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the
position of D0 as well as in the Carry flag. CY is modified according to bit D7. S, Z, P,

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AC are not affected.

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Example: RLC

Rotate accumulator right

RRC none Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in

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the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P,
AC are not affected.

Example: RRC

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Rotate accumulator left through carry
RAL none Each binary bit of the accumulator is rotated left by one position through the Carry flag.
Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant
position D0. CY is modified according to bit D7. S, Z, P, AC are not affected.
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Example: RAL

Rotate accumulator right through carry

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RAR none Each binary bit of the accumulator is rotated right by one position through the Carry
flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant
position D7. CY is modified according to bit D0. S, Z, P, AC are not affected.

Example: RAR
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Complement accumulator
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CMA none The contents of the accumulator are complemented. No flags are affected.
Example: CMA Complement carry CMC none The Carry flag is complemented. No other flags are
affected.
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Example: CMC

Set Carry
STC none The Carry flag is set to 1. No other flags are affected.
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Example: STC

1.5.5 CONTROL INSTRUCTIONS

No operation
NOP none No operation is performed. The instruction is fetched and decoded. However no
operation is executed.
Example: NOP

Halt and enter wait state

HLT none The CPU finishes executing the current instruction and halts any further execution. An
interrupt or reset is necessary to exit from the halt state.
Example: HLT
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Disable interrupts
DI none The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled.
No flags are affected.

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Example: DI

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Enable interrupts
EI none The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected.
After a system reset or the acknowledgement of an interrupt, the interrupt enable flipflop
is reset, thus disabling the interrupts. This instruction is necessary to reenable the interrupts (except

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TRAP).
Example: EI

1.6 programming in 8085

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8 Bit Addition:

LXI H 4000H : HL points 4000H

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MOV A, M : Get first operand

INX H : HL points 4001H

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ADD M : Add second operand

INX H : HL points 4002H

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MOV M, A : Store result at 4002H

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HLT : Terminate program execution

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Flowchart

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8 Bit Subtraction: no
Source program:

LXI H, 4000H : HL points 4000H

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MOV A, M : Get first operand

INX H : HL points 4001H

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SUB M : Subtract second operand

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INX H : HL points 4002H

MOV M, A : Store result at 4002H.

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HLT : Terminate program execution

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Flowchart

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8Bit Multiplication
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Source program : Flowchart for program

LDA 2200H
MOV E, A
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MVI D, 00 : Get the first number in DE

register pair
LDA 2201H
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MOV C, A : Initialize counter

LX I H, 0000 H : Result = 0
BACK: DAD D : Result = result + first
number
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DCR C : Decrement count

JNZ BACK : If count 0 repeat
SHLD 2300H : Store result
HLT : Terminate program execution
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8 BIT DIVISION

MVI E, 00 : Quotient = 0
LHLD 2200H : Get dividend
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LDA 2300 : Get divisor
MOV B, A : Store divisor
MVI C, 08 : Count = 8
NEXT: DAD H : Dividend = Dividend x 2

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MOV A, E
RLC

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MOV E, A : Quotient = Quotient x 2
MOV A, H
SUB B : Is most significant byte of Dividend > divisor
JC SKIP : No, go to Next step

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MOV H, A : Yes, subtract divisor
INR E : and Quotient = Quotient + 1
SKIP:DCR C : Count = Count - 1
JNZ NEXT : Is count =0 repeat
MOV A, E

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STA 2401H : Store Quotient
Mov A, H
STA 2410H : Store remainder
HLT : End of program. no
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Question Bank
Unit I

PART – A (2 MARKS)

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1. How AD0 – AD7 are multiplexed?

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2. Why the ready signals of 8085 microprocessor is sampled by the processor?
3. List out the similarities between CALL – RET and PUSH – POP instruction.
4. How the address and data lines are de multiplexed in 8085?
5. List out the function of SIM instructions.

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6. What is buffer?
7. Write the function of HOLD pin in Intel 8085 processor.
8. What is the need of ALE signals in 8085 processor?
9. What is the necessity of S0, S1 pins in 8085?
10. List the allowed register pairs of 8085.

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11. Mention the purpose of SID and SOD lines.
12. What is Microprocessor? Give the power supply & clock frequency of 8085.
13. List few applications of Microprocessor – based system.
14. What are the functions of an accumulator?
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15. Mention the purpose of SID and SOD lines.
16. What is Opcode?
17. List the four instructions which control the interrupt structure of the 8085
18. What is meant by polling?
19. What is meant by interrupt?
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20. Define priority interrupts of 8085.

PART – B (16 MARKS)

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1 a) Explain the Logical and Arithmetic instructions available in 8085. (10)

b) Explain the functions of Flag register in 8085 processor. (06)
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2 a) Differences between I/O mapped I/O and Memory mapped I/O. (06)
b) Write an assembly language program to convert 8 – bit binary to ASCII Code (10)
3 a) Draw the block diagram of 8085 microprocessor and explain. (10)
b) Write an assembly language program to add two 2 – digit BCD numbers. (06)
4 a) Explain the instruction set of 8085 microprocessor in detail with one example
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for each group. (10)

b) Write a note on status flag. (06)
5 a) Explain the pin diagram of 8085 microprocessor and explain the functional
usage of each pin in detail. (16)
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6 a) Draw the timing diagram of MVI A08H. (08)

b) Write an assembly language program to convert ASCII code to 8-bit binary. (08)
7 a) Explain the timing diagram when 8085 fetches and executes instruction.
OUT FFH which is stored in memory staring from the address 8000H. (12)
b) List out the Maskable and non-maskable interrupts available in 8085
microprocessor. (04)
8 a) How do the instructions of 8085 is classified based on their functions and
world length? Give example. (10)
b) Write an ASSEMBLY LANGUAGE PROGRAM to add two 8-bit numbers. (06)
9 a) Write briefly about IN and OUT instructions with an example program and
draw the timing diagram for both instructions. (08)
b) Explain briefly about the different types of interrupts in 8085. (08)

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UNIT II 8086 SOFTWARE ASPECTS

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Architecture of 8086

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Unlike microcontrollers, microprocessors do not have inbuilt memory. Mostly Princeton
architecture is used for microprocessors where data and program memory are combined in a single
memory interface. Since a microprocessor does not have any inbuilt peripheral, the circuit is purely
digital and the clock speed can be anywhere from a few MHZ to a few hundred MHZ or even GHZ.

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This increased clock speed facilitates intensive computation that a microprocessor is supposed to
do.
We will discuss the basic architecture of Intel 8086 before discussing more advanced
microprocessor architectures.

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Internal architecture of Intel 8086:

Intel 8086 is a 16 bit integer processor. It has 16-bit data bus and 20-bit address bus. The lower 16-
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bit address lines and 16-bit data lines are multiplexed (AD0-AD15). Since 20-bit address lines are
available, 8086 can access up to 2 20 or 1 Giga byte of physical memory.
The basic architecture of 8086 is shown below.
The internal architecture of Intel 8086 is divided into two units, viz., Bus Interface Unit (BIU) and
Execution Unit (EU).
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Bus Interface Unit (BIU )

The Bus Interface Unit (BIU) generates the 20-bit physical memory address and provides the
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interface with external memory (ROM/RAM). As mentioned earlier, 8086 has a single memory
interface. To speed up the execution, 6-bytes of instruction are fetched in advance and kept in a 6-
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byte Instruction Queue while other instructions are being executed in the Execution Unit (EU).
Hence after the execution of an instruction, the next instruction is directly fetched from the
instruction queue without having to wait for the external memory to send the instruction. This is
called pipe-lining and is helpful for speeding up the overall execution process.
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8086's BIU produces the 20-bit physical memory address by combining a 16-bit segment address
with a 16-bit offset address. There are four 16-bit segment registers, viz., the code segment (CS),
the stack segment (SS), the extra segment (ES), and the data segment (DS). These segment registers
hold the corresponding 16-bit segment addresses. A segment address is the upper 16-bits of the
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starting address of that segment. The lower 4-bits of the starting address of a segment is always
zero. The offset address is held by another 16-bit register. The physical 20-bit address is calculated
by shifting the segment address 4-bit left and then adding that to the offset address.
For Example:

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Code segment Register CS holds the segment address which is 4569 H

Instruction pointer IP holds the offset address which is 10A0 H
The physical 20-bit address is calculated as follows
Segment address : 45690 H
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Offset address
:+ 10A0 H
Physical address : 46730 H
Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four
different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of
processor memory these 4 segments are located the processor uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack.
By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer
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(BP) registers is located in the stack segment. SS register can be changed directly using POP
instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By
default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and

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index register (SI, DI) is located in the data segment. DS register can be changed directly using
POP and LDS instructions.

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Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program
data. By default, the processor assumes that the DI register references the ES segment in string
manipulation instructions. ES register can be changed directly using POP and LES instructions.
It is possible to change default segments used by general and index registers by prefixing

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instructions with a CS, SS, DS or ES prefix.

Execution Unit:

All general registers of the 8086 microprocessor can be used for arithmetic and logic operations.

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The general registers are:

Accumulator register consists of 2 8-bit registers AL and AH, which can be combined together and
used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH
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contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined together and used as
a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the
high-order byte. BX register usually contains a data pointer used for based, based indexed or
register indirect addressing.
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Count register consists of 2 8-bit registers CL and CH, which can be combined together and used
as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and
CH contains the high-order byte. Count register can be used as a counter in string manipulation and
shift/rotate instructions.
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Data register consists of 2 8-bit registers DL and DH, which can be combined together and used as
a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH
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contains the high-order byte. Data register can be used as a port number in I/O operations. In
integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial
or resulting number.
The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack.
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Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used
for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation instructions.
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Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data address in string manipulation instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flags is a 16-bit register containing 9 1-bit flags:

Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement
index registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.
Sign Flag (SF) - set if the most significant bit of the result is set.
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Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL
register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result

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is even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit

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during last result calculation.

2.2 pin details

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The following pin function descriptions are for 8086 systems in either minimum or maximum
mode. The ``Local
Bus'' in these descriptions is the direct multiplexed bus interface connection to the 8086 (without
regard to additional bus buffers).

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AD15±AD0 2±16, 39 -ADDRESS DATA BUS: These lines constitute the time multiplexed
memory/IO address (T1), and data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower
byte of the data bus, pins D7±D0. It is LOW during T1 when a byte is to be transferred on the lower
portion of the bus in memory or I/O operations. Eight-bit oriented devices tied to the lower half

and float to 3-state

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would normally use A0 to condition chip select functions. (See BHE.) These lines are active HIGH

OFF during interrupt acknowledge and local bus ``hold acknowledge''

A19/S6,, A18/S5 , A17/S4, A16/S3 35±38 - ADDRESS/STATUS: During T1 these are the four
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most significant, address lines for memory operations. During I/O operations these, lines are LOW.
During memory and I/O operations, status information is available on these lines during T2, T3,
TW, T4. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK
cycle. A17/S4 and A16/S3 are encoded as shown. This information indicates which relocation
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register is presently being used for data accessing. These lines float to 3-state OFF during local bus
``hold acknowledge.''
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BHE/S7 34 - BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE)
should be used to enable data onto the most significant half of the data bus, pins D15±D8. Eight-bit
oriented devices tied to the upper half of the bus would normally use BHE to condition chip select
functions. BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is
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to be transferred on the high portion of the bus. The S7 status information is available during T2,
T3, and T4. The signal is active LOW, and floats to 3-state OFF in `hold''. It is LOW during T1 for
the first interrupt acknowledge cycle.
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RD 32 READ: Read strobe indicates that the processor is performing a memory or I/O read cycle,
depending on the state of the S2 pin. This signal is used to read devices which reside on the 8086
local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaranteed to remain
HIGH in T2 until the 8086 local bus has floated. This signal floats to 3-state OFF in ``hold
acknowledge''.

READY 22 - READY: is the acknowledgement from the addressed memory or I/O device that it
will complete the data transfer. The READY signal from memory/IO is synchronized by the 8284A
Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not
synchronized. Correct operation is not guaranteed if the setup and hold times are not met.

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INTR 18 - INTERRUPT REQUEST: is a level triggered input which is sampled during the last
clock cycle of each instruction to determine if the processor should enter into an interrupt
acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in
system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is

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internally synchronized. This signal is active HIGH.

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TEST 23 TEST: input is examined by the ``Wait'' instruction. If the TEST input is LOW
execution continues, otherwise the rocessor waits in an ``Idle'' state. This input is synchronized
internally during each clock cycle on the leading edge of CLK.

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NMI 17 NON-MASKABLE INTERRUPT an edge triggered input which causes a type 2
interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system
memory. NMI is not maskable internally by software. A transition from LOW to HIGH initiates the
interrupt at the end of the current instruction. This input is internally synchronized.,

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RESET 21 - RESET: causes the processor to immediately terminate its present activity. The signal
must be active HIGH for at least four clock cycles. It restarts execution, as described in the
Instruction Set description, when RESET returns LOW. RESET is internally synchronized.

CLK 19
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CLOCK: provides the basic timing for the processor and bus controller. It is
asymmetric with a 33% duty cycle to provide optimized internal timing.

VCC 40 VCC: a5V power supply pin. ,GND 1, 20 GROUND

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MN/MX 33 I MINIMUM/MAXIMUM: indicates what mode the processor is to
operate in. The two modes are discussed in the following sections.

S2, S1, S0 26±28 STATUS: active during T4, T1, and T2 and is returned to the passive state (1, 1,
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1) during T3 or during TW when READY is HIGH. This status is used by the 8288 Bus Controller
to generate all memory and I/O access control signals. Any change by S2, S1, or S0 during T4 is
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used to indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used
to indicate the end of a bus cycle

2.3 Instruction Set

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In general, the features of the modern x86 instruction set are:

A compact encoding
o Variable length and alignment independent (encoded as little endian, as is all data in
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the x86 architecture)

o Mainly one-address and two-address instructions, that is to say, the first operand is
also the destination.
o Memory operands as both source and destination are supported (frequently used to
read/write stack elements addressed using small immediate offsets).
o Both general and implicit register usage; although all seven (counting ebp) general
registers in 32-bit mode, and all fifteen (counting rbp) general registers in 64-bit
mode, can be freely used as accumulators or for addressing, most of them are also
implicitly used by certain (more or less) special instructions; affected registers must
therefore be temporarily preserved (normally stacked), if active during such
instruction sequences.
Produces conditional flags implicitly through most integer ALU instructions.

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Supports various addressing modes including immediate, offset, and scaled index but not
PC-relative, except jumps (introduced as an improvement in the x86-64 architecture).
Includes floating point to a stack of registers.
Contains special support for atomic instructions (xchg, cmpxchg/cmpxchg8b, xadd, and

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integer instructions which combine with the lock prefix)
SIMD instructions (instructions which perform parallel simultaneous single instructions

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on many operands encoded in adjacent cells of wider registers).

TYPES OF INSTRUCTION
Instructions vary from one CPU to another

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General groupings possible...
Arithmetic/Logic
* Add, subtract, AND, OR, shifts
* Performed by ALU Data Movement
* Load, Store (to/from registers/memory) Transfer of Control

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* Jump, Branch, procedure call Test/Compare
* Set condition flags Input/Output
* In, Out
* Only on some CPU's Others no
* Halt, NOP

Stack instructions
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The x86 architecture has hardware support for an execution stack mechanism. Instructions such as
push, pop, call and ret are used with the properly set up stack to pass parameters, to allocate space
for local data, and to save and restore call-return points. The ret size instruction is very useful for
implementing space efficient (and fast) calling conventions where the callee is responsible for
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reclaiming stack space occupied by parameters.

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When setting up a stack frame to hold local data of a recursive procedure there are several choices;
the high level enter instruction takes a procedure-nesting-depth argument as well as a local size
argument, and may be faster than more explicit manipulation of the registers (such as push bp, mov
bp, sp, sub sp, size) but it is generally not used. Whether it is faster depends on the particular x86
implementation (i.e. processor) as well as the calling convention and code intended to run on
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multiple processors will usually run faster on most targets without it.

The full range of addressing modes (including immediate and base+offset) even for instructions
such as push and pop, makes direct usage of the stack for integer, floating point and address data
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simple, as well as keeping the ABI specifications and mechanisms relatively simple compared to
some RISC architectures (require more explicit call stack details).

Integer ALU instructions

x86 assembly has the standard mathematical operations, add, sub, mul, with idiv; the logical
operators and, or, xor, neg; bitshift arithmetic and logical, sal/sar, shl/shr; rotate with and without
carry, rcl/rcr, rol/ror, a complement of BCD arithmetic instructions, aaa, aad, daa and others.

Floating point instructions

x86 assembly language includes instructions for a stack-based floating point unit. They include
addition, subtraction, negation, multiplication, division, remainder, square roots, integer truncation,
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fraction truncation, and scale by power of two. The operations also include conversion instructions
which can load or store a value from memory in any of the following formats: Binary coded
decimal, 32-bit integer, 64-bit integer, 32-bit floating point, 64-bit floating point or 80-bit floating
point (upon loading, the value is converted to the currently used floating point mode). x86 also

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includes a number of transcendental functions including sine, cosine, tangent, arctangent,
exponentiation with the base 2 and logarithms to bases 2, 10, or e.

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The stack register to stack register format of the instructions is usually fop st, st(*) or fop st(*), st,
where st is equivalent to st(0), and st(*) is one of the 8 stack registers (st(0), st(1), ..., st(7)). Like
the integers, the first operand is both the first source operand and the destination operand. fsubr and

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fdivr should be singled out as first swapping the source operands before performing the subtraction
or division. The addition, subtraction, multiplication, division, store and comparison instructions
include instruction modes that will pop the top of the stack after their operation is complete. So for
example faddp st(1), st performs the calculation st(1) = st(1) + st(0), then removes st(0) from the
top of stack, thus making what was the result in st(1) the top of the stack in st(0).

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SIMD instructions

Modern x86 CPUs contain SIMD instructions, which largely perform the same operation in parallel
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on many values encoded in a wide SIMD register. Various instruction technologies support
different operations on different register sets, but taken as complete whole (from MMX to SSE4.2)
they include general computations on integer or floating point arithmetic (addition, subtraction,
multiplication, shift, minimization, maximization, comparison, division or square root). So for
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example, paddw mm0, mm1 performs 4 parallel 16-bit (indicated by the w) integer adds (indicated
by the padd) of mm0 values to mm1 and stores the result in mm0. SSE also includes a floating
point mode in which only the very first value of the registers is actually modified (expanded in
SSE2). Some other unusual instructions have been added including a sum of absolute differences
(used for motion estimation in video compression, such as is done in MPEG) and a 16-bit multiply
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accumulation instruction (useful for software-based alpha-blending and digital filtering). SSE (since
SSE3) and 3DNow! extensions include addition and subtraction instructions for treating paired
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floating point values like complex numbers.

These instruction sets also include numerous fixed sub-word instructions for shuffling, inserting
and extracting the values around within the registers. In addition there are instructions for moving
data between the integer registers and XMM (used in SSE)/FPU (used in MMX) registers.
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Data manipulation instructions

The x86 processor also includes complex addressing modes for addressing memory with an
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immediate offset, a register, a register with an offset, a scaled register with or without an offset, and
a register with an optional offset and another scaled register. So for example, one can encode mov
eax, [Table + ebx + esi*4] as a single instruction which loads 32 bits of data from the address
computed as (Table + ebx + esi * 4) offset from the ds selector, and stores it to the eax register. In
general x86 processors can load and use memory matched to the size of any register it is operating
on. (The SIMD instructions also include half-load instructions.)

The x86 instruction set includes string load, store and move instructions (lods, stos, and movs)
which perform each operation to a specified size (b for 8-bit byte, w for 16-bit word, d for 32-bit
double word) then increments/decrements (depending on DF, direction flag) the implicit address
register (si for lods, di for stos, and both for movs). For the load and store, the implicit target/source
register is in the al, ax or eax register (depending on size). The implicit segment used is ds for lods,
es for stos and both for movs.
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The stack is implemented with an implicitly decrementing (push) and incrementing (pop) stack
pointer. In 16-bit mode, this implicit stack pointer is addressed as SS:[SP], in 32-bit mode it is
SS:[ESP], and in 64-bit mode it is [RSP]. The stack pointer actually points to the last value that was
stored, under the assumption that its size will match the operating mode of the processor (i.e., 16,

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32, or 64 bits) to match the default width of the push/pop/call/ret instructions. Also included are the
instructions enter and leave which reserve and remove data from the top of the stack while setting

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up a stack frame pointer in bp/ebp/rbp. However, direct setting, or addition and subtraction to the
sp/esp/rsp register is also supported, so the enter/leave instructions are generally unnecessary.

This code in the beginning of a function:

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pushl %ebp /* save calling function's stack frame (%ebp) */
movl %esp,%ebp /* make a new stack frame on top of our caller's stack */
subl $4,%esp /* allocate 4 bytes of stack space for this function's local variables */

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...is functionally equivalent to just:

enter $4,$0
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Other instructions for manipulating the stack include pushf/popf for storing and retrieving the
(E)FLAGS register. The pusha/popa instructions will store and retrieve the entire integer register
state to and from the stack.
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Values for a SIMD load or store are assumed to be packed in adjacent positions for the SIMD
register and will align them in sequential little-endian order. Some SSE load and store instructions
require 16-byte alignment to function properly. The SIMD instruction sets also include "prefetch"
instructions which perform the load but do not target any register, used for cache loading. The SSE
instruction sets also include non-temporal store instructions which will perform stores straight to
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memory without performing a cache allocate if the destination is not already cached (otherwise it
will behave like a regular store.)
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Most generic integer and floating point (but no SIMD) instructions can use one parameter as a
complex address as the second source parameter. Integer instructions can also accept one memory
parameter as a destination operand.
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8086 instruction set (79 basic instructions)

AAA AAD AAM AAS

ADC ADD AND CALL
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CBW CLC CLD CLI

CMC CMP CMPS CMPXCHG
CWD DAA DAS DEC
DIV ESC HLT IDIV
IMUL IN INC INT
INTO IRET/IRETD Jxx JCXZ/JECXZ
JMP LAHF LDS LEA
LES LOCK LODS LOOP
MOV MOVS LOOPE/LOOPZ LOOPNZ/LOOPNE
MUL NEG NOP NOT
OR OUT POP POPF/POPFD
PUSH RCL RCR PUSHF/PUSHFD

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REP REPE/REPZ RET/RETF REPNE/REPNZ
ROL ROR SAHF SAL/SHL
SAR SBB SCAS SHL
SHR STC STD STI

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STOS SUB TEST WAIT/FWAIT
XCHG XLAT/XLATB XOR

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2.4 Addressing modes

Indexed :- 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or

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DI), the resulting value is a pointer to location where data resides.
• Based Indexed :- the contents of a base register (BX or BP) is added to the contents of an index
register (SI or DI), the resulting value is a pointer to location where data resides.
• Based Indexed with displacement :- 8-bit or 16-bit instruction operand is added to the contents
of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to

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location where data resides.
• Implied - the data value/data address is implicitly associated with the instruction.
• Register - references the data in a register or in a register pair.
• Immediate - the data is provided in the instruction.
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• Direct - the instruction operand specifies the memory address where data is located.
• Register indirect - instruction specifies a register containing an address, where data is located.
This addressing mode works with SI, DI, BX and BP registers.
• Based :- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP),
the resulting value is a pointer to location where data resides.
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DATA ADDRESSING MODES

• MOV instruction is a common and flexible instruction. – provides a basis for explanation of data
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addressing modes
• Figure 1 illustrates the MOV instruction and defines the direction of data flow.
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• Source is to the right and destination the left, next to the opcode MOV. – an opcode, or operation
code, tells the microprocessor which operation to perform
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Figure 3–2 shows all possible variations of the data-addressing modes using MOV.
• These data-addressing modes are found with all versions of the Intel microprocessor.
– except for the scaled-index-addressing mode, found only in 80386 through Core2
• RIP relative addressing mode is not illustrated. only available on the Pentium 4 and Core2
in the 64-bit mode

Register Addressing
• The most common form of data addressing. – once register names learned, easiest to apply.
• The microprocessor contains these 8-bit register names used with register addressing: AH, AL,
BH, BL, CH, CL, DH, and DL.
• 16-bit register names: AX, BX, CX, DX, SP, BP, SI, and DI.
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In 80386 & above, extended 32-bit register names are: EAX, EBX, ECX, EDX, ESP, EBP, EDI,
and ESI.
• 64-bit mode register names are: RAX, RBX, RCX, RDX, RSP, RBP, RDI, RSI, and R8 through
R15.

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• Important for instructions to use registers that are the same size. – never mix an 8-bit \with a 16-
bit register, an 8- or a 16-bit register with a 32-bit register – this is not allowed by the

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microprocessor and results in an error when assembled

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Figure 3 shows the operation of the MOV BX, CX instruction.

• The source register‟s contents do not change. – the destination register‟s contents do change
• The contents of the destination register or destination memory location change for all instructions
except the CMP and TEST instructions.
• The MOV BX, CX instruction does not affect the leftmost 16 bits of register EBX.

Immediate Addressing
• Term immediate implies that data immediately follow the hexadecimal opcode in the memory.
– immediate data are constant data – data transferred from a register or memory location are
variable data
• Immediate addressing operates upon a byte or word of data.
• Figure 3–4 shows the operation of a MOV EAX,13456H instruction.
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As with the MOV instruction illustrated in Figure 3, the source data overwrites the destination

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data. In symbolic assembly language, the symbol # precedes immediate data in some
assemblers. – MOV AX,#3456H instruction is an example
• Most assemblers do not use the # symbol, but represent immediate data as in the MOV
AX,3456H instruction. – an older assembler used with some Hewlett- Packard logic development
does, as may others – in this text, the # is not used for immediate data

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The symbolic assembler portrays immediate data in many ways.
• The letter H appends hexadecimal data.
• If hexadecimal data begin with a letter, the assembler requires the data start with a 0. – to
represent a hexadecimal F2, 0F2H is used in assembly language
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• Decimal data are represented as is and require no special codes or adjustments. – an example is
the 100 decimal in the MOV AL,100 instruction An ASCII-coded character or characters may
be depicted in the immediate form if the ASCII data are enclosed in apostrophes. – be careful to use
the apostrophe („) for ASCII data and not the single quotation mark („)
• Binary data are represented if the binary number is followed by the letter B. – in some assemblers,
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the letter Y Each statement in an assembly language program consists of four parts or fields.
• The leftmost field is called the label. – used to store a symbolic name for the memory location it
represents
• All labels must begin with a letter or one of the following special characters: @, $, -, or ?.
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– a label may any length from 1 to 35 characters

• The label appears in a program to identify the name of a memory location for storing data and
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for other purposes. The next field to the right is the opcode field. – designed to hold the
instruction, or opcode – the MOV part of the move data instruction is an example of an opcode
• Right of the opcode field is the operand field. – contains information used by the opcode
– the MOV AL,BL instruction has the opcode MOV and operands AL and BL
• The comment field, the final field, contains a comment about the instruction(s). – comments
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always begin with a semicolon (;)

Direct Data Addressing

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• Applied to many instructions in a typical program.

• Two basic forms of direct data addressing: – direct addressing, which applies to a MOV
between a memory location and AL, AX, or EAX – displacement addressing, which applies to
almost any instruction in the instruction set
• Address is formed by adding the displacement to the default data segment address or an
alternate segment address.

Direct Addressing

• Direct addressing with a MOV instruction transfers data between a memory location,
located within the data segment, and the AL (8-bit), AX (16-bit), or EAX (32-bit) register.
– usually a 3-byte long instruction
• MOV AL,DATA loads AL from the data segment memory location DATA (1234H).
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– DATA is a symbolic memory location, while 1234H is the actual hexadecimal location

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This instruction transfers a copy contents of memory location 11234H into AL. – the effective
address is formed by adding 1234H (the offset address) and 10000H (the data segment address of
1000H times 10H) in a system operating in the real mode

Displacement Addressing
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• Almost identical to direct addressing, except the instruction is 4 bytes wide instead of 3.
• In 80386 through Pentium 4, this instruction can be up to 7 bytes wide if a 32-bit register
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and a 32-bit displacement are specified.
• This type of direct data addressing is much more flexible because most instructions use it.
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Register Indirect Addressing

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• Allows data to be addressed at any memory location through an offset address held in any
of the following registers: BP, BX, DI, and SI.
• In addition, 80386 and above allow register indirect addressing with any extended register
except ESP.
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• In the 64-bit mode, the segment registers serve no purpose in addressing a location in the flat
model.
The data segment is used by default with register indirect addressing or any other mode that uses
BX, DI, or SI to address memory.
• If the BP register addresses memory, the stack segment is used by default. – these settings are
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considered the default for these four index and base registers
• For the 80386 and above, EBP addresses memory in the stack segment by default.
• EAX, EBX, ECX, EDX, EDI, and ESI address memory in the data segment by default.
When using a 32-bit register to address memory in the real mode, contents of the register must
never exceed 0000FFFFH.

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• In the protected mode, any value can be used in a 32-bit register that is used to indirectly

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address memory. – as long as it does not access a location outside the segment, dictated by the
access rights byte
• In the 64-bit mode, segment registers are not used in address calculation; the register contains the
actual linear memory address. In some cases, indirect addressing requires specifying the size of the
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data by the special assembler directive BYTE PTR, WORD PTR, DWORD PTR, or QWORD
PTR. – these directives indicate the size of the memory data addressed by the memory pointer
(PTR)
• The directives are with instructions that address a memory location through a pointer or index
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register with immediate data.
• With SIMD instructions, the octal OWORD PTR, represents a 128-bit-wide number Indirect
addressing often allows a program to refer to tabular data located in memory.
• Figure 3–7 shows the table and the BX register used to sequentially address each location in the
table.
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• To accomplish this task, load the starting location of the table into the BX register with a MOV
immediate instruction.
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• After initializing the starting address of the table, use register indirect addressing to store the 50
samples sequentially
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Base-Plus-Index Addressing

• Similar to indirect addressing because it indirectly addresses memory data.

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• The base register often holds the beginning location of a memory array. – the index register holds
the relative position of an element in the array – whenever BP addresses memory data, both the
stack segment register and BP generate the effective address

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Locating Data with Base-Plus-Index Addressing

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• Figure 3–8 shows how data are addressed by the MOV DX,[BX + DI] instruction when the
microprocessor operates in the real mode.
• The Intel assembler requires this addressing mode appear as [BX][DI] instead of [BX + DI].
• The MOV DX,[BX + DI] instruction is MOV DX,[BX][DI] for a program written for the Intel

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ASM assembler.

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Plus-Index Addressing
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• A major use is to address elements in a memory array.

• To accomplish this, load the BX register (base) with the beginning address of the array
and the DI register (index) with the element number to be accessed.
• Figure 3–9 shows the use of BX and DI to access an element in an array of data.
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2.5 Assembler Directives

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An assembler directive is a message to the assembler that tells the assembler something it
needs to know in order to carry out the assembly process; for example, an assemble directive tess
the assembler where a program is to be located in memory. We are going to use the following
directives in this course:

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<label> EQU <value> Equate

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ORG <value> Origin
<label> DC <value> Define constant
<label> DS <value> Define storage
END <value> End of assembly language program and "starting address" for

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execution

In each case, the term <label> indicates a user-defined label (i.e., symbolic name) that must start in
column 1 of the program, and <value> indicates a value that must be supplied by the programmer
(this may be a number, or a symbolic name that has a value).

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Equate:The EQU assembler directive simply equates a symbolic name to a numeric value.
Consider:

Sunday
Monday
EQU 1
EQU 2
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The assembler substitutes the equated value for the symbolic name; for example, if you write the
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instruction ADD.B #Sunday,D2, the assembler treats it as if it were ADD.B #1,D2.

You could also write

Sunday EQU 1
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Monday EQU Sunday + 1

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In this case, the assembler evaluates "Sunday + 1" as 1 + 1 and assigns the value 2 to the symbolic
name "Monday".

Do not think that the EQU directive creates variables or constant. It doesn't and it has no effect on
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the code generated by the program. This directive simply allows you to make a name equivalent to
its value (i.e., it's a form of short hand).

Origin : The origin directive tells the assembler where to load instructions and data into memory.
The 68000 reserves the first 1024 bytes of memory for exception vectors. Your programs will start
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at location 1024; that is, you should begin your program with ORG 1024 or ORG $400 (remember
that 1024 = 40016).

Define Constant :The define constant assembler directive allows you to put a data value in
memory at the time that the program is first loaded. The DC directive takes the suffix .B, .W, or .L.
You can put several values on one line (each value is separated by a comma). The optional label
field is given the address of the first location in memory allocated to the DC function. Consider the
example:

ORG $2000 Locate data here

Val1 DC.B 20,34 Store 20 and 34 in consecutive bytes
Val2 DC.L 20

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Me DC.B ’Alan Clements’

The effect of this code is to store the value $14 in location $2000, $22 in location $2001,
$00000014 in locations $2002, $2003, $2004, $2005. Remember that a 32-bit longword takes four

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bytes of memory. The ASCII string „Alan Clements‟ is stored in bytes $2006 to $2012.

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If you write MOVE.B Val2,D2, the assembler translates it as MOVE.B $2002,D2. When this
instruction is executed, data register D2 is loaded with the contents of memory location $2002. The
value loaded into D2 might be 20. Might be?? Yes, might be, because another instruction might
modify the contents of Val2. By the way, if you execute MOVE.B Me,D0, data register D0 would

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be loaded with $41 (the ASCII code for „A‟). However, if you execute MOVE.W Me,D0, data
register D0 would be loaded with $416C (the ASCII code for „Al‟).

Define Storage : The define storage directive is used to reserve one or more memory locations.

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This directive is similar to the Pascal type declaration. Consider:

Result DS.B 1 Save a byte for Result

Table DS.W 10 Save 10 words (20 bytes) for Table
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Point DS.L 1 Save 1 longword (4 bytes) for Point

We will put these two fragments of assembly language together and assemble them using the X68K
command (X68K is the Teesside 68K cross-assembler that runs under DOS on a PC). The
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following is part of the listing file produced by the assembler. The second column contains memory
addresses and the third column contains the data loaded into these addresses.

2 ORG $2000 ;Locate data here

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00002000
3 1422 VAL1: DC.B 20,34
00002000
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4 00000014 VAL2: DC.L 20

00002002
5 416C616E2043 ME: DC.B ’Alan
00002006 Clements’
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6C656D656E74
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6 00000001 RESULT: DS.B 1 ;Save a byte for Result
00002013
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7 00000014 TABLE: DS.W 10 ;Save 10 words (20 bytes) for

00002014 Table
8 00000004 POINT: DS.L 1 ;Save 1 longword (4 bytes) for
00002028 Point

A L I G N : The .ALIGN directive advances the current location counter to the next specified
"boundary."

Syntax

.A LIGN [ boundar y]
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Parameters
boundary
An integer value for the byte boundary to which you want to advance the location

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counter. The Assembler advances the location counter to that boundary. Permissible
values must be a power of 2 and can range from one to 4096. The default value is 8

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(double word aligned).

A L L O W : The .ALLOW directive tells the Assembler to temporarily allow PA-RISC features
from a higher version level of the PA-RISC architecture. The .ALLOW directive also tells the

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Assembler to temporarily allow implementation-specific features in the assembly source file.

Syntax

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.A LLOW 1.1

Lines of source code

.A LLOW no
Parameters
Title not available (Parameters )
1.1
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Allows PA-RISC 1.1 features.
2.0
Allows PA-RISC 2.0 features.
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relocatable object file marked as a PA-RISC 1.1 architecture version.

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CALL:

The .CALL directive marks the next branch statement as a procedure call, and permits you to
describe the location of arguments and the function return result.
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Syntax

. C A L L [ a r g u m e n t _ d e s c r i p t i o n [ a r g u m e n t _ d e s c r i p t i o n ] .. . ]
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Parameters
argument_ description
Allows you to communicate to the linker the types of registers used to pass floating point
arguments and receive floating point return results in the succeeding procedure call. Similarly, this
information can be communicated in the .EXPORT directive.
The linker requires this information because the runtime architecture allows floating point
arguments and return values to reside in either general registers or floating point registers,
depending on source language convention. At link time, the linker ensures that both the caller and
called procedure agree on argument location. If not, the linker may insert code to relocate the

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arguments (or return result) before control is transferred to the called procedure or a procedure
return is completed.
You can use up to 5 argument-descriptions in the .CALL directive; one for each of the four

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arguments that may be passed in registers (arg0-arg3), and one for a return value (ret0).

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C O M M : The .COMM directive makes a storage request for a specified number of bytes.

Syntax

label .COMM [ num_bytes ]

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Parameters
label

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Labels the location of the reserved storage.
num_bytes
An integer value for the number of bytes you want to reserve. The Assembler uses a
default value of 4 if the .COMM directive lacks a num_bytes parameter. Permissible
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values range from one to 0x3FFFFFFF.

Discussion
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The .COMM directive declares a block of storage that can be thought of as a common block. You
must label every .COMM directive. The linker associates the label with the subspace in which the
.COMM directive is declared and allocates the necessary storage within that subspace. .COMM
always allocates its space in the $BSS$ subspace of the $PRIVATE$ space. If the label of a
.COMM directive appears in several object modules, the linker uses the maximum size specified in
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any module when it allocates the necessary storage in the current subspace.
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E N D : The .END directive terminates an assembly language program.

Syntax
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.END

Discussion
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This directive is the last statement in an assembly language program. If a source file lacks an .END
directive, the Assembler terminates the program when it encounters the end of the file.

The .END directive terminates an assembly language program.

Syntax

.END

Discussion

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This directive is the last statement in an assembly language program. If a source file lacks an .END
directive, the Assembler terminates the program when it encounters the end of the file.

E N D M : The .ENDM directive marks the end of a macro definition. The macro definition is

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entered into the macro table and the remaining source lines are read in and assembled. An .ENDM
directive must always accompany a .MACRO directive.

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Syntax

.ENDM

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Example

This example defines the macro QUADL; it aligns the data specified in the macro parameters on

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quad word boundaries. The .ENDM directive delimits the end of the definition of QUADL.

QUADL .MACRO WD1,WD2,WD3,WD4

.ALIGN 16
.WORD WD1
.ALIGN 16
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.WORD WD2
.ALIGN 16
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.WORD WD3
.ALIGN 16
.WORD WD4
.ENDM
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2.6 Assembly language program :

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ASSEMBLY LANGUAGE PROGRAMMING: AN INTRODUCTION

Instruction Execution
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Fetch/Decode/Execute cycle is like a program:

Repeat
Fetch instruction from primary memory
Increment Program Counter
Decode
Fetch operands from memory (if required)
Execute instruction
Write results to memory (if required)
Until Halt
How is this "program" written?

eg. ADD Instruction

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1. Fetch operand1, store in register X
2. Fetch operand2, store in register Y
3. Tell ALU to add X and Y
4. Put result in ACC

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MICROCODE (see fig. below)

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Lowest level of software
Flexible: can be updated by designers
Controls the digital logic of the CPU

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Implements the machine code instructions

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no
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Lowest level of software meets highest level of hardware

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1. ALP to add list of 10 given numbers

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title ALP to add list of 10 given numbers

dosseg
.model small
.stack 100
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.code
main proc
mov ax, @data
mov ds, ax
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mov, cx, 0aH

mov dx, 00
mov SI, offset array1
BACK: add dl, SI
adc dh, 00
LOOP back
mov result, dx
mov ax, 4c00h
INT 21h
main endp
.data
array1 db 01, 02, 03, 04, 05, 06, 07, 08, 09, 10

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result db ?
end main

2. SUM THE NUMBERS FROM 1-100

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title SUM THE NUMBERS FROM 1-100

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dosseg
.model small
.stack 100H
.code

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main proc
mov ax, 0
mov cx, 10h ; loop count=10
BACK: add ax, cx ; add two numbers
loop BACK ; repeat until cx=0

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mov ax, 4c00h ; return to DOS
int 21h
main endp
end main no
3. An Example Of Keyboard Intercept

Now we need to write and test a routine for printing a message to the display. For this, we‟ll
ar
use DOS function call 9, which prints a string to the video display.

.Data
mesg db
t

'Ten seconds have passed!',0Dh, 0Ah,'$' ;

; pmesg - Prints the message pointed to by the DX register on the screen.;
5s

pmesg
PROC
mov
ah, 09h
w.

;DOS Print to screen function.

int
21h
;Call DOS.
ret
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;Return after printing.

pmesg
ENDP

;Test our procedure for printing a message.

start: mov
ax, @Data ;We're using the data segment now so we
mov
ds, ax
; need to initialize it!

.Code
end
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mov
call
call
call

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mov
int

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start

dx, offset mesg;Point DX at the message.

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pmesg
;Print the message on the screen.
pmesg
; a few times.
pmesg

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;
ax, 4C00h
;DOS Exit function call, return code 0.
21h no
;Call DOS to exit.

4. Hello world!" program for DOS in MASM style assembly

.MODEL Small
.STACK 100h
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.DATA .MODEL Small
.STACK 100h
.DATA
msg db 'Hello, world!$'
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.CODE
start:
5s

mov ah, 09h ; Display the message

lea dx, msg
int 21h
mov ax,4C00h ; Terminate the executable
int 21h
w.

end start

5. "Hello World!" program for Windows in MASM style assembly

ww

; requires /coff switch on 6.15 and earlier versions

.386
.model small,c
.stack 100h
.data
msg db "Hello World!",0
.code
INCLUDELIB MSVCRT
EXTRN printf:NEAR
EXTRN exit:NEAR
PUBLIC main

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main PROC
push offset msg
call printf
push 0 call

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exit main
ENDP END

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main

6. "Hello world!" program for Linux in NASM style assembly

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; This program runs in 32-bit protected mode
;
section .data ; section for initialized data
str: db 'Hello world!', 0Ah ; message string with new-line char at the end (10 decimal)

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strLen: equ $-str ; calcs length of string (bytes) by subtracting this' address ($
symbol) from the str's start address
section .text ; this is the code section
global _start ; _start is the entry point and needs global scope to be 'seen' by the
no
linker -equivalent to main() in C/C++
_start: ; procedure start
mov eax,4 ; specify the sys_write function code (from OS vector table)
mov ebx,1 ; specify file descriptor stdout -in linux, everything's treated as a file,
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even hardware devices
mov ecx,str ; move start address of string message to ecx register
mov edx,strLen ; move length of message (in bytes)
int 80h ; tell kernel to perform the system call we just set up - in linux services
are requested through the kernel
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mov eax,1 ; specify sys_exit function code (from OS vector table)

mov ebx,0 ; specify return code for OS (0 = everything's fine)
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int 80h ; tell kernel to perform system call

7. print "/bin/sh\n" program in 64 -bit mode Linux

w.

section .text
global _start, write
write:
mov al,1 ;write syscall
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syscall
ret
_start:
mov rax,0x0a68732f6e69622f
push rax
xor rax,rax
mov rsi,rsp
mov rdi,1
mov rdx,8
call write

exit: ; just exit not a function

xor rax,rax
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mov rax,60
syscall

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QUESTION BANK

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PART – A (2 MARKS)

1. What is meant by Software interrupts in 8086?

2. State the modes in which 8086 operates.

s.
3. How the interrupts can be masked/unmasked in 8086?
4. What are the signals involved in memory bank selection of 8086 microprocessor?
5. Write the difference between near procedure and far procedure.
6. What is the function of SI and DI registers in 8086?
7. What is meant by stack?

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8. What are the advantages of using memory segmentation?
9. What is macro?
10. Write the uses of PUSH and POP instruction in 8086.
11. Define ALIGN & ASSUME.
12. Define PTR & GROUP.
13. Define PROC & MNDP.
14. Define SEGMENT & ENDS.
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15. Define SOP.
16. What are procedures?
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17. What is meant by Linking process?
18. Write about the passing parameters using registers with example.
19. What is a recursive procedure?
20. What are Macros?
21. What are the 8086 interrupt types?
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22. What is interrupt service routine?

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PART – B (16 MARKS)

1 a) Write an assembly language program in 8086 to search the largest data in the array
(10)
b) Explain the various status flags in 8086 (06)
w.

2 a) Discuss the various addressing modes of 8086 (10)

b) Explain the following assembler directive in 8086 (06)
(a) ASSEUME
(b) EQU
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(c) DW
3 a) Write short notes on Macro (06)
b) Explain the function of assembler directives (10)
4 a) Explain the register organization of 8086 (10)
b) Explain the pin diagram of 8086 (06)
5. Discuss the instruction set of 8086 in detail (16)

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UNIT III MULTI PROCESSOR CONFIGURATIONS.

3.1 MULTIPROCESSOR SYSTEMS

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Multiprocessor Systems refer to the use of multiple processors that execute instructions
simultaneously and communicate using mailboxes and semaphores

Maximum mode of 8086 is designed to implement 3 basic multiprocessor configurations:

s.
1. coprocessor (8087)
2. closely coupled (8089)
3. loosely coupled (Multibus)

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Coprocessors and closely coupled configurations are similar in that both the CPU and the external
processor share:
- Memory
- I/O system
- Bus & bus control logic
- Clock generator
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3.2 Closely Coupled Configuration:
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CL O C K
t
5s

80 86
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Bus Sy ste m B u s
Co n tro l
Lo g ic
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C o p ro cesso r
or
In d ep e n d e n t M em ory I/O
Po c e sso r

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Example: 8086/8087

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8086/8088
C o p ro c e s s o r (ie : 8 0 8 7 )

Monitor the

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ESC 8086 or 8088
Wake up the
coprocessor

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Deactivate the
Execute no host's !TEST pin
8086
and execute the
instructions
specified operation
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Wake up the Activate the

8086 or 8088 !TEST pin
t

WAIT
5s
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Coprocessor cannot take control of the bus, it does everything through the CPU
- 8089 shares CPU=s clock and bus control logic
- communication with host CPU is by way of shared memory
ww

- host sets up a message (command) in memory

- independent processor interrupts host on completion

NOTE: Closely Coupled processor may take control of the bus independently Two 8086‟s cannot be
closely coupled

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8086/8088 Independent Processor (8089)

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Wait for

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Set up request
message

Fetch the

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message
Wake up independent
processor with OUT

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instruction Perform
requested
task

Execute
no Notify CPU
8086 of
instructions completion
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Wait for ready

t

or interrupt
request
5s
w.
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3.3 Loosely Coupled Configuration:
- has shared system bus, system memory, and system I/O
- each processor has its own clock as well as its own memory (in addition to access to the
system resources, such as the system clock)

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- clocks are of similar frequency, but asynchro-nous towards each other

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- Used for medium to large multiprocessor systems
- Each module is capable of being the bus master
- Any module could be a processor capable of being a bus master, a coprocessor configuration or a
closely coupled configuration.

s.
- No direct connections between the modules. Each share the system bus and communicate through
shared resources.
- Processor in their saeparate modules can simulateneously access their private subsystems through
their local busses, and perorm their local data references and instruction fetches independandtly.

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This results in improved degree of concurrent processing.
- Ecellent for real time applications, as separate modules can be assigned specialized tasks.

ADVANTAGES:
no
- high system throughput can be achieved by having more than one CPU.
- The system can be expanded in modular form. Each bus master module is an independant unit and
normally resides on a separate PC board. One can be added or removed without affecting the
others in the system.
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- A failure in one module normally does not affect the breakdown of the entire system and the faulty
module can be easily detected and replaced
- each bus master has its own local bus to access dedicated memory or IO devices so a greater de-
gree of parallel processing can be achieved.
t

PROBLEMS:
5s

- Bus Arbitration (contention): Make sure that only 1 processor can access the bus at any given time
- must synchronize local and system clocks for synchronous transfer
- requires control chips to tie into the system bus
w.

Processor Bus Access:

- Needs some kind of priority allocation

- Output a Bus Request >BRQ= to request the bus >> BRQ line goes to some controller
ww

- Input a Bus Grant >BGR= to gain access to bus >> BGR line from some controller
- Output a Bus Busy >BBSY= signal to hold the bus

Clocking:
- take both clocks and derive a common clock (ie: local clock & system clock)
or
- take leading edge of one of the clocks >> can alternate or change for each individual
operation (clock will jitter)

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BUS ALLOCATION SCHEMES:

Daisy Chaining:

- Need a bus controller to monitor bus busy and bus request signals

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- Sends a bus grant to a Master >> each Master either keeps the service or passes it on

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- Controller synchronizes the clocks

- Master releases the Bus Busy signal when finished

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Master 1 Master 2 Master N
...

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Bus A cces s Bus A cces s Bus A cces s
Lo gi c Lo gi c Lo gi c

BG R
no
Bus BR Q
Controller
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BBS Y
t
5s
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Polling:

- Controller sends address of device to grant bus access

- Can use priority resolution here:
memory= highest priority

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- Highest priority is granted first, if it does not respond, then a lower priority is granted, and so on
until someone accepts

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(ie: one request line, 3-bit grant line)

Master 1 Master 2 Master N

s.
Bu s Ac c e ss Bu s Ac c e ss
... Bu s Ac c e ss
Logi c Logi c Logi c

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Bus
Controller

Rotating
Encoder BR Q
no
0 to N BBS Y
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Independent:
t

- Each master has a request and grant line

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- Now just a question of priority

- Could have fixed priority, rotating priority, etc.

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usually fixed because memory is desired to be the highest priority

- Synchronization of the clocks must be performed once a Master is recognized

- Master will receive a common clock from one side and pass it to the controller which will derive a
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clock for transfer

- Can accurately predict calculations (since memory is always the highest priority)

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M a ste r 1 M a ste r 2 M a ste r N

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Bus A cce Bus A cce Bus A cce

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ss ss ss
Bu s Lo gi Lo gi Lo gi
Bu s G rant1 c Bu s c C
C o n t r o l ler

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5s
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3.4 8087 Co Processors
Overview

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�Each processor in the 80x86 family has a corresponding coprocessor with which it is
compatible.

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�Math Coprocessor is known as NPX,NDP,FUP.
Numeric processor extension (NPX),
Numeric data processor (NDP),
Floating point unit (FUP).

s.
Compatible Processor and Coprocessor

Processors
1. 8086 & 8088

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2. 80286
3. 80386DX
4. 80386SX
5. 80486DX no
6. 80486SX
Coprocessors
1. 8087
2. 80287,80287XL
3. 80287,80387DX
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4. 80387SX
5. It is Inbuilt
6. 80487SX
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Architecture of 8087

�Control Unit
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�Execution Unit

Control Unit
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�Control unit: To synchronize the operation of the coprocessor and the processor.
�This unit has a Control word and Status word and Data Buffer
�If instruction is an ESCape (coprocessor) instruction, the coprocessor executes it, if not
the microprocessor executes.
�Status register reflects the over all operation of the coprocessor.
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Architecture of 8087

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Status Register

15 0

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B C3 ST C2 C1 C0 ES PE UE OE ZE DE IE

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• C3-C0 Condition code bits
• TOP Top-of-stack (ST)
• ES Error summary

s.
• PE Precision error
• UE Under flow error
• OE Overflow error
• ZE Zero error

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• DE Denormalized error
• IE Invalid error
• B Busy bit

�B-Busy bit indicates that coprocessor is busy executing a task. Busy can be tested by
no
examining the status or by using the FWAIT instruction. Newer coprocessor
automatically synchronize with the microprocessor, so busy flag need not be tested
before performing additional coprocessor tasks.
�C3-C0 Condition code bits indicates conditions about the coprocessor.
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�TOP- Top of the stack (ST) bit indicates the current register address as the top of the
stack.
�ES-Error summary bit is set if any unmasked error bit (PE, UE, OE, ZE, DE, or IE) is
set. In the 8087 the error summary is also caused a coprocessor interrupt.
t

�PE- Precision error indicates that the result or operand executes selected precision.

�UE-Under flow error indicates the result is too large to be represent with the current
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precision selected by the control word.

�OE-Over flow error indicates a result that is too large to be represented. If this error is
masked, the coprocessor generates infinity for an overflow error.
�ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or
w.

non-zero number.
�DE-Denormalized error indicates at least one of the operand is denormalized.
�IE-Invalid error indicates a stack overflow or underflow, indeterminate from (0/0,0,-0,
etc) or the use of a NAN as an operand. This flag indicates error such as those produced
ww

by taking the square root of a negative number.

CONTROL REGISTER

�Control register selects precision, rounding control, infinity control.

�It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register.
�Instruction FLDCW is used to load the value into the control register.

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Control Register
15 0

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IC R C P C PM UM OM ZM DM IM

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•IC Infinity control
•RC Rounding control
•PC Precision control

s.
•PM Precision control
•UM Underflow mask
•OM Overflow mask
•ZM Division by zero mask
•DM Denormalized operand mask

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•IM Invalid operand mask
�IC –Infinity control selects either affine or projective infinity. Affine allows positive
and negative infinity, while projective assumes infinity is unsigned.

INFINITY CONTROL
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0 = Projective
1 = Affine
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�RC –Rounding control determines the type of rounding.

ROUNDING CONTROL
00=Round to nearest or even
01=Round down towards minus infinity
t

10=Round up towards plus infinity

11=Chop or truncate towards zero
5s

�PC- Precision control sets the precision of he result as define in table

PRECISION CONTROL
w.

00=Single precision (short)

01=Reserved
10=Double precision (long)
11=Extended precision (temporary)
�Exception Masks – It Determines whether the error indicated by the exception affects
ww

the error bit in the status register. If a logic1 is placed in one of the exception control bits,
corresponding status register bit is masked off.

Numeric Execution Unit

�This performs all operations that access and manipulate the numeric data in the
coprocessor‟s registers.
�Numeric registers in NUE are 80 bits wide.

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�NUE is able to perform arithmetic, logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM.
�Numeric data is routed into two parts ways a 64 bit mantissa bus and

m
a 16 bit sign/exponent bus.

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3.5 Pin Diagram of 8087

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no
t ar
5s
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Circuit Connection for 8086 – 8087

�Multiplexed address-data bus lines are connected directly from the 8086 to 8087.
ww

�The status lines and the queue status lines connected directly from 8086 to 8087.
�The Request / Grant signal RQ/GT0 of 8087 is connected to RQ /GT1 of 8086.

�BUSY signal 8087 is connected to TEST pin of 8086.

�Interrupt output INT of the 8087 to NMI input of 8086. This intimates an error
condition.

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�The main purpose of the circuitry between the INT output of 8087 and the NMI input is
to make sure that an NMI signal is not present upon reset, to make it possible to mask
NMI input and to make it possible for other devices to cause an NMI interrupt.
�BHE pin is connected to the system BHE line to enable the upper bank of memory.
�The RQ/GT1 input is available so that another coprocessor such as 8089 I/O processor
t

can be connected and function in parallel with the 8087.

�One type of Cooperation between the two processors that you need
5s

to know about it is how the 8087 transfers data between memory and its internal registers.
�When 8086 reads an 8087 instruction that needs data from memory or wants to send
data to memory, the 8086 sends out the memory address code in the instruction and sends
out the appropriate memory read or memory write signal to transfer a word of data.
w.

�In the case of memory read, the addressed word will be kept on the data bus by the
memory. The 8087 then simply reads the word of data bus. The 8086 ignores this word
.If the 8087 only needs this one word of data, it can then go on and executes its
instruction.
�Some 8087 instructions need to read in or write out up to 80-bit word. For these cases
ww

8086 outputs the address of the first data word on the address bus and outputs the
appropriate control signal.
�The 8087 reads the data word on the data bus by memory or writes a data word to
memory on the data bus. The 8087 grabs the 20-bit physical address that was output by
the 8086.To transfer additional words it needs to/from memory, the 8087 then takes over
the buses from 8086.
�To take over the bus, the 8087 sends out a low-going pulse on

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RQ/GT0 pin. The 8086 responds to this by sending another low going pulse back to the

RQ/GT0 pin of 8087 and by floating its buses.

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�The 8087 then increments the address it grabbed during the first transfer and outputs the
incremented address on the address bus. When the 8087 output a memory read or memory write

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signal, another data word will be transferred to or from the 8087.
�The 8087 continues the process until it has transferred all the data words required by
the instruction to/from memory.
�When the 8087 is using the buses for its data transfer, it sends another low-going pulse out on

s.
its RQ/ GT0 pin to 8086 to know it can have the buses back again. The next type of the
synchronization between the host processor and the coprocessor is that required to make sure the
8086 hast does not attempt to execute the next instruction before the 8087 has completed an
instruction.
�Taking one situation, in the case where the 8086 needs the data produced by the execution of

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an 8087 instruction to carry out its next instruction.
�In the instruction sequence for example the 8087 must complete the FSTSW STATUS
instruction before the 8086 will have the data it needs to execute the MOV AX , STATUS
instruction. no
�Without some mechanism to make the 8086 wait until the 8087 completes the FSTSW
instruction, the 8086 will go on and execute the MOV AX , STATUS with erroneous data .
�We solve this problem by connecting the 8087 BUSY output to the TEST pin of the 8086 and
putting on the WAIT instruction in the program.
�While 8087 is executing an instruction it asserts its BUSY pin high. When it is finished with an
ar
instruction, the 8087 will drop its BUSY pin low. Since the BUSY pin from 8087 is connected to
the TEST pin 8086 the processor can check its pin of 8087 whether it finished it instruction or
not.
�You place the 8086 WAIT instruction in your program after the 8087 FSTSW instruction
t

.When 8086 executes the WAIT instruction it enters an internal loop where it repeatedly checks
the logic level on the TEST input. The 8086 will stay in this loop until it finds the TEST input
5s

asserted low, indicating the 8087 has completed its instruction. The 8086 will then exit the
internal loop, fetch and execute the next instruction.
Example
FSTSW STATUS ;copy 8087 status word to memory
MOV AX, STATUS ;copy status word to AX to check ; bits
w.

(a)
�In this set of instructions we are not using WAIT instruction. Due to this the flow of execution
of command will takes place continuously even though the previous instruction had not finished
it‟s completion of its work .so we may lost data .
ww

FSTSW STATUS ;copy 8087 status word to memory

FWAIT ;wait for 8087 to finish before- ; doing next 8086 instruction
MOV AX,STATUS ;copy status word to AX to check ; bits
(b)
�In this code we are adding up of FWAIT instruction so that it will stop the execution of the
command until the above instruction is finishes it‟s work .so that you are not loosing data and
after that you will allow to continue the execution of instructions.

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�Another case where you need synchronization of the processor and the coprocessor is the case
where a program has several 8087 instructions in sequence.
�The 8087 are executed only one instruction at a time so you have to make sure that 8087 has

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completed one instruction before you allow the 8086 to fetch the next 8087 instruction from
memory.

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�Here again you use the BUSY-TEST connection and the FWAIT instruction to solve the
problem. If you are hand coding, you can just put the 8086 WAIT(FWAIT) instruction after each
instruction to make sure that instruction is completed before going on to next.
�If you are using the assembler which accepts 8087 mnemonics, the assembler will

s.
automatically insert the 8-bit code for the WAIT instruction ,10011011 binary (9BH), as the first
byte of the code for 8087 instruction.

INTERFACING

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�Multiplexed address-data bus lines are connected directly from the 8086 to 8087.
�The status lines and the queue status lines connected directly from 8086 to 8087.
�The Request/Grant signal RQ/GT0 of 8087 is connected to

RQ/GT1 of 8086.
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�BUSY signal 8087 is connected to TEST pin of 8086.
�Interrupt output INT of the 8087 to NMI input of 8086. This intimates an error condition.
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�A WAIT instruction is passed to keep looking at its TEST pin, until it finds pin Low to
indicates that the 8087 has completed the computation.
�SYNCHRONIZATION must be established between the processor and coprocessor in
two situations.
t

a) The execution of an ESC instruction that require the participation of the NUE must not be
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initiated if the NUE has not completed the execution of the previous instruction.

b) When a processor instruction accesses a memory location that is an operand of a previous

coprocessor instruction .In this case CPU must synchronize with NPX to ensure that it
has completed its instruction. Processor WAIT instruction is provided.
w.

Exception Handling

�The 8087 detects six different types of exception conditions that occur during instruction
ww

execution. These will cause an interrupt if unmasked and interrupts are enabled.

1)INVALID OPERATION
2)OVERFLOW
3)ZERO DIVISOR
4)UNDERFLOW
5)DENORMALIZED OPERAND
6)INEXACT RESULT

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3.6 Data Types

�Internally, all data operands are converted to the 80-bit temporary real format. We have 3

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types.

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•Integer data type
•Packed BCD data type
•Real data type

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Coprocessor data types

Integer Data Type

Packed BCD
Real data type

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Example
�Converting a decimal number into a Floating-point number.
1) Converting the decimal number into binary form.
no
2) Normalize the binary number
3) Calculate the biased exponent.
4) Store the number in the floating-point format.

Example
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Step Result
1) 100.25
2) 1100100.01 = 1.10010001 * 26
3) 110+01111111=10000101
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4 ) Sign = 0
Exponent =10000101
5s

Significand = 10010001000000000000000
•In step 3 the biased exponent is the exponent a 26 or 110,plus a bias of 01111111(7FH)
,single precision no use 7F and double precision no use 3FFFH.
•IN step 4 the information found in prior step is combined to form the floating point no.
w.

INSTRUCTION SET

�The 8087 instruction mnemonics begins with the letter F which stands for Floating
point and distinguishes from 8086.
ww

�These are grouped into Four functional groups.

�The 8087 detects an error condition usually called an exception when it executing an
instruction it will set the bit in its Status register.
Types
I. DATA TRANSFER INSTRUCTIONS.
II. ARITHMETIC INSTRUCTIONS.
III. COMPARE INSTRUCTIONS.
IV. TRANSCENDENTAL INSTRUCTIONS.
(Trigonometric and Exponential)

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I Data Transfers Instructions:

�REAL TRANSFER

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FLD Load real
FST Store real

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FSTP Store real and pop
FXCH Exchange registers
�INTEGER TRANSFER
FILD Load integer

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FIST Store integer
FISTP Store integer and pop
�PACKED DECIMAL TRANSFER(BCD)
FBLD Load BCD
FBSTP Store BCD and pop

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Example
�FLD Source- Decrements the stack pointer by one and copies a real number from a
stack element or memory location to the new ST.
•FLD ST(3) ;Copies ST(3) to ST. no
•FLD LONG_REAL[BX] ;Number from memory
;copied to ST.
�FLD Destination- Copies ST to a specified stack position or to a specified memory
location .
•FST ST(2) ;Copies ST to ST(2),and
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;increment stack pointer.
•FST SHORT_REAL[BX] ;Copy ST to a memory at a
;SHORT_REAL[BX]
�FXCH Destination – Exchange the contents of ST with the contents of a specified
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stack element.
•FXCH ST(5) ;Swap ST and ST(5)
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�FILD Source – Integer load. Convert integer number from memory to temporary-real
format and push on 8087 stack.
•FILD DWORD PTR[BX] ;Short integer from memory at [BX].
�FIST Destination- Integer store. Convert number from ST to integer and copy to
memory.
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•FIST LONG_INT ;ST to memory locations named LONG_INT.

�FISTP Destination-Integer store and pop. Identical to FIST except that stack pointer is
incremented after copy.
�FBLD Source- Convert BCD number from memory to temporary- real format and
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push on top of 8087 stack.

II Arithmetic Instructions:

�Four basic arithmetic functions:

Addition, Subtraction, Multiplication, and
Division.
�Addition

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FADD Add real
FADDP Add real and pop
FIADD Add integer

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�Subtraction
FSUB Subtract real

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FSUBP Subtract real and pop
FISUB Subtract integer
FSUBR Subtract real reversed
FSUBRP Subtract real and pop

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FISUBR Subtract integer reversed
�Multiplication
FMUL Multiply real
FMULP Multiply real and pop
FIMUL Multiply integer

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�Advanced
FABS Absolute value
FCHS Change sign FPREM
Partial remainder no
FPRNDINT Round to integer
FSCALE Scale
FSQRT Square root
FXTRACT Extract exponent and mantissa.
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Example
�FADD – Add real from specified source to specified destination Source can be a stack
or memory location. Destination must be a stack element. If no source or destination is
specified, then ST is added to ST(1) and stack pointer is incremented so that the result of
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addition is at ST.
•FADD ST(3), ST ;Add ST to ST(3), result in ST(3)
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•FADD ST,ST(4) ;Add ST(4) to ST, result in ST.

•FADD ;ST + ST(1), pop stack result at ST
•FADDP ST(1) ;Add ST(1) to ST. Increment stack
;pointer so ST(1) become ST.
•FIADD Car_Sold ;Integer number from memory + ST
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�FSUB - Subtract the real number at the specified source from the real number at the
specified destination and put the result in the specified destination.
•FSUB ST(2), ST ;ST(2)=ST(2) – ST.
•FSUB Rate ;ST=ST – real no from memory.
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•FSUB ;ST=( ST(1) – ST)

�FSUBP - Subtract ST from specified stack element and put result in specified stack
element .Then increment the pointer by one.
•FSUBP ST(1) ;ST(1)-ST. ST(1) becomes new ST
�FISUB – Integer from memory subtracted from ST, result in ST.
•FISUB Cars_Sold ;ST becomes ST – integer from memory

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III Compare Instructions:

�Comparison

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FCOM Compare real
FCOMP Compare real and pop

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FCOMPP Compare real and pop twice
FICOM Compare integer
FICOMP Compare integer and pop
FTST Test ST against +0.0

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FXAM Examine ST

III Transcendental Instruction:

�Transcendental FPTAN

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Partial tangent FPATAN
Partial arctangent F2XM1
2x - 1
FYL2X Y log2X no
FYL2XP1 Y log2(X+1)
Example
�FPTAN – Compute the values for a ratio of Y/X for an angle in ST. The angle must be
in radians, and the angle must be in the range of 0 < angle < π/4.�F2XM1 – Compute
Y=2x-1 for an X value in ST. The result Y replaces X in ST. X must be in the range
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0≤X≤0.5.
�FYL2X - Calculate Y(LOG2X).X must be in the range of 0 < X < ∞ any Y
must be in the range -∞<Y<+∞.
�FYL2XP1 – Compute the function Y(LOG2(X+1)).This instruction is almost identical
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to FYL2X except that it gives more accurate results when compute log of a number very
close to one.
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Constant Instructions.
�Load Constant Instruction
FLDZ Load +0.0
FLDI Load+1.0
FLDPI Load π
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FLDL2T Load log210

FLDL2E Load log2e
FLDLG2 Load log102
FLDLN2 Load loge2
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ALGORITHM
To calculate x to the power of y
•Load base, power.
•Compute (y )*( log2 x)
•Separate integer(i) ,fraction(f) of a real number
•Divide fraction (f) by 2
•Compute (2 f/2) * ( 2f/2)
•xy = (2x) * (2y )

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3.7 Assembly Language Programs :

Program to calculate x to the power of y

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.MODEL SMALL
.DATA

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x Dq 4.567 ;Base
y Dq 2.759 ;Power
temp DD
temp1 DD

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temp2 DD ;final real result
tempint DD
tempint1 DD ;final integer result
two DW
diff DD

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trunc_cw DW 0fffh
.STACK 100h
.CODE
start: mov ax, @DATA ;init data segment no
mov ds, ax
load: fld y ;load the power
fld x ;load the base
comput: fyl2x ;compute (y * log2(x))
fst temp ;save the temp result
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trunc: fldcw trunc_cw ;set truncation command
frndint
fld temp ;load real number of fyl2x
fist tempint ;save integer after truncation
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fld temp ;load the real number

getfrac: fisub tempint ;subtract the integer
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fst diff ;store the fraction

fracby2: fidiv two ;divide the fraction by 2
twopwrx: f2xm1 ;calculate the 2 to the power fraction
fst temp1 ;minus 1 and save the result
fld1 ;load1
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fadd ;add 1 to the previous result

fst temp1 ;save the result
sqfrac: fmul st(0),st(0) ;square the result as fraction
fst temp1 ;was halved and save the result
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fild tempint ;save the integer portion

fxch ;interchange the integer
;and power of fraction.
scale: fscale ;scale the result in real and ;integer
fst temp2 ;in st(1) and store
fist tempint1 ;save the final result in real and integer
over: mov ax,4c00h ;exit to dos
int 21h

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end start

3.8 8089 I/O Processors:

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The design of I/O subsystems is an integral and important step in computer system

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design. CPUs and I/O peripherals have generally non-compatible bus and timing requirements-a
fact that can result in significant degradation in system performance . The logical solution to this
problem has been the deployment of an intelligent I/O subsystem which ... isolates the CPU from
the I/O peripherals.' T APPLICATION I CPU is therefore free to proceed at full speed with its

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ROGPAMS primary task of internal program processing and It PROGRAMS data manipulation.
Control of all I/ operations is ATA BUFF then performed by an I/O processor, an integral part
of the I/O subsystem. The CPU maintains supervisory control over the system and issues
commands and messages to the I/O processor, which then pro- CP ceeds with al necessary
peripheral control operations to complete the desired I/O transaction. The I/O processor is

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responsible for device initialization, record selection, I/O transfer, simple data transformation,
error checking and retries, and it signals the CPU upon successful completion of the I/O transfer.
Microprocessors of today (such as the Intel 80864) have attained respectable performance evels
by innovative architectural and technological advances However, such advances in
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microprocessor performance may be seriously overshadowed by the constraints of traditional on-
intelligent I/O subsystems.

The Intel 8089 I/O processor is designed to solve such problems by providing the
necessary intelligence and capability to microcomputer I/O subsystems. The architecture of the
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I/O processor is designed to meet typical I/O system requirements, such as high speed DMA
transfers, peripheral synchronization, etc., and is better suited to I/O processing than a general-
purpose microprocessor. This article describes the Intel 8089 I/O processor. It contains a
description of the various IOP-based system architectures and an overview of their operation.
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The internal architecture of the IOP and a typical application example are then given to illustrate
its various features and capabilities that facilitate I/O subsystem design. The I/O processor
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contains two independent I/O channels and a processor on the same chip. When both channels
are running concurrently, the IOP employs the following priority algorithm for channel selection:
highest priority
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* DMA transfers
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* chained channel program

* DMA termination second priority
* channel attention service lowest priority
* normal channel program execution
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If both channels are requesting service for tasks with equal priorities, channel selection is done
according to two programmable priority bits. The priority bits may specify a rotating priority or
assign one channel to have higher priority than the other. The above priority selection scheme
ensures fast responses for time-critical I/O operations while providing overall user
programmability to perform channel selection.

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Register structure
The I/O processor maintains separate register sets for each of its two I/O channels,
enabling them to execute independently of one another. Each set contains 8 registers (Figure 5),

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and almost all of them can be used for general computation during channel program execution.
Eight of the 16 registers are 21 bits wide and can be used to address one megabyte of system

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memory or 64K bytes of I/O space. The 21st bit is used to select the address space as system or
local I/O space. The other 8 registers are 16 bits wide. The GA and GB registers are used to
reference the source and destination locations during any data transfer operation. The GC
register can also be used

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as a general register/pointer by the channel program. The task pointer serves as the channel
program counter which is initialized whenever the channel is started; it can also be manipulated
by the channel program. The BC register contains the number of bytes to be transferred during
DMA operation and can terminate the DMA transfer if byte count termination is selected. The IX
register is used as an index in the indexed addressing mode. The mask/compare register is used

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to perform masked byte comparisons during channel program execution and DMA operations.
During program execution, the comparisons are used for conditional jumping, and in DMA, they
may terminate the current DMA transfqr. The control register is a special 16-bit register which
defines the channel's operation during DMA transfer operations.
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Input-Output Processor (IOP)
Instead of having each interface communicate with the CPU, a computer may incorporate
one or more external processors and assign them the task of communicating directly with all I/O
devices. An input-output processor (IOP) may be classified as a processor with direct memory
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access capability that communicates with I/O devices. In this configuration, the computer
system can be divided into a memory unit, and a number of processors comprised of the CPU
and one or more IOPs. Each IOP takes care of input and output tasks, relieving the CPU from the
housekeeping chores involved in I/O transfers. A processor that communicates with remote
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terminals over telephone and other communication media in a serial fashion is called a data
communication processor (DCP).
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The IOP is similar to a CPU except that it is designed to handle the details of I/O
processing, Unlike the DMA controller that must be set up entirely by the CPU, the IOP can
fetch and execute its own instructions. IOP instructions are specifically designed to facilitate I/O
transfers. In addition, the IOP can perform other processing asks, such as arithmetic, logic,
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branching, and code translation. The block diagram of a computer with two processors is shown
in Fig. 4-19. The memory unit occupies a central position and can communicate with each
processor by means of direct memory access. The CPU is responsible for processing data needed
in the solution of computation tasks. The IOP provides a path for transfer of data between
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various peripheral devices and the memory unit. The CPU is usually assigned the task of
initiating the I/O program. From then on the IOP operates independent of the CPU and continues
to transfer data from external devices and memory.

The data formats of peripheral devices differ from memory and CPU data formats. The
IOP must structure data words from many different sources. For example, it may be necessary to
take four bytes from an input device and pack them into one 32-bit word before the transfer to
memory. Data are gathered in the IOP at the device rate and bit capacity while the CPU is

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executing its own program. After the input data are assembled into a memory word, they are
transferred from IOP directly into memory by "stealing" one memory cycle from the CPU.
Similarly, an output word transferred from memory to the IOP is directed from the IOP to the

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output device at the device rate and bit capacity.

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The communication between the IOP and the devices attached to it is similar to the program
control method of transfer. Communication with the memory is similar to the direct memory
access method. The way by which the CPU and IOP communicate depends on the level of
sophistication included in the system. In very-large-scale computers, each processor is

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independent of all others and anyone processor can initiate an operation. In most computer
systems, the CPU is the master while the IOP is a slave processor. The CPU is assigned the task
of initiating all operations, but I/O instructions are executed in the IOP. CPU instructions provide
operations to start an I/O transfer and also to test I/O status conditions needed for making

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decisions on various I/O activities. The IOP, in turn, typically asks for CPU attention by means
of an interrupt. It also responds to CPU requests by placing a status word in a prescribed location
in memory to be examined later by a CPU program. When an I/O operation is desired, the CPU
informs the IOP where to find the I/O program and then leaves the transfer details to the IOP.
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Instructions that are read from memory by an IOP are sometimes called commands, to istinguish
them from instructions that are read by the CPU. Otherwise, an instruction and a command have
similar functions. Commands are prepared by experienced programmers and are stored in
memory. The command words constitute the program for the IOP. The CPU informs the 10P
where to find the commands in memory when it is time to execute the I/O program.
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3.10 CPU-IOP Communication

The communication between CPU and IOP may take different forms, depending on the
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particular computer considered. In most cases the memory unit acts as a message center where
each processor leaves information for the other. To appreciate the operation of a typical IOP, we
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will illustrate by a specific example the method by which the CPU and IOP communicate. This is
a simplified example that omits many operating details in order to provide an overview of basic
concepts. The CPU sends an instruction to test the IOP path. The IOP responds by inserting a
status word in memory for the CPU to check. The bits of the status word indicate the condition
of the IOP and I/O device, such as IOP overload condition, device busy with another transfer, or
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device ready for I/O transfer. The CPU refers to the status word in memory to decide what to do
next. If all is in order, the CPU sends the instruction to start I/O transfer. The memory address
received with this instruction tells the IOP where to find its program.
The CPU can now continue with another program while the IOP is busy with the I/O
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program. Both programs refer to memory by means of DMA transfer. When the IOP terminates
the execution of its program, it sends an interrupt request to the CPU. The CPU responds to the
interrupt by issuing an instruction to read the status from the IOP. The IOP responds by placing
the contents of its status report into a specified memory location. The status word indicates
whether the transfer has been completed or if any errors occurred during the transfer. From
inspection of the bits in the status word, the CPU determines if the I/O operation was completed
satisfactorily without errors. The IOP takes care of all data transfers between several I/O units
and the memory while the CPU is processing another program. The IOP and CPU are competing
for the 1.lSe of memory, so the number of devices that can be in operation is limited by the

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access rune of the memory. It is not possible-to saturate the memory by I/O devices in most
systems, as the speed of most devices is much slower than the CPU. However, some very fast
units, such as magnetic disks, can use an appreciable number of the available memory cycles. In

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that case, the speed of the CPU may deteriorate because it will often have to wait for the IOP to
conduct memory transfers.

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QUESTION BANK
PART – A (2 MARKS)

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1. How clock signal is generated in 8086? What is the maximum internal clock
frequency of 8086?
2. Define the multiprocessor system.

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3. Draw and explain the time shared bus.
4. List the advantages of multiprocessor system.
5. What is bus arbiter? What is the function of that bus arbiter?
6. Write the features of 8087.
7. List the function of 8086 pin no
(a) NMI
(b) DT / R
(c) QS0 – QS1
8. Explain the function of
(a) BUSY
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(b) RQ / GT
(c) INT
9. What are the schemes used for establishing priority in order to resolve bus
arbitration problem?
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10. How single stepping can be done in 8086?

11. State the signification of LOCK signal in 8086?
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PART – B (16 MARKS)

1. a) Draw and explain the maximum mode of 8086. (12)

b) List the advantages of multiprocessor system. (04)
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2. a) Explain the functions of

(a) HLDA (04)
(b) RQ/GT0 (04)
(c) DEN (04)
(d) ALE (04)
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3. a) Draw and explain the block diagram of minimum mode of operation. (12)
b) Write notes on addressing memory. (04)
4. Define the bus cycle and minimum modes read and write bus cycles with proper timing
diagram. (16)
5. a) Draw the input and output timing diagram of maximum mode of operation in
8086. (10)
b) Explain the addressing capabilities of 8086. (06)
6. a) Draw and explain the bit pattern of the control registers of 8087. (04)
b) Draw and explain the block diagram of 8087. (12)

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UNIT IV I/O INTERFACING

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4.1.1 Memory Interfacing

The memory is made up of semiconductor material used to store the programs and data. Three

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types of memory is,

 Process memory
 Primary or main memory

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 Secondary memory

TYPICAL EPROM AND STATIC RAM:

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A typical semiconductor memory IC will have n address pins, m data pins (or output
pins).

Having two power supply pins (one for connecting required supply voltage (V and
the other for connecting ground). no
The control signals needed for static RAM are chip select (chip enable), read control
(output enable) and write control (write enable).
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The control signals needed for read operation in EPROM are chip select (chip enable)
and read control (output enable).
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EXAMPLE-1

Consider a system in which the full memory space 64kb is utilized for EPROM memory.

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Interface the EPROM with 8085 processor.

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The memory capacity is 64 Kbytes. i.e
2^n = 64 x 1000 bytes where n = address lines.
So, n = 16.
In this system the entire 16 address lines of the processor are connected to address input

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pins of memory IC in order to address the internal locations of memory.
The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).
Since the processor is connected to EPROM, the active low RD pin is connected to active
low output enable pin of EPROM.
The range of address for EPROM is 0000H to FFFFH.

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EXAMPLE-2
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Consider a system in which the available 64kb memory space is equally divided between
EPROM and RAM. Interface the EPROM and RAM with 8085 processor.

Implement 32kb memory capacity of EPROM using single IC 27256.

32kb RAM capacity is implemented using single IC 62256.
The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the
processor are connected to 15 address pins of both EPROM and RAM.
The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and If
A15 is 0, it select EPROM.

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Inverter is used for selecting the memory.
The memory used is both Ram and EPROM, so the low RD and WR pins of processor
are connected to low WE and OE pins of memory respectively.

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The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 8000H
to FFFFH.

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EXAMPLE-3

Consider a system in which 32kb memory space is implemented using four numbers of 8kb
memory. Interface the EPROM and RAM with 8085 processor.
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The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and
the remaining two numbers be RAM.
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Each 8kb memory requires 13 address lines and so the address lines A0- A12 of
the processor are connected to 13 address pins of all the memory.
The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four
chip select signals.
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These four chip select signals can be used to select one of the four memory IC at any
one time.
The address line A15 is used as enable for decoder.
The simplified schematic memory organization is shown.
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4.1.2 I/O STRUCTURE OF A TYPICAL MICROCOMPUTER:
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There are three major types of data transfer between the microcomputer and art I/O device. They
are,

Programmed I/O : In programmed I/O the data transfer is accomplished through an I/O
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port and controlled by software.

Interrupt driven I/O : In interrupt driven I/O, the I/O device will interrupt the
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processor, and initiate data transfer.

Direct memory access (DMA) : In DMA, the data transfer between memory and I/O
can be performed by bypassing the microprocessor.
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INTERFACING I/O AND PERIPHERAL DEVICES:

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1. For data transfer from input device to processor the following operations are performed.

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The input device will load the data to the port.
When the port receives a data, it sends message to the processor to read the data.
The processor will read the data from the port.
After a data have been read by the processor the input device will load the next data into
the port.

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2. For data transfer from processor to output device the following operations are performed.

The processor will load the data to the port.

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The port will send a message to the output device to read the data.
The output device will read the data from the port.
After the data have been read by the output device the processor can load the next data to
the port.

8212
The 8212 is a 24 pin IC.
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The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355 and 8755.

It consists of eight number of D-type latches.

It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8
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The 8212 can be used as an input or output device
It has two selecting device DS1 (low) and DS2.

If,
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There are two types for interfacing I/O devices:

1. Memory mapped I/O device.

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2. Standard I/O mapped I/O device or isolated I/O mapping.

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Example 1:

A system requires 16kb EPROM and 16kb RAM. Also the system has 2 numbers of 8255, one
number of 8279, one number of 8251 and one number of 8254. (8255 - Programmable peripheral
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interface; 8279-Keyboard/display controller, 8251 - USART and 8254 - Timer). Draw the
Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O
mapped.

The I/O devices in the system should be mapped by standard I/O mapping. Hence
separate decoders can be used to generate chip select signals for memory IC and
peripheral IC's.
For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.

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For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.
The 8kb memories require 13 address lines. Hence the address lines A0 - A12 are used
for selecting the memory locations.

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The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-to-
8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/ M(low) of

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8085, so that this decoder is enabled for memory read/write operation. The other enable
pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of the
decoder are used to select memory lCs and the remaining 4 are kept for future expansion.
The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.

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The RAM is mapped at the end of memory space from C000 to FFFFH.
There are five peripheral IC's to be interfaced to the system. The chip-select signals for
these IC's are given through another 3-to-8 decoder 74LS138 (I/O decoder). The input to
this decoder is A11, A12 and A13
The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O

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decoder.
The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this
decoder is enabled for I/O read/write operation.
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The 16 bit address for the memory and 8255 devices are,

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4.2 PARALLEL COMMUNICATION INTERFACE

The Intel 8255 (or i8255) Programmable Peripheral Interface chip is a peripheral chip originally

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developed for the Intel 8085 microprocessor, and as such is a member of a large array of such
chips, known as the MCS-85 Family.This chip was later also used with the Intel 8086 and its

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descendants. It was later made (cloned) by many other manufacturers. It is made in DIP 40 and
PLCC 44 pins encapsulated versions.

This chip is used to give the CPU access to programmable parallel I/O, and is similar to other

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such chips like the Motorola 6520 PIA (Peripheral Interface Adapter) the MOS Technology 6522
(Versatile Interface Adapter) and the MOS Technology CIA (Complex Interface Adapter) all
developed for the 6502 family. Other such chips are the 2655 Programmable Peripheral Interface
from the Signetics 2650 family of microprocessors, the 6820 PIO (Peripheral Input/Output) from
the Motorola 6800 family, the Western Design Center WDC 65C21, an enhanced 6520, and

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many others.The 8255 is widely used not only in many microcomputer/microcontroller systems
especially Z-80 based, home computers such as SV-328 and all MSX, but also in the system
board of the best known original IBM-PC, PC/XT, PC/jr, etc. and clones.However, most often
the functionality the 8255 offered is now not implemented with the 8255 chip itself anymore, but
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is embedded in a larger VLSI chip as a sub function. The 8255 chip itself is still made, and is
sometimes used together with a micro controller to expand its I/O capabilities.

4.2.1Functional Block diagram:

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The 8255 has 24 input/output pins in all. These are divided into three 8-bit ports. Port A and port
B can be used as 8-bit input/output ports. Port C can be used as an 8-bit input/output port or as
two 4-bit input/ouput ports or to produce handshake signals for ports A and B.
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The three ports are further grouped as follows:

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1) Group A consisting of port A and upper part of port C.

2) Group B consisting of port B and lower part of port C.

Eight data lines (D0 - D7) are available (with an 8-bit data buffer) to read/write data into the
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ports or control register under the status of the " RD" (pin 5) and WR" (pin 36), which are
active low signals for read and write operations respectively. The address lines A1 and A0 allow
to successively access any one of the ports or the control register as listed below:
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FIGURE 1

A1 A0 Function
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0 0 port A
0 1 port B
1 0 port C
1 1 control register
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The control signal "' CS" (pin 6) is used to enable the 8255 chip. It is an active low signal, ie,
when CS = '0, the 8255 is enabled. The RESET input (pin 35) is connected to a system (like
8085, 8086, etc. ) reset line so that when the system is reset, all the ports are initialised as input
lines. This is done to prevent 8255 and/or any peripheral connected to it, from being destroyed
due to mismatch of ports. This is explained as follows. Suppose an input device is connected to
8255 at port A. If from the previous operation, port A is initialised as an output port and if 8255
is not reset before using the current configuration, then there is a possibility of damage of either

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the input device connected or 8255 or both since both 8255 and the device connected will be
sending out data.

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The control register or the control logic or the command word register is an 8-bit register used to
select the modes of operation and input/output designation of the ports.

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4.2.2 Pin Configuration:

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D0 - D7 These are the data input/output lines for the device. All information read from and
written to the 8255 occurs via these 8 data lines.
CS (Chip Select Input). If this line is a logical 0, the microprocessor can read and write to the
8255.
RD (Read Input) Whenever this input line is a logical 0 and the RD input is a logical 0, the 8255
data outputs are enabled onto the system data bus.

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WR (Write Input) Whenever this input line is a logical 0 and the CS input is a logical 0, data is
written to the 8255 from the system data bus
A0 - A1 (Address Inputs) The logical combination of these two input lines determines which

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internal register of the 8255 data is written to or read from.
RESET The 8255 is placed into its reset state if this input line is a logical 1. All peripheral ports

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are set to the input mode.
PA0 - PA7, PB0 - PB7, PC0 - PC7 These signal lines are used as 8-bit I/O ports. They can be
connected to peripheral devices. The 8255 has three 8 bit I/O ports and each one can be
connected to the physical lines of an external device. These lines are labeled PA0-PA7, PB0-

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PB7, and PC0-PC7. The groups of the signals are divided into three different I/O ports labeled
port A (PA), port B (PB), and port C (PC).

4.2.3 Operational Modes of 8255

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There are two main operational modes of 8255:

1. Input/output mode 2. Bit set/reset mode

Input/Output Mode
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There are three types of the input/output mode. They are as follows:
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Mode 0

In this mode, the ports can be used for simple input/output operations without handshaking. If
both port A and B are initialized in mode 0, the two halves of port C can be either used together
as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of
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port C are independent, they may be used such that one-half is initialized as an input port while
the other half is initialized as an output port. The input output features in mode 0 are as follows:
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1. O/p are latched. 2. I/p are buffered not latched. 3. Port do not have handshake or interrupt
capability.

Mode 1
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When we wish to use port A or port B for handshake (strobed) input or output operation, we
initialise that port in mode 1 (port A and port B can be initilalised to operate in different
modes,ie, for eg, port A can operate in mode 0 and port B in mode 1). Some of the pins of port C
function as handshake lines. For port B in this mode (irrespective of whether is acting as an input
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port or output port), PC0, PC1 and PC2 pins function as handshake lines. If port A is initialised
as mode 1 input port, then, PC3, PC4 and PC5 function as handshake signals. Pins PC6 and PC7
are available for use as input/output lines. The mode 1 which supports handshaking has
following features: 1. Two ports i.e. port A and B can be use as 8-bit i/o port. 2. Each port uses
three lines of port c as handshake signal and remaining two signals can be function as i/o port. 3.
interrupt logic is supported. 4. Input and Output data are latched.

Mode 2

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Only group A can be initialised in this mode. Port A can be used for bidirectional
handshake data transfer. This means that data can be input or output on the same eight lines
(PA0 - PA7). Pins PC3 - PC7 are used as handshake lines for port A. The remaining pins of port

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C (PC0 - PC2) can be used as input/output lines if group B is initialised in mode 0. In this mode,
the 8255 may be used to extend the system bus to a slave microprocessor or to transfer data bytes

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to and from a floppy disk controller.

Bit Set/Reset (BSR) mode

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In this mode only port b can be used (as an output port). Each line of port C (PC0 - PC7) can be
set/reset by suitably loading the command word register.no effect occurs in input-output mode.
The individual bits of port c can be set or reset by sending the signal OUT instruction to the
control register.

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4.2.3 Control Word Format

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Control Word format in input/output mode

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The figure shows the control word format in the input/output mode. This mode is selected
by making D7 = '1' .

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D0, D1, D3, D4 are for lower port C, port B, upper port C and port A respectively. When
D0 or D1 or D3 or D4 are "SET", the corresponding ports act as input ports. For eg, if D0

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= D4 = '1', then lower port C and port A act as input ports. If these bits are "RESET", then
the corresponding ports act as output ports. For eg, if D1 = D3 = '0', then port B and
upper port C act as output ports.

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D2 is used for mode selection for group B (Port B and Lower Port C). When D2 = '0',
mode 0 is selected and when D2 = '1', mode 1 is selected.

D5, D6 are used for mode selection for group A (Upper Port C and Port A). The format is
as follows:

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D6 D5 mode
0 0 0
0 1 1 no
1 x 2

Example: If port B and upper port C have to be initialised as input ports and lower port C and
port A as ouput ports (all in mode 0), what is the control word?
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o 1. Since it is an input/ouput mode, D7 = '1'.

o 2. Mode selection bits, D2, D5, D6 are all '0' for mode 0 operation.
o 3. Port B should operate as input port, hence, D1 = '1'.
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o 4. Upper port C should also be an input port, hence, D3 = '1'.

o 5. Port A has to operate output port, hence, D4 = '0'.
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o 6. Lower port C should also operate as output port, hence, D0 = '0'.

Applying the corresponding values to the format in input/output mode, we get the control word
as "8A (hex)"
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BSR mode format

File:8255ctrlformat bsr.gif
Control Word format in BSR mode
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The figure shows the control word format in BSR mode. This mode is selected by making
D7='0'.

D0 is used for bit set/reset. When D0= '1', the port C bit selected (selection of a port C bit
is shown in the next point) is SET, when D0 = '0', the port C bit is RESET.

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D1, D2, D3 are used to select a particular port C bit whose value may be altered using D0
bit as mentioned above. The selection of the port C bits are done as follows:

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D3 D2 D1 bit/pin of port C selected
0 0 0 PC0

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0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4

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1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

D4, D5, D6 are not used.

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Example: If the 5th bit (PC5) of port C has to be "SET", then what is the control word?

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o
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1. Since it is BSR mode, D7 = '0'.
2. Since D4, D5, D6 are not used, assume them to be '0'.
o 3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
o 4. PC5 has to be set, hence, D0 = '1'.
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Applying the above values to the format for BSR mode, we get the control word as "0B (hex)".

4.3 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER

TRANSMITTER (USART) (8251)
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The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter)

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for serial data communication. As a peripheral device of a microcomputer system, the 8251
receives parallel data from the CPU and transmits serial data after conversion. This device
also receives serial data from the outside and transmits parallel data to the CPU after
conversion.
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4.3.1 Block diagram of the 8251 USART (Universal Synchronous Asynchronous Receiver
Transmitter)
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The 8251 functional configuration is programmed by software. Operation between the 8251
and a CPU is executed by program control. Table 1 shows the operation between a CPU
and the device.

Control Words
There are two types of control word.
1. Mode instruction (setting of function)

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2. Command (setting of operation)

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Table 1 Operation between a CPU and 8251

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1) Mode Instruction

Mode instruction is used for setting the function of the 8251. Mode instruction will be in

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"wait for write" at either internal reset or external reset. That is, the writing of a control
word after resetting will be recognized as a "mode instruction."

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Items set by mode instruction are as follows:

• Synchronous/asynchronous mode

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• Stop bit length (asynchronous mode)
• Character length
• Parity bit
• Baud rate factor (asynchronous mode)
• Internal/external synchronization (synchronous mode)

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• Number of synchronous characters (Synchronous mode)

The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of
synchronous mode, it is necessary to write one-or two byte sync characters. If sync
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characters were written, a function will be set because the writing of sync characters
constitutes part of mode
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instruction.

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2) Command

Command is used for setting the operation of the 8251. It is possible to write a command
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whenever necessary after writing a mode instruction and sync characters.

Items to be set by command are as follows:

• Transmit Enable/Disable
• Receive Enable/Disable
• DTR, RTS Output of data.
• Resetting of error flag.
• Sending to break characters

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• Internal resetting
• Hunt mode (synchronous mode)

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Status Word

It is possible to see the internal status of the 8251 by reading a status word. The bit

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configuration of status word is shown in Fig. 5.

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4.3.2 Pin Description

D 0 to D 7 (l/O terminal)

This is bidirectional data bus which receive control words and transmits data from the
CPU and sends status words and received data to CPU.

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RESET (Input terminal)

A "High" on this input forces the 8251 into "reset status." The device waits for the writing

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of "mode instruction." The min. reset width is six clock inputs during the operating status
of CLK.

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CLK (Input terminal)

CLK signal is used to generate internal device timing. CLK signal is independent of RXC

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or TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC
at Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at
Asynchronous "x16" and "x64" mode.

WR (Input terminal)

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This is the "active low" input terminal which receives a signal for writing transmit data
and control words from the CPU into the 8251.

RD (Input terminal)
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This is the "active low" input terminal which receives a signal for reading receive data and
status words from the 8251.
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C/D (Input terminal)

This is an input terminal which receives a signal for selecting data or command words and
status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If
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C/D = high, command word or status word will be accessed.

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CS (Input terminal)

This is the "active low" input terminal which selects the 8251 at low level when the CPU
accesses. Note: The device won’t be in "standby status"; only setting CS = High.
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TXD (output terminal)

This is an output terminal for transmitting data from which serial-converted data is sent
out. The device is in "mark status" (high level) after resetting or during a status when
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transmit is disabled. It is also possible to set the device in "break status" (low level) by a
command.

TXRDY (output terminal)

This is an output terminal which indicates that the 8251is ready to accept a transmitted
data character. But the terminal is always at low level if CTS = high or the device was set in
"TX disable status" by a command. Note: TXRDY status word indicates that transmit data

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character is receivable, regardless of CTS or command. If the CPU writes a data character,
TXRDY will be reset by the leading edge or WR signal.

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TXEMPTY (Output terminal)

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This is an output terminal which indicates that the 8251 has transmitted all the characters
and had no data character. In "synchronous mode," the terminal is at high level, if
transmit data characters are no longer remaining and sync characters are automatically
transmitted. If the CPU writes a data character, TXEMPTY will be reset by the leading

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edge of WR signal. Note : As the transmitter is disabled by setting CTS "High" or
command, data written before disable will be sent out. Then TXD and TXEMPTY will be
"High". Even if a data is written after disable, that data is not sent out and TXE will be
"High".After the transmitter is enabled, it sent out. (Refer to Timing Chart of Transmitter
Control and Flag Timing)

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TXC (Input terminal)

This is a clock input signal which determines the transfer speed of transmitted data. In
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"synchronous mode," the baud rate will be the same as the frequency of TXC. In
"asynchronous mode", it is possible to select the baud rate factor by mode instruction. It
can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data out of the 8251.
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RXD (input terminal)

This is a terminal which receives serial data.

RXRDY (Output terminal)

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This is a terminal which indicates that the 8251 contains a character that is ready to
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READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of RD
signal. Unless the CPU reads a data character before the next one is received completely,
the preceding data will be lost. In such a case, an overrun error flag status word will be set.
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RXC (Input terminal)

This is a clock input signal which determines the transfer speed of received data. In
"synchronous mode," the baud rate is the same as the frequency of RXC. In
"asynchronous mode," it is possible to select the baud rate factor by mode instruction. It
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can be 1, 1/16, 1/64 the RXC.

SYNDET/BD (Input or output terminal)

This is a terminal whose function changes according to mode. In "internal synchronous

mode." this terminal is at high level, if sync characters are received and synchronized. If a
status word is read, the terminal will be reset. In "external synchronous mode, "this is an
input terminal. A "High" on this input forces the 8251 to start receiving data characters.

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In "asynchronous mode," this is an output terminal which generates "high level"output
upon the detection of a "break" character if receiver data contains a "low-level" space
between the stop bits of two continuous characters. The terminal will be reset, if RXD is at

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high level. After Reset is active, the terminal will be output at low level.

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DSR (Input terminal)

This is an input port for MODEM interface. The input status of the terminal can be
recognized by the CPU reading status words.

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DTR (Output terminal)

This is an output port for MODEM interface. It is possible to set the status of DTR by a
command.

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CTS (Input terminal)

This is an input terminal for MODEM interface which is used for controlling a transmit
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circuit. The terminal controls data transmission if the device is set in "TX Enable" status
by a command. Data is transmitable if the terminal is at low level.

RTS (Output terminal)

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This is an output port for MODEM interface. It is possible to set the status RTS by a
command.

4.4 8253 Timer IC General

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The Intel 8253 is a programmable counter / timer chip designed for use as an Intel
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microcomputer peripheral. It uses nMOS technology with a single +5V supply and is packaged
in a 24-pin plastic DIP.

It is organized as 3 independent 16-bit counters, each with a counter rate up to 2 MHz. All modes
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of operation are software programmable.

The 82C54 is pin compatible with the HMOS 8254, and is a superset of the 8253.

Six programmable timer modes allow the 82C54 / 8253 to be used as an event counter, elapsed
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time indicator, programmable one-shot, and in many other applications.

4.4.1 Block diagram

The timer has three independent, programmable counters and they are all identical. The
block labeled data bus buffer contains the logic to buffer the data bus to / from the
microprocessor, and to the internal registers. The block labeled read / write logic controls the
reading and the writing of the counter registers. The final block, the control word register,

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contains the programmed information that is sent to the device from the microprocessor. In effect
this register defines how the 8253 logically works.

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Block diagram of an 8253 programmable interval timer

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Each counter in the block diagram has 3 logical lines connected to it. Two of these lines,
clock and gate, are inputs. The third, labeled OUT is an output. The function of these lines
changes and depends on how the device is initialized or programmed.
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4.4.2 PIN configuration

The following picture shows the pin configuration of the 8253 and a general definition of the
lines follows:
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Clock This is the clock input for the counter. The counter is 16 bits. The maximum clock
frequency is 1 / 380 nanoseconds or 2.6 megahertz. The minimum clock frequency is DC or
static operation.

Out This single output line is the signal that is the final programmed output of the device. Actual
operation of the out line depends on how the device has been programmed.

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Gate This input can act as a gate for the clock input line, or it can act as a start pulse, depending
on the programmed mode of the counter.

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4.4.3 Uses of the 8253 gate input pin.

.
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Signal Status Low or going low Rising High

Mode

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0 Disables counting -- Enables counting

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1) Initiates counting
1 -- 2) Resets output --

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after next clock

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1) Disables counting
1) Reloads counter
2 2) Sets output Enables counting
2) Initiates counting
immediately high
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1) Disables counting
3 2) Sets output Initiates counting Enables counting
immediately high
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4 Disables counting -- Enables counting

5 -- Initiates counting --
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This table shows the different uses of the 8253 gate input pin.

Each mode of operation for the counter has a different use for the GATE input pin

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4.4.4 Internal 8253 registers

Here is a list of the internal 8253 registers that will program the internal counters of the 8253:

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RD WR A0 A1 function

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1 0 0 0 Load counter 0
COUNTER 0
0 1 0 0 Read counter 0

COUNTER 1
1 0
no 0 1 Load counter 1

0 1 0 1 Read counter 1
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1 0 1 0 Load counter 2
COUNTER 2
0 1 1 0 Read counter 2
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1 0 1 1 Write mode word

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MODE WORD or
CONTROL WORD

-- 0 1 1 1 No-operation
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Counter #0, #1, #2 Each counter is identical, and each consists of a 16-bit, pre-settable, down
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counter. Each is fully independent and can be easily read by the CPU. When the counter is read,
the data within the counter will not be disturbed. This allows the system or your own program to
monitor the counter's value at any time, without disrupting the overall function of the 8253.

Control Word Register This internal register is used to write information to, prior to using the
device. This register is addressed when A0 and A1 inputs are logical 1's. The data in the register
controls the operation mode and the selection of either binary or BCD ( binary coded decimal )

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counting format. The register can only be written to. You can't read information from the
register.

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Control Word Register

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CONTROL BYTE D7 - D0

D7 D6 D5 D4 D3 D2 D1 D0

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SC1 SC0 RL1 RL0 M2 M1 M0 BCP

All of the operating modes for the counters are selected by writing bytes to the control register.
This is the control word format. no
D7 D6 Counter Select
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SC1 SC0

0 0 counter 0

0 1 counter 1
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1 0 counter 2
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1 1 illegal value

D5 D4
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RL1 RL0 R / L Definition

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Bits D7 and D6 are labeled SC1 and SC0. These bits select the counter to be programmed, it is
necessary to define, using the control bits D7 and D6, which counter is being set up.

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0 0
Counter value is latched. This means

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that the selected counter has its
contents transferred into a temporary
latch, which can then be read by the CPU.

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0 1 Read / load least-significant byte only.

1 0 Read / load most-significant byte only.

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1 1 Read / load least-significant byte first,
then most-significant byte.
Once a counter is set up, it will remain that way until it is changed by another control word.

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Bits D5 and D4 ( RL1 / RL0 ) of the control word shown above are defined as the read / load
mode for the register that is selected by bits D7 and D6. Bits D5 and D4 define how the
particular counter is to have data read from or written to it by the CPU.

These bits are defined as:

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The 1st value, $00, is the counter latch mode. If this mode is specified, the current counter value
is latched into an internal register at the time of the I/O write operation to the control register.
When a read of the counter occurs, it is this latched value that is read.
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Caution: If the latch mode is not used, then it is possible that the data read back

may be in the process of changing while the read is occurring. This could result in invalid data
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being input by the CPU ( see the timing diagrams to the 8253 by intel's site or go to page
"Memory mapped I/O" ). To read the counter value while the counter is still in the process of
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counting, one must first issue a latch control word, and then issue another control word that
indicates the order of the bytes to be read.

An alternative method of obtaining a stable count from the timer is to externally inhibit counting
while the register is being read. To this, an external logic to the 8253 controlled by the Z80 to
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inhibit count during an input read operation is to connect.

Each technique has certain disadvantages. The first, the latching method, may give the CPU a
reading that is "old" by several cycles, depending on the speed of the count and which byte of the
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counter is being read.

The second method, the external inhibiting function, requires additional hardware. In addition, it
may change the overall system operation. The counters 1 and 2 of the MZ-700 are not designed
with this additional hardware function. :-( but the counter 0. You can use this method for your
own purposes even an amplifier is connected to the output pin of this counter.
The input to counter 0 is 1.1088MHz.

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The next 3 bits of the control word are D3, D2, and D1. These bits determine the basic mode of
operation for the selected counter. The mode descriptions follows:

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D3 D2 D1
Mode value

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M2 M1 M0

0 0 0 mode 0: interrupt on terminal count

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0 0 1 mode 1: programmable one-shot

x 1 0 mode 2: rate generator

x 1 1 mode 3: square wave generator

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1 0 0 mode 4: software triggered strobe

1 0 1 mode 5: hardware triggered strobe

D0 counts down in
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The final bit D0 of the control register determines how the register will
count:
0 binary
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The maximum values for the count in each count mode are 104 (
1 BCD 10,000 decimal ) in BCD, and 216 ( 65,536 decimal ) in binary.

4.4.5 Modes
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The following text describes all possible modes. The modes used in the MZ-700 and set by the
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monitor's startup are mode 0, mode 2, and mode 3.

Mode Interrupt on Terminal Count

0
The counter will be programmed to an initial value and afterwards counts down at a rate
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equal to the input clock frequency. When the count is equal to 0, the OUT pin will be a
logical 1. The output will stay a logical 1 until the counter is reloaded with a new value
or the same value or until a mode word is written to the device.
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Once the counter starts counting down, the GATE input can disable the internal counting
by setting the GATE to a logical 0 ( see the table above ).
Mode Programmable One-Shot
1
In mode 1, the device can be setup to give an output pulse that is an integer number of
clock pulses. The one-shot is triggered on the rising edge of the GATE input. If the
trigger occurs during the pulse output, the 8253 will be retriggered again.

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Mode Rate Generator
2

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The counter that is programmed for mode 2 becomes a "divide by n" counter. The OUT
pin of the counter goes to low for one input clock period. The time between the pulses of

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going low is dependent on the present count in the counter's register. I mean the time of
the logical 1 pulse.

For example, suppose to get an output frequency of 1,000 Hz ( Hertz ), the period would
be 1 / 1,000 s = 1 ms ( millisecond ) or 1,000 µs ( microseconds ). If an input clock of 1

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MHz ( Mega-Hertz ) were applied to the clock input of the counter #0, then the counter
#0 would need to be programmed to 1000 µs. This could be done in decimal or in BCD. (
The period of an input clock of 1 MHz is 1 / 1,000,000 = 1 µs. )

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The formula is: n=fi divided by fout.
fi = input clock frequency, fout = output frequency, n = value to be loaded.

My example: fi = 1 MHz = 1 x 106 Hz, fout = 1 kHz = 1 x 103 Hz.

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n = 1 x 106 Hz / 1 x 103 Hz = 1 x 103 = 1,000. This is the decimal value to be loaded or
the hexadecimal value $03E8. The following program example uses the decimal load
count.
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B000 3E35 LD A,$35 ; load control word
; for counter 0 mode 2
B002 3207E0 LD ($E007),A ; into port $E007
; for BCD count
B005 2104E0 LD HL,$E004 ; address to the port
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; of counter 0
B008 3E00 LD A,$00
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B00A 77 LD (HL),A ; load least significant

; byte of 1000 first
B00B 3E10 LD A,$10
B00D 77 LD (HL),A ; load most significant
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; byte of 1000 last

B00E 3E01 LD A,1
B010 3208E0 LD ($E008),A ; start counter 0 is only
; necessary for the MZ-700.
; Not necessary for
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; counter #1 and #2
;
; The counter is now initialized and the output frequency
; will be 1000 Hz if the input frequency is 1 MHz.

If the count is loaded between output pulses, the present period will not be affected. A
new period will occur during the next count sequence.

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Mode Square Wave Generator
3

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Mode 3 is similar to the mode 2 except that the output will be high for half the period
and low for half. If the count is odd, the output will be high for ( n + 1 ) / 2 and low for (
n - 1 ) / 2 counts.

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For example, I'll setup counter #0 for a square wave frequency of 10 kHz ( kilo-Hertz ),
assuming the input frequency is 1 MHz.

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Please refer to the formula described at mode 2.
1 x 106 / 10 x 103 = 100. This is the decimal value to be loaded or the hexadecimal value
$0064. The following program example uses the binary load count.

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B000 3E35 LD A,$36 ; load control word
; for counter 0 mode 3
B002 3207E0 LD ($E007),A ; into port $E007
; for binary count
B005 2104E0 LD HL,$E004 ; address to the port
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; of counter 0
B008 3E00 LD A,$64 ; equals to
; 100 microseconds
; for 10,000 Hz
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B00A 77 LD (HL),A ; load least significant
; byte of $0064 first
B00B 3E10 LD A,$00
B00D 77 LD (HL),A ; load most significant
; nyte of $0064 last
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B00E 3E01 LD A,1

B010 3208E0 LD ($E008),A ; start counter 0 is only
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; necessary for the MZ-700.

; Not necessary for counter
; #1 and #2
;
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; The counter is now initialized and the output frequency

; will be 10 kHz if the input frequency is 1 MHz.
Mode Software Triggered Strobe
4
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In this mode the programmer can set up the counter to give an output timeout starting
when the register is loaded. On the terminal count, when the counter equals to 0, the
output will go to a logical 0 for one clock period and then returns to a logical 1. First the
mode is set, the output will be a logical 1.
Mode Hardware Triggered Strobe
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In this mode the rising edge of the trigger input will start the counting of the counter. The

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output goes low for one clock at the terminal count. The counter is retriggerable, thus
meaning that if the trigger input is taken low and then high during a count sequence, the

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sequence will start over.

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When the external trigger input goes to a logical 1, the timer will start to time out. If the
external trigger occurs again, prior to the time completing a full timeout, the timer will
retrigger.

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4.5 8279 Display and Keyboard Controller
8279 is a programmable display and keyboard controller. Intel 8279 chips are part of
many standard microprocessor kits that schools use and also of a variety of industrial
applications
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with small amounts of data I/O. The device is well suited for driving seven or eighteen segment
display units and for interfacing matrix keyboards. Dedicated peripheral for display and
keyboard control will free the processors in the host machines from a variety of chores
Basics of Keyboard Interfacing Matrix keyboards are connected in a series of rows and columns
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as shown in the material. The important tasks in interfacing a keyboard are 1) detecting a
keypress, 2) debounce the keypress and 3) encode the key to some standard code. Refer to Pages
281-285 for general introduction to keyboard interfacing. Pay particular attention to the matrix
keyboard layout and the flowchart in the material. Understand how the rows are selectively
pulled down and how the columns are checked to detect the keys. Two definitions are important
for keyboard interfacing. They pertain to detecting multi- ple simultaneous inputs. In 2-Key
Lockout mechanism, one key must be released before the other key is detected. In the N-Key
Rollover mode, if two keys are pressed almost simultaneously, both keypresses are detected and
are placed in a queue.

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Basics of Alphanumeric Displays

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8279 can be used to control a variety of display units. In this project, 8279 is used to drive LED

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displays only. In a multi-character LED display, the data inputs are sent on a common bus, but
different positions are selectively turned on in sequence. The refresh is done fast enough to hide
the multiplexing. This allows the display unit to have very few data lines coming in and also
reduces power consumption. For a multiplexed display, timing the character position that is
displayed is very critical. 8279 takes care of this timing. Basics of 8279 Programming

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• 8279 has two internal addresses which are memory mapped in the host CPU. The input line A0
selects one of these two addresses. If A0=„1‟, the control and status registers in the 8279 are
chosen. If A0=„0‟, 8279 is enabled for reading data from it or writing data to it.

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• When control/status is chosen, the device takes in control words. The first 3 bits
of the 8-bit control word identify the operation or the mode that is chosen. Rest
of the bits are interpreted according to the mode. The material given has detailed
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descriptions on how to interpret the control word.
8279 - Internal Block Diagram Internal organization of 8279 is shown in Figure . The
device runs internally at 100 kHz. Since the CLK input is at 3 MHz, the clock has to be divided
inside to 100 kHz. For doing so, proper Program Clock Word must be sent to the device and then
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the device is ready for Data I/O. The block diagram shows all the internal blocks for both
keyboard and display control.

1. Display is achieved using 1) the internal 16×8 Display RAM, 2) the Timing control unit
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and 3) the Scan Counter. CPU fills the display RAM with data. The data must be in seven
segment format. The scan counter counts from “0000” to “1111” and places its output on the line
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SL3-SL0. Based on the scan count generated, the Decoder shown in Figure 1 selectively turns
one of the sixteen characters in the display unit. The timing control for the display is done by the
signal BD. The characters are displayed from digit 1 to 16 and then returns back to 1. The time
8279 takes between two updates to the same digit position is called the scan time.
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2. The 16 character keyboard is organized as a 4×4 matrix keyboard. We use only

the last two bits of the scan counter, namely SL1 and SL0. Keyscan is achieved by driving one
row to „0‟ at a time and detecting for one of the columns being „0‟. If there is a key press,
the corresponding column goes low and the column information is passed on to 8279 through
the lines RL3-RL0. 8279 knows the row code that is being generated and we can scan lines
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RL3- RL0, effectively detecting the exact key that is pressed. After detecting a keypress, 8279
waits for a debounce time and scans the key again. If key press is still present, it produces a
8-bit keycode based on the column and the row in which the key is pressed. The keycode is
then placed in the internal 8-byte FIFO RAM. If a valid keypress is found, it asserts an
Interrupt Request to the CPU through the line IRQ. It is up to the CPU to read the data.
Meanwhile, 8279 increments FIFO count in the internal status register.

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3. In both cases, CPU communicates with the 8279 only when there is a character that needs
to be displayed or if a keypress is detected. For more details, consult the material given in the
class.

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4.6 8259A PROGRAMMABLE INTERRUPT C ONTROLLER (8259A/8259A-2)

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Features

Y 8086, 8088 Compatible

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Y MCS-80, MCS-85 ompatible
Y Eight-Level Priority Controller
Y Expandable to 64 Levels

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Y Programmable Interrupt Modes
Y Individual Request Mask Capability
Y Single a 5V Supply (No Clocks)
Y Available in 28-Pin DIP and 28-Lead PLCC Package
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4.6.1 FUNCTIONAL DESCRIPTION
Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority
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interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without
additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a
single a 5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead in handling multi-
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level priority inter- rupts. It has several modes, permitting optimization for a variety of
system requirements.
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The 8259A is fully upward compatible with the Intel 8259. Software originally written for
the 8259 will operate the 8259A in all 8259 equivalent modes (MCS-80/85, Non- Buffered,
Edge Triggered).
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Interrupts in Microcomputer Systems

Microcomputer system design requires that I.O de- vices such as keyboards, displays,
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sensors and oth- er components receive servicing in a an efficient manner so that large
amounts of the total system tasks can be assumed by the microcomputer with little or no
effect on throughput.
The most common method of servicing such devic- es is the Polled approach. This is
where the proces- sor must test each device in sequence and in effect „„ask‟‟ each one
if it needs servicing. It is easy to see that a large portion of the main program is looping
through this continuous polling cycle and that such a method would have a serious

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detrimental effect on system throughput, thus limiting the tasks that could be assumed by
the microcomputer and reducing the cost effectiveness of using such devices

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A more desirable method would be one that would allow the microprocessor to be
executing its main program and only stop to service peripheral devices when it is told to do

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so by the device itself. In effect, the method would provide an external asynchronous input
that would inform the processor that it should complete whatever instruction that
is currently being executed and fetch a new routine that will service the requesting
device. Once this servicing is com- plete, however, the processor would resume exactly

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where it left off.

This method is called Interrupt . It is easy to see that system throughput would drastically
increase, and thus more tasks could be assumed by the micro- computer to further
enhance its cost effectiveness.

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The Programmable Interrupt Controller (PIC) func- tions as an overall manager in an

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Interrupt-Driven system environment. It accepts requests from the peripheral equipment,

determines which of the in- coming requests is of the highest importance (priori- ty),
ascertains whether the incoming request has a higher priority value than
the level currently being serviced, and issues an interrupt to the CPU based on this
determination.
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Each peripheral device or structure usually has a special program or „„routine‟‟ that is
associated with its specific functional or operational requirements; this is referred to
as a „„service routine‟‟. The PIC, after issuing an Interrupt to the CPU, must somehow
input information into the CPU that can „„point‟‟ the Program Counter to the service
routine associated with the requesting device. This „„pointer‟‟ is an ad- dress in a
vectoring table and will often be referred to, in this document, as vectoring data.

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4.6.2 8259A Pin Configuration

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The 8259A is a device specifically designed for use in real time, interrupt driven

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microcomputer systems. It manages eight levels or requests and has built-in features for
expandability to other 8259A‟s (up to 64 levels). It is programmed by the system‟s
software as an I/O peripheral. A selection of priority modes is available to the programmer
so that the manner in which the requests are processed by the 8259A can

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be configured to match his system requirements. The priority modes can be changed or
reconfigured dynamically at any time during the main program. This means that the
complete interrupt structure can be defined as required, based on the total system
environment

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INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR)

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The interrupts at the IR input lines are handled by two registers in cascade, the
Interrupt Request Reg- ister (IRR) and the In-Service (ISR). The IRR is used to store all
the interrupt levels which are requesting service; and the ISR is used to store all the
interrupt levels which are being serviced.

PRIORITY RESOLVER

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This logic block determines the priorites of the bits set in the IRR. The highest
priority is selected and strobed into the corresponding bit of the ISR during INTA pulse.

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INTERRUPT MASK REGISTER (IMR)

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The IMR stores the bits which mask the interrupt lines to be masked. The IMR
operates on the IRR. Masking of a higher priority input will not affect the interrupt
request lines of lower quality.

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INT (INTERRUPT)

This output goes directly to the CPU interrupt input. The VOH level on this line is
designed to be fully compatible with the 8080A, 8085A and 8086 input levels.

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INTA (INTERRUPT ACKNOWLEDGE)

INTA pulses will cause the 8259A to release vector- ing information onto the data bus.
The format of this data depends on the system mode (mPM) of the
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DATA BUS BUFFER

This 3-state, bidirectional 8-bit buffer is used to inter- face the 8259A to the system Data
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Bus. Control words and status information are transferred through the Data
Bus Buffer.

READ/WRITE CONTROL LOGIC

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The function of this block is to accept OUTput com- mands from the CPU. It
contains the Initialization Command Word (ICW) registers and Operation Command
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Word (OCW) registers which store the various control formats for device operation.
This function block also allows the status of the 8259A to be transferred onto the Data
Bus.
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CS (CHIP SELECT)

A LOW on this input enables the 8259A. No reading or writing of the chip will occur
unless the device is selected.
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WR (WRITE)

A LOW on this input enables the CPU to write con- trol words (ICWs and OCWs) to the
8259A.

RD (READ)

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A LOW on this input enables the 8259A to send the status of the Interrupt Request
Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the
Interrupt level onto the Data Bus.

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A0

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This input signal is used in conjunction with WR and RD signals to write commands into
the various com- mand registers, as well as reading the various status registers of the chip.
This line can be tied directly to one of the address lines.

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THE CASCADE BUFFER/COMPARATOR

This function block stores and compares the IDs of all 8259A‟s used in the system.

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The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master
and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the
ID of the interrupting slave device onto the CAS0 – 2 lines. The slave thus
selected will send its preprogrammed subroutine address onto the Data Bus
during the next one or two consecutive INTA pulses. (See section „„Cascading the
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8259A‟‟.)

INTERRUPT SEQUENCE
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The powerful features of the 8259A in a microcom- puter system are its
programmability and the inter- rupt routine addressing capability. The latter allows
direct or indirect jumping to the specific interrupt rou- tine requested without any polling of
the interrupting devices. The normal sequence of events during an interrupt depends
on the type of CPU being used.
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The events occur as follows in an MCS-80/85 sys- tem:

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1. One or more of the INTERRUPT REQUEST lines (IR7 – 0) are raised high, setting
the correspond- ing IRR bit(s).
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2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.

3. The CPU acknowledges the INT and responds with an INTA pulse.

4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and
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the correspond- ing IRR bit is reset. The 8259A will also release a CALL instruction code
(11001101) onto the 8-bit Data Bus through its D7 – 0 pins.6.

5 . This CALL instruction will initiate two more INTA pulses to be sent to the 8259A
from the CPU group.
6 . These two INTA pulses allow the 8259A to re- lease its preprogrammed
subroutine address onto the Data Bus. The lower 8-bit address is re-leased at the first
INTA pulse and the higher 8-bit address is released at the second INTA pulse.

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7. This completes the 3-byte CALL instruction re- leased by the 8259A. In the AEOI
mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit
remains set until an appro- priate EOI command is issued at the end of the interrupt

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sequence.

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The events occuring in an 8086 system are the same until step 4.

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4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and the
correspond- ing IRR bit is reset. The 8259A does not drive the Data Bus during this
cycle.

5. The 8086 will initiate a second INTA pulse. Dur- ing this pulse, the 8259A releases

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an 8-bit pointer onto the Data Bus where it is read by the CPU.

6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the
end of the sec- ond INTA pulse. Otherwise, the ISR bit remains set until an
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appropriate EOI command is issued at the end of the interrupt subroutine.

If no interrupt request is present at step 4 of either sequence (i.e., the request was too
short in duration) the 8259A will issue an interrupt level 7. Both the vectoring bytes
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and the CAS lines will look like an interrupt level 7 was requested.

When the 8259A PIC receives an interrupt, INT be- comes active and an interrupt
acknowledge cycle is started. If a higher priority interrupt occurs between the two INTA
pulses, the INT line goes inactive im- mediately after the second INTA pulse. After an un-
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specified amount of time the INT line is activated again to signify the higher priority
interrupt waiti can vary between parts. The designer should be aware of this
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consideration when designing a sys- tem which uses the 8259A. It is recommended that
proper asynchronous design techniques be fol- lowed.

4.6.3 PROGRAMMING THE 8259A

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The 8259A accepts two types of command words generated by the CPU:

1. Initialization Command Words (ICWs): Before normal operation can begin, each
8259A in the system must be brought to a starting pointÐby a sequence of 2 to 4 bytes
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timed by WR pulses.

2. Operation Command Words (OCWs): These are the command words which
command the 8259A to operate in various interrupt modes. These modes are:

a. Fully nested mode

b. Rotating priority mode c. Special mask mode

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d. Polled mode

The OCWs can be written into the 8259A anytime after initialization.

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INITIALIZATION COMMAND WORDS (ICWS)

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General

Whenever a command is issued with A0 e 0 and D4 e 1, this is interpreted as

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Initialization Command Word 1 (ICW1). ICW1 starts the intiitalization se- quence
during which the following automatically oc- cur.

a. The edge sense circuit is reset, which means that following initialization, an interrupt
request (IR) in- put must make a low-to-high transistion to gener- ate an interrupt.

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b. The Interrupt Mask Register is cleared. c. IR7 input is assigned priority 7. d.

The slave mode address is set to 7. no

e. Special Mask Mode is cleared and Status Read is set to IRR.

f. If IC4 e 0, then all functions selected in ICW4 are set to zero. (Non-Buffered
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mode*, no Auto- EOI, MCS-80, 85 system).

*NOTE:

Master/Slave in ICW4 is only used in the buffered mode.

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Initialization Command Words 1 and 2 (ICW1, ICW2)

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A5 – A15: Page starting address of service routines . In an MCS 80/85 system, the 8
request levels will generate CALLs to 8 locations equally spaced in memory. These can
be programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8 rou- tines
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will occupy a page of 32 or 64 bytes, respec- tively.

The address format is 2 bytes long (A0 – A15). When the routine interval is 4, A0 – A4
are automatically in- serted by the 8259A, while A5 – A15 are programmed externally.
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When the routine interval is 8, A0 – A5 are automatically inserted by the 8259A, while
A6 – A15 are programmed externally.

The 8-byte interval will maintain compatibility with current software, while the 4-byte
interval is best for a compact jump table.

In an 8086 system A15 – A11 are inserted in the five most significant bits of the
vectoring byte and the

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8259A sets the three least significant bits according to the interrupt level. A10 – A5 are
ignored and ADI (Address interval) has no effect.

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LTIM: If LTIM e 1, then the 8259A will operate in the level interrupt mode. Edge
detect logic on the interrupt inputs will be disabled.

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ADI: CALL address interval. ADI e 1 then inter- val e 4; ADI e 0 then interval
e 8.

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SNGL: Single. Means that this is the only 8259A in the system. If SNGL e 1 no
ICW3 will be issued.

IC4: If this bit is setÐICW4 has to be read. If

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ICW4 is not needed, set IC4 e 0.

Initialization Command Word 3 (ICW3)

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This word is read only when there is more than one

8259A in the system and cascading is used, in which case SNGL e 0. It will load the 8- bit
slave register. The functions of this register are:
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a. In the master mode (either when SP e 1, or in buffered mode when M/S e 1 in

ICW4) a „„1‟‟ is set for each slave in the system. The master then will release byte 1 of the
call sequence (for MCS-
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80/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for
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8086 only byte

2) through the cascade lines.

b. In the slave mode (either when SP e 0, or if BUF e 1 and M/S e 0 in ICW4) bits
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2 – 0 identify the slave. The slave compares its cascade input with these bits and, if they
are equal, bytes 2 and 3 of the call sequence (or just byte 2 for 8086) are released by it
on the Data Bus.
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Initialization Command Word 4 (ICW4)

SFNM: If SFNM e 1 the special fully nested mode is programmed.

BUF: If BUF e 1 the buffered mode is pro- grammed. In buffered mode

SP/EN be- comes an enable output and the master/ slave determination is by M/S.

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M/S: If buffered mode is selected: M/S e 1 means the 8259A is programmed
to be a

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master, M/S e 0 means the 8259A is pro- grammed to be a slave. If BUF e 0,
M/S has no function.

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AEOI: If AEOI e 1 the automatic end of interrupt mode is programmed.

mPM: Microprocessor mode: mPM e 0 sets the

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8259A for MCS-80, 85 system operation, mPM e 1 sets the 8259A for 8086 system
operation.

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4.7 Programmable DMA Controller Core

The C8237 Programmable DMA Controller core (C8237 core) is a peripheral interface
circuit for microprocessor systems. The core is designed for use with an external, 8-bit address
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latch. It contains four independent channels and may be expanded to any number or channels by
cascading additional controller chips. Each channel has a full 64K address and word count
capability.

4.7.1 Features
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Enable/Disable control of individual DMA requests

Four, independent DMA channels
Independent auto-initialization of all channels
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Memory-to-Memory transfers
Memory block initialization
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Address increment or decrement

Directly expandable to any number of channels
End of process input for terminating transfers
Software DMA requests
Independent polarity control for DREQ and DACK signals
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The C8237 was developed in HDL and synthesizes to approximately 5,500 gates
depending on the technology used
Functionality based on the Intel 8237
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Applications

The C8237 core is designed to improve system performance by allowing external devices to
directly transfer information from the system memory.

Symbol Diagram

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4.7.2 Functional Description

The C8237 core is partitioned into modules as shown in the block diagram and described below:
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TIMING & C ONTROL
It generates internal timing and external control signals for the C8237. The timing Control block
derives internal timing from the clock input. The C8237 operates in two major cycles, idle cycle
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(Si) and Active cycle (S0, S1, S2, S3, and S4). Memory-to-memory transfers require a read-from
and a write-to-memory to complete each transfer. It requires eight states for a single transfer. The
first four states (S11, S12, S13, S14) are used for the read-from-memory half and the last four
states (S21, S22, S23, S24) for the write-to-memory half of the transfer. Each state is composed
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of one full clock period

FIXED P RIORITY & R OTATING P RIORITY LOGIC
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The Fixed Priority fixes the channels in priority order based upon the descending value of their
number. The lowest priority channel is 3 and the highest priority channel is 0.
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With Rotating Priority, the last channel to get service becomes the lowest priority channel with
the others rotating accordingly.

C8237 R EGISTERS
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The C8237 contains 344 bits of internal memory in the form of registers. CSN must be low when
the microprocessor is attempting to write or read the internal registers of the C8237.

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Block
Diagram

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C OMMAND R EGISTER

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Write Command Register Command:

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A3 A2 A1 A0 IORN IOWN

1 0 0 0 1 0

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This 8-bit register controls the operation of the C8237. It is programmed by the
microprocessor and is cleared by Reset or a Master Clear instruction.

D7 D6 D5 D4 D3 D2 D1 D0

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Bit0:
0 -> Memory-to-memory disable
1 -> Memory-to-memory enable
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0 -> Channel 0 address hold disable
Bit1: 1 -> Channel 0 address hold enable
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X -> if bit0 = 0

0 -> Controller enable

Bit2:
1 -> Controller disable
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0 -> Normal timing

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Bit3: 1 -> Compressed timing

X -> if bit 0 = 1

0 -> Fixed priority

Bit4:
1 -> Rotating priority
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0 -> Late write

Bit5: 1 -> Extended write
X -> if bit3 = 1
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0 -> DREQ sense active high

Bit6:
1 -> DREQ sense active low

0 -> DACK sense active low

Bit7:
1 -> DACK sense active high

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MODE R EGISTER

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Write Mode Register Command:

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A3 A2 A1 A0 IORN IOWN

1 0 1 1 1 0

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Each channel has a 6-bit Mode register. It is programmed by the microprocessor.

D7 D6 D5 D4 D3 D2 D1 D0

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Bit1 & Bit0:
00 -> Channel 0
01 -> Channel 1
10 -> Channel 2
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11 -> Channel 3
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00 -> Verify transfer (pseudo transfer)
01 -> Write transfer (from I/O to the memory)
Bit3 & Bit2: 10 -> Read transfer (from the memory to I/O)
11 -> Illegal
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XX -> if bits 6 and 7 = 11

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0 -> Auto initialization disable

Bit4:
1 -> Auto initialization enable

0 -> Address increment select

Bit5:
1 -> Address decrement select
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00 -> Demand mode

01 -> Single mode
Bit7 & Bit6:
10 -> Block mode
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11 -> Cascade mode

Demand Transfer Mode: The device will continue making transfers until a TC or external EOPN
is encountered or until DREQ goes inactive.

Single Transfer Mode: The device makes one transfer only. DREQ must be held active until
DACK becomes active in order to be recognized.

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Block Transfer Mode: The device is active by DREQ or software request to continue making
transfers during the service until a TC or an external EOPN is encountered. DREQ need only be
held active until DACK becomes active.

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Cascade Transfer Mode: This mode is used to cascade more than one C8237 together for simple

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system expansion. The ready input is ignored in this cascade transfer mode.

R EQUEST R EGISTER

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Write Request Register Command:

A3 A2 A1 A0 IORN IOWN

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1 0 0 1 1 0

Each channel has a request bit associated with it in the 4-bit Request register. These are non-
maskable and subject to prioritization by the Priority Encoder. Each register bit is set or reset
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separately under software control or is cleared upon generation of a TC or external EOPN. The
entire reg-ister is cleared by a Reset. In order to make a software request, the channel must be in
Block Mode.
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X X X X X D2 D1 D0
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00 -> Channel 0
01 -> Channel 1
Bit1 & Bit0:
10 -> Channel 2
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11 -> Channel 3

0 -> Reset request bit

Bit2:
1 -> Set request bit
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MASK R EGISTER
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Each channel has a mask bit associated with it which can be set to disable the incoming DREQ.
Each mask bit is set when its associated channel produces an EOPN if the channel is not
programmed for Auto initialize. Each bit of the 4-bit Mask register may also be set or cleared
separately under software control. The entire register is also set by a Reset. This disables all
DMA requests until a clear Mask register instruction allows them to occur.

P ROGRAMMING A LL MASK R EGISTER B ITS:

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Write All Mask Register Bits Command:

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A3 A2 A1 A0 IORN IOWN

1 1 1 1 1 0

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X X X X X D2 D1 D0

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00 -> Channel 0
01 -> Channel 1
Bit1 & Bit0:
10 -> Channel 2
11 -> Channel 3

Bit2:
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0 -> Clear mask bit
1 -> Set mask bit
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P ROGRAMMING S INGLE MASK R EGISTER B ITS:

Write Single Mask Register Bit Command:

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A3 A2 A1 A0 IORN IOWN
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1 0 1 0 1 0

X X X X D3 D2 D1 D0
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0 -> Clear channel 0 mask bit

Bit0:
1 -> Set channel 0 mask bit

0 -> Clear channel 1 mask bit

Bit1:
1 -> Set channel 1 mask bit

Bit2: 0 -> Clear channel 2-mask bit

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1 -> Set channel 2 mask bit

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0 -> Clear channel 3-mask bit
Bit3:
1 -> Set channel 3 mask bit

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S TATUS R EGISTER

Read Status Register Command:

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A3 A2 A1 A0 IORN IOWN

1 0 0 0 0 1

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This register is available to be read out of the C8237 by the microprocessor. It contains
information about the status of the devices at this point. Bits 0-3 are set when that channel
reaches a TC or an external EOPN is applied. These bits are cleared upon Reset and on each
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Status Read. Bits 4-7 are set whenever their corresponding channel is requesting.

D7 D6 D5 D4 D3 D2 D1 D0
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Bit0: 1 -> Channel 0 has reached TC

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Bit1: 1 -> Channel 1 has reached TC

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Bit2: 1 -> Channel 2 has reached TC

Bit3: 1 -> Channel 3 has reached TC

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Bit4: 1 -> Channel 0 request

Bit5: 1 -> Channel 1 request

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Bit6: 1 -> Channel 2 request

Bit7: 1 -> Channel 3 request

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TEMPORARY R EGISTER

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Read Temporary Register Command:

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A3 A2 A1 A0 IORN IOWN

1 1 0 1 0 1

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This register is used to hold data during memory-to-memory transfers. Following the completion
of the transfers, the last word moved can be read by the microprocessor. The temporary register
is cleared by a Reset.

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C URRENT ADDRESS R EGISTER

Each channel has a 16-bit Current Address register. This register holds the value of the address
used during DMA transfers. The address is automatically incremented or decremented after each
transfer and the intermediate values of the address are stored in the Current Address register
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during the transfer. This register is written or read by the microprocessor.

C URRENT W ORD R EGISTER

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Each channel has a 16-bit Current Word Count register. This register determines the number of
transfers to be per-formed. The word count is decremented after each transfer. When the value in
the register goes from zero to FFFFH, a TC will be generated. This register is loaded or read by
the microprocessor in the Program Condition.
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BASE ADDRESS AND BASE W ORD C OUNT R EGISTERS

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Each channel has a 16-bit Base Address and 16-bit Base Word Count register. These registers
store the original value, which will be loaded to current registers during Auto initialize.

W ORD C OUNT AND ADDRESS R EGISTER C OMMAND C ODES

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Write -> CSN = 0, IORN = 1 and IOWN = 0

Read -> CSN = 0, IORN = 0 and IOWN = 1
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Register A3 A2 A1 A0 FF DB0-DB7

CH 0 0 A0-A7
Base and 0 0 0 0
Current Address 1 A8-A15

CH 0 0 0 0 1 0 W0-W7

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Base and Current Word Count 1 W8-W15

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CH 1 0 A0-A7
Base and 0 0 1 0
Current Address 1 A8-A15

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0 W0-W7
CH 1
0 0 1 1
Base and Current Word Count
1 W8-W15

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CH 2 0 A0-A7
Base and 0 1 0 0
Current Address 1 A8-A15

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0 W0-W7
CH 2
0 1 0 1
Base and Current Word Count
1 W8-W15

CH 3
Base and 0
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1 1 0
0 A0-A7

Current Address 1 A8-A15

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0 W0-W7
CH 3
0 1 1 1
Base and Current Word Count
1 W8-W15
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S OFTWARE C OMMANDS
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These three commands do not depend on any specific bit pattern on the data bus.

C LEAR FIRST/LAST F LIP -FLOP C OMMAND:

A3 A2 A1 A0 IORN IOWN
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1 1 0 0 1 0
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This command must be executed prior to writing or reading new address or word count
information to the C8237.

MASTER C LEAR C OMMAND:

A3 A2 A1 A0 IORN IOWN

1 1 0 1 1 0

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This command has the same effect as the hardware Reset. The Command, Status, Request,
Temporary, and Internal First/Last Flip-Flop registers are cleared and the Mask register is set.
The C8237 will be in the idle cycle.

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C LEAR MASK R EGISTER C OMMAND:

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A3 A2 A1 A0 IORN IOWN

1 1 1 0 1 0

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This command clears the mask bits of all four channels, enabling them to accept DMA requests.

TEMPORARY W ORD C OUNT R EGISTER (16 BIT DECREMENTOR )

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It will decrement the word count after each transfer. When the value in the register goes from
zero to FFFFH, a Terminal Count (TC) will be generated.

TEMPORARY ADDRESS R EGISTER (16 B IT INCREMENTOR /DECREMENTOR )

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Base on the mode of the address, the address will be decremented or incremented after each
transfer. And the intermediate values of the address are stored in the Current Address register
during the transfer.
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4.8 Application of 8085

4.8.1 “STEPPERMOTORINTERFACE”USING8085MICROPROCESSOR
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DESCRIPTION:
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The stepper motors have immense applications in printing, Industrial Robotics, Precision
tool motions in drilling, cutting and shaping machines, lathe etc.

This project is proposed to demonstrate interfacing of stepper motor to 8085

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microprocessor and to run it in continuous or stepped motion in forward or reverse direction

under program control, using 8085 microprocessor.
HARDWARE DESCRIPTION:
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The hardware setup consists of a microprocessor motherboard and stepper motor

interface board. The motherboard consists of 8085 MPU, 8KB EPROM, 8KB RAM, Keyboard
and display controller 8279, 21-key Hex-keypad and six numbers of seven segment LEDs and
Bus Expansion connector. The stepper motor interface consists of driver transistors for stepper
motor windings and address decoding circuit. The microprocessor output the binary sequence
through data bus, which are converted to current pulses by the driver transistors and used to drive
stepper motor. The software for the system is developed in 8085 assembly language.

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Address
AD -AD
0 7 / Transistor
LATCH Address

50 Pin Expansion Connector

/ CS
8085 7

Stepper
D -D

Connector
7
0

A -A
EPROM D -D

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0 3

0
System bus M

RAM 8279
no LED indication for
output binary
Displa
Keyboard
C D E F int
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8 9 A B Go
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Fig1. Block diagram of stepper motor interface

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STEPPER MOTOR INTERFACING WITH 8085

MVI A, 80H
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OUT 43H
MVI A,88H
loop: OUT 40H
CALL delay
RRC
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JMP loop
delay: PUSH PSW
LXI H,0001H
delay20:LXI D,FFFF
delay10:DCX D
MOV A,D
DRA E
JNZ delay10

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DCX H
MOV A,H
ORA L

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JNZ delay20
POP PSW

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RET

4.8.2 TEMPERATURE CONTROLLER USING 8085 MICROPROCESSOR

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DESCRIPTION:
Industrial and control application/may require automation of the process such as
temperature, pressure, liquid flow, etc., in order to minimize manual intervention. To automate

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any application an intelligent processor plays a major role. One such processor proposed for the
project is 8085, an 8-bit microprocessor.
The temperature controller can be used to control the temperature of any plant. Typically
it contains a Processor unit, Temperature input unit and Control output unit. The 8085 based
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motherboard forms the processing unit. The Analog-to-Digital unit together with temperature
sensor forms the temperature input unit. The relay driver forms the control output unit. Electric
power to the heating element (coil) is supplied through relay contacts. The switching ON/OFF
of the relay controls the heat supplied to the plant.
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Temp MPU Control

output Plant
Input
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Simple schematic of temperature controller

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Operationally, the system requires two set points-upper and lower, to be entered by the
user. Whenever the temperature of the plant exceeds the upper limit or recede the lower limit
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relay is turned-off, so that a temperature is maintained within limits. The software for the
temperature controller is developed in 8085 assembly language programs.

HARDWARE DESCRIPTION:

The hardware consists of 8085 microprocessor motherboard, ADC interface board,

and relay and driver unit.

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The motherboard consists of 8085 MPU, 8KB EPROM, 8KB RAM keyboard and display
controller 8279, programmable peripheral interface 8255, 21 key hex-keypad and six numbers of
seven segment LED‟s. Ports Expansion connector parallel port connectors are provided for

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external interfacing.

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The temperature input board or ADC interface board consists of ADC 0809, which is an
8-bit converter with eight channels of input. It is interfaced with the motherboard through 50-pin
bus expansion connector. The temperature sensor ADC590 is used to sense the temperature of
the plant and its analog output is applied to the channel-0 of ADC.

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Relay is switched ON/OFF by driving the transistor to saturation/cut-off which is
connected to port A of 8255.

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+V
26 pin connector

driver
Parallel port

8255 8085 LATCH

PPI CPU
AD TEMPERATURE
NC no 590 SENSOR

50 pin Expansion connector

SYSTEM ADC
P
INTERFAC
BUS E
BOARD
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EPROM RAM 8279

8KB 8KB KEYBOARD
DISPLAY
DISPLAY
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C D E F int
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8 9 A B

4 5 6 7 Nxt
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0 1 2 3 Sub

KEYBOARD
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QUESTION BANK

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UNIT – IV
I/O INTERFACING

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PART – A (2 MARKS)

1. What is meant by i/p port and o/p port?

2. Compare I/o mapped I/o memory mapped I/o
3. Illustrates the different modes of operation in 8255.

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4. List the features of 8251.
5. What is the internal operating frequency of 8259 and How can you derive it from the
clock signal?
6. What is the function of GATE signal in 8254 timer?

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7. What is the format of KWI in 8259?
8. What is difference between programmable internal timers 8253 / 54?
9. Give the control format of 8253 / 54.
10. What is the need of DMA in microprocessor?
11. Explain the different types of DMA transfer.
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12. Write the features of mode 0 in 8255?
13. What are the features of mode 1 in 8255?
14. What are the signals used in input control signal & Output control signal?
15. What are the features used mode 2 in 8255?
16. What are the features of operations used in 8253?
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17. What are the different types of Write operations used in 8253?
18. Give the different types of command words used in 8259a?
19. Give the operating modes of 8259a.
20. What are the output modes used in 8279?
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PART – B (16 MARKS)

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1. Draw the block diagram of 8279 and explain the functions of each. (16)
2. With the help of neat diagram explain how 8251 is interfaced with 8085 and used for
serial communication. (16)
3. Discuss the silent feature of 8259 and explain the block diagram of 8259 programmable
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interrupts controllers. (16)

4 a) Describe the various modes of operation in 8253 programmable internal
timer. (08)
b) Explain the operation of DMA controller 8237. (08)
5 a) Draw and explain the interfacing of cascaded 8259 with 8086. (10)
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b) Explain in detail about the modes of operation in 8255. (06)

6. Draw the pin diagram of 8257 programmable DMA controller and explain the
function of each pin in detail. (16)
7. Discuss the various operating modes of 8253 timer with necessary control
Words. (16)

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UNIT V MICROCONTROLLERS

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5.1 Architecture and programming of 8051 MCU's

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Microcontroller manufacturers have been competing for a long time for attracting choosy
customers and every couple of days a new chip with a higher operating frequency, more memory
and upgraded A/D converters appeared on the market.

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However, most of them had the same or at least very similar architecture known in the world of
microcontrollers as “8051 compatible”. What is all this about? The whole story has its
beginnings in the far 80s when Intel launched the first series of microcontrollers called the MCS
051. Even though these microcontrollers had quite modest features in comparison to the new
ones, they conquered the world very soon and became a standard for what nowadays is called the

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microcontroller.

The main reason for their great success and popularity is a skillfully chosen configuration which
satisfies different needs of a large number of users allowing at the same time constant expansions
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(refers to the new types of microcontrollers). Besides, the software has been developed in great
extend in the meantime, and it simply was not profitable to change anything in the
microcontroller‟s basic core. This is the reason for having a great number of various
microcontrollers which basically are solely upgraded versions of the 8051 family. What makes
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this microcontroller so special and universal so that almost all manufacturers all over the world
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As seen in figure above, the 8051 microcontroller has nothing impressive in appearance:
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4 Kb of ROM is not much at all.

128b of RAM (including SFRs) satisfies the user's basic needs.
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4 ports having in total of 32 input/output lines are in most cases sufficient to make all
necessary connections to peripheral environment.

The whole configuration is obviously thought of as to satisfy the needs of most programmers
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working on development of automation devices. One of its advantages is that nothing is missing
and nothing is too much. In other words, it is created exactly in accordance to the average user„s
taste and needs. Another advantages are RAM organization, the operation of Central Processor
Unit (CPU) and ports which completely use all recourses and enable further upgrade.
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5.2 Pinout Description
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Pins 1-8: Port 1 Each of these pins can be configured as an input or an output.

Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most
registers. In other words, the positive voltage on this pin resets the microcontroller. By applying
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logic zero to this pin, the program starts execution from the beginning.
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Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions:

Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication
output.
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Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication
clock output.
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Pin 12: INT0 Interrupt 0 input.

Pin 13: INT1 Interrupt 1 input.

Pin 14: T0 Counter 0 clock input.

Pin 15: T1 Counter 1 clock input.

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Pin 16: WR Write to external (additional) RAM.

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Pin 17: RD Read from external RAM.

Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which specifies

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operating frequency is usually connected to these pins. Instead of it, miniature ceramics
resonators can also be used for frequency stability. Later versions of microcontrollers operate at
a frequency of 0 Hz up to over 50 Hz.

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Pin 20: GND Ground.

Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher address byte,

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i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is
not used, which means that not all eight port bits are used for its addressing, the rest of them are
not available as inputs/outputs.
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Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it
every time the microcontroller reads a byte from memory.

Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address
byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the
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external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and
uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous
logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by
means of only one additional (and cheap) integrated circuit. In other words, this port is used for
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both data and address transmission.

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Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address
transmission with no regard to whether there is internal memory or not. It means that even there
is a program written to the microcontroller, it will not be executed. Instead, the program written
to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will
use both memories, first internal then external (if exists).
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Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as general
inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is
driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0).
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Pin 40: VCC +5V power supply.

5.3 input / Output Ports (I/O Ports)

All 8051 microcontrollers have 4 I/O ports each comprising 8 bits which can be configured as
inputs or outputs. Accordingly, in total of 32 input/output pins enabling the microcontroller to be
connected to peripheral devices are available for use.

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Pin configuration, i.e. whether it is to be configured as an input (1) or an output (0), depends on
its logic state. In order to configure a microcontroller pin as an input, it is necessary to apply a
logic zero (0) to appropriate I/O port bit. In this case, voltage level on appropriate pin will be 0.

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Similarly, in order to configure a microcontroller pin as an input, it is necessary to apply a logic

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one (1) to appropriate port. In this case, voltage level on appropriate pin will be 5V (as is the
case with any TTL input). This may seem confusing but don't loose your patience. It all becomes
clear after studying simple electronic circuits connected to an I/O pin.

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Input/Output (I/O) pin
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Figure above illustrates a simplified schematic of all circuits within the microcontroler connected
one of its pins. It refers to all the pins except those of the P0 port which do not have pull-up
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resistors built-in.
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Output pin
A logic zero (0) is applied to a bit of the P register. The output FE transistor is turned on, thus
connecting the appropriate pin to ground.

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Input pin
A logic one (1) is applied to a bit of the P register. The output FE transistor is turned off and the
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appropriate pin remains connected to the power supply voltage over a pull-up resistor of high
resistance.

Logic state (voltage) of any pin can be changed or read at any moment. A logic zero (0) and
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logic one (1) are not equal. A logic one (0) represents a short circuit to ground. Such a pin acts as
an output.

A logic one (1) is “loosely” connected to the power supply voltage over a resistor of high
resistance. Since this voltage can be easily “reduced” by an external signal, such a pin acts as an
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input.
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Port 0

The P0 port is characterized by two functions. If external memory is used then the lower address
byte (addresses A0-A7) is applied on it. Otherwise, all bits of this port are configured as
inputs/outputs.

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The other function is expressed when it is configured as an output. Unlike other ports consisting
of pins with built-in pull-up resistor connected by its end to 5 V power supply, pins of this port
have this resistor left out. This apparently small difference has its consequences:

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If any pin of this port is configured as an input then it acts as if it “floats”. Such an input has

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unlimited input resistance and indetermined potential.

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When the pin is configured as an output, it acts as an “open drain”. By applying logic 0 to a port
bit, the appropriate pin will be connected to ground (0V). By applying logic 1, the external
output will keep on “floating”. In order to apply logic 1 (5V) on this output pin, it is necessary to
built in an external pull-up resistor.
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Port 1
P1 is a true I/O port, because it doesn't have any alternative functions as is the case with P0, but
can be cofigured as general I/O only. It has a pull-up resistor built-in and is completely
compatible with TTL circuits.
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Port 2

P2 acts similarly to P0 when external memory is used. Pins of this port occupy addresses
intended for external memory chip. This time it is about the higher address byte with addresses
A8-A15. When no memory is added, this port can be used as a general input/output port showing
features similar to P1.

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Port 3

All port pins can be used as general I/O, but they also have an alternative function. In order to

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use these alternative functions, a logic one (1) must be applied to appropriate bit of the P3
register. In terms of hardware, this port is similar to P0, with the difference that its pins have a

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pull-up resistor built-in.

5.4 Memory Organization

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The 8051 has two types of memory and these are Program Memory and Data Memory. Program
Memory (ROM) is used to permanently save the program being executed, while Data Memory
(RAM) is used for temporarily storing data and intermediate results created and used during the
operation of the microcontroller. Depending on the model in use (we are still talking about the
8051 microcontroller family in general) at most a few Kb of ROM and 128 or 256 bytes of RAM

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is used. However…

All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64 kb
memory. It is neither a mistake nor a big ambition of engineers who were working on basic core
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development. It is a matter of smart memory organization which makes these microcontrollers a
real “programmers‟ goody“.

Program Memory
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The first models of the 8051 microcontroller family did not have internal program memory. It
was added as an external separate chip. These models are recognizable by their label beginning
with 803 (for example 8031 or 8032). All later models have a few Kbyte ROM embedded. Even
though such an amount of memory is sufficient for writing most of the programs, there are
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situations when it is necessary to use additional memory as well. A typical example are so called
lookup tables. They are used in cases when equations describing some processes are too
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complicated or when there is no time for solving them. In such cases all necessary estimates and
approximates are executed in advance and the final results are put in the tables (similar to
logarithmic tables).
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How does the microcontroller handle external memory depends on the EA pin logic state:

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EA=0 In this case, the microcontroller completely ignores internal program memory and
executes only the program stored in external memory.

EA=1 In this case, the microcontroller executes first the program from built-in ROM, then the
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program stored in external memory.

In both cases, P0 and P2 are not available for use since being used for data and address
transmission. Besides, the ALE and PSEN pins are also used.
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Data Memory

As already mentioned, Data Memory is used for temporarily storing data and intermediate results
created and used during the operation of the microcontroller. Besides, RAM memory built in the
8051 family includes many registers such as hardware counters and timers, input/output ports,
serial data buffers etc. The previous models had 256 RAM locations, while for the later models
this number was incremented by additional 128 registers. However, the first 256 memory
locations (addresses 0-FFh) are the heart of memory common to all the models belonging to the

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8051 family. Locations available to the user occupy memory space with addresses 0-7Fh, i.e.
first 128 registers. This part of RAM is divided in several blocks.

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The first block consists of 4 banks each including 8 registers denoted by R0-R7. Prior to
accessing any of these registers, it is necessary to select the bank containing it. The next memory

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block (address 20h-2Fh) is bit- addressable, which means that each bit has its own address (0-
7Fh). Since there are 16 such registers, this block contains in total of 128 bits with separate
addresses (address of bit 0 of the 20h byte is 0, while address of bit 7 of the 2Fh byte is 7Fh).
The third group of registers occupy addresses 2Fh-7Fh, i.e. 80 locations, and does not have any

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special functions or features.

Additional RAM

In order to satisfy the programmers‟ constant hunger for Data Memory, the manufacturers

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decided to embed an additional memory block of 128 locations into the latest versions of the
8051 microcontrollers. However, it‟s not as simple as it seems to be… The problem is that
electronics performing addressing has 1 byte (8 bits) on disposal and is capable of reaching only
the first 256 locations, therefore. In order to keep already existing 8-bit architecture and
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compatibility with other existing models a small trick was done.

What does it mean? It means that additional memory block shares the same addresses with
locations intended for the SFRs (80h- FFh). In order to differentiate between these two
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physically separated memory spaces, different ways of addressing are used. The SFRs memory
locations are accessed by direct addressing, while additional RAM memory locations are
accessed by indirect addressing.
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Memory expansion

In case memory (RAM or ROM) built in the microcontroller is not sufficient, it is possible to add

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two external memory chips with capacity of 64Kb each. P2 and P3 I/O ports are used for their
addressing and data transmission.

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From the user‟s point of view, everything works quite simply when properly connected because
most operations are performed by the microcontroller itself. The 8051 microcontroller has two
pins for data read RD#(P3.7) and PSEN#. The first one is used for reading data from external

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data memory (RAM), while the other is used for reading data from external program memory
(ROM). Both pins are active low. A typical example of memory expansion by adding RAM and
ROM chips (Hardward architecture), is shown in figure above.

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Even though additional memory is rarely used with the latest versions of the microcontrollers,

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we will describe in short what happens when memory chips are connected according to the
previous schematic. The whole process described below is performed automatically.

When the program during execution encounters an instruction which resides in

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external memory (ROM), the microcontroller will activate its control output ALE and set
the first
8 bits of address (A0-A7) on P0. IC circuit 74HCT573 passes the first 8 bits to memory
address pins.
A signal on the ALE pin latches the IC circuit 74HCT573 and immediately afterwards 8

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higher bits of address (A8-A15) appear on the port. In this way, a desired location of
additional program memory is addressed. It is left over to read its content.
Port P0 pins are configured as inputs, the PSEN pin is activated and the
microcontroller reads from memory chip.
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Similar occurs when it is necessary to read location from external RAM. Addressing is
performed in the same way, while read and write are performed via signals appearing on the
control outputs RD (is short for read) or WR (is short for write).
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5.5 Counters and Timers

As you already know, the microcontroller oscillator uses quartz crystal for its operation. As the
frequency of this oscillator is precisely defined and very stable, pulses it generates are always of
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the same width, which makes them ideal for time measurement. Such crystals are also used in
quartz watches. In order to measure time between two events it is sufficient to count up pulses
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coming from this oscillator. That is exactly what the timer does. If the timer is properly
programmed, the value stored in its register will be incremented (or decremented) with each
coming pulse, i.e. once per each machine cycle. A single machine-cycle instruction lasts for 12
quartz oscillator periods, which means that by embedding quartz with oscillator frequency of
12MHz, a number stored in the timer register will be changed million times per second, i.e. each
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microsecond.

The 8051 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their
main purpose is to measure time and count external events. Besides, they can be used for
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generating clock pulses to be used in serial communication, so called Baud Rate.

Timer T0
As seen in figure below, the timer T0 consists of two registers – TH0 and TL0 representing a low
and a high byte of one 16-digit binary number.

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Accordingly, if the content of the timer T0 is equal to 0 (T0=0) then both registers it consists of
will contain 0. If the timer contains for example number 1000 (decimal), then the TH0 register
(high byte) will contain the number 3, while the TL0 register (low byte) will contain decimal

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number 232.

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Formula used to calculate values in these two registers is very simple:

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TH0 × 256 + TL0 = T

Matching the previous example it would be as follows:
3 × 256 + 232 =
1000
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Since the timer T0 is virtually 16-bit register, the largest value it can store is 65 535. In case of
exceeding this value, the timer will be automatically cleared and counting starts from 0. This
condition is called an overflow. Two registers TMOD and TCON are closely connected to this
timer and control its operation.

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TMOD Register (Timer Mode)

The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure

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below, the low 4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to
the timer 1. There are 4 operational modes and each of them is described herein.

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Bits of this register have the following function:

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GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin
(P3.3):
o 1 - Timer 1 operates only if the INT1 bit is set.
o 0 - Timer 1 operates regardless of the logic state of the INT1 bit.
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C/T1 selects pulses to be counted up by the timer/counter 1:
o 1 - Timer counts pulses brought to the T1 pin (P3.5).
o 0 - Timer counts pulses from internal oscillator.
T1M1,T1M0 These two bits select the operational mode of the Timer 1.
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T1M1 T1M0 Mode Description

0 0 0 13-bit timer
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0 1 1 16-bit timer
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1 0 2 8-bit auto-reload

1 1 3 Split mode
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GATE0 enables and disables Timer 1 using a signal brought to the INT0 pin (P3.2):
o 1 - Timer 0 operates only if the INT0 bit is set.
o 0 - Timer 0 operates regardless of the logic state of the INT0 bit.
C/T0 selects pulses to be counted up by the timer/counter 0:
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o 1 - Timer counts pulses brought to the T0 pin (P3.4).

o 0 - Timer counts pulses from internal oscillator.
T0M1,T0M0 These two bits select the oprtaional mode of the Timer 0.

T0M1 T0M0 Mode Description

0 0 0 13-bit timer

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0 1 1 16-bit timer

1 0 2 8-bit auto-reload

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1 1 3 Split mode

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Timer 0 in mode 0 (13-bit timer)

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This is one of the rarities being kept only for the purpose of compatibility with the previuos
versions of microcontrollers. This mode configures timer 0 as a 13-bit timer which consists of all
8 bits of TH0 and the lower 5 bits of TL0. As a result, the Timer 0 uses only 13 of 16 bits. How
does it operate? Each coming pulse causes the lower register bits to change their states. After
receiving 32 pulses, this register is loaded and automatically cleared, while the higher byte (TH0)

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is incremented by 1. This process is repeated until registers count up 8192 pulses. After that,
both registers are cleared and counting starts from 0.

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Timer 0 in mode 1 (16-bit timer)

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Mode 1 configures timer 0 as a 16-bit timer comprising all the bits of both registers TH0 and
TL0. That's why this is one of the most commonly used modes. Timer operates in the same way
as in mode 0, with difference that the registers count up to 65 536 as allowable by the 16 bits.

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Timer 0 in mode 2 (Auto-Reload Timer)

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Mode 2 configures timer 0 as an 8-bit timer. Actually, timer 0 uses only one 8-bit register for
counting and never counts from 0, but from an arbitrary value (0-255) stored in another (TH0)
register.
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The following example shows the advantages of this mode. Suppose it is necessary to constantly
count up 55 pulses generated by the clock.
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If mode 1 or mode 0 is used, It is necessary to write the number 200 to the timer registers and
constantly check whether an overflow has occured, i.e. whether they reached the value 255.
When it happens, it is necessary to rewrite the number 200 and repeat the whole procedure. The
same procedure is automatically performed by the microcontroller if set in mode 2. In fact, only
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the TL0 register operates as a timer, while another (TH0) register stores the value from which the
counting starts. When the TL0 register is loaded, instead of being cleared, the contents of TH0
will be reloaded to it. Referring to the previous example, in order to register each 55th pulse, the
best solution is to write the number 200 to the TH0 register and configure the timer to operate in
mode 2.

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Timer 0 in Mode 3 (Split Timer)

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Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. In
other words, the 16-bit timer consisting of two registers TH0 and TL0 is split into two
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independent 8-bit timers. This mode is provided for applications requiring an additional 8-bit
timer or counter. The TL0 timer turns into timer 0, while the TH0 timer turns into timer 1. In
addition, all the control bits of 16-bit Timer 1 (consisting of the TH1 and TL1 register), now
control the 8-bit Timer 1. Even though the 16-bit Timer 1 can still be configured to operate in
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any of modes (mode 1, 2 or 3), it is no longer possible to disable it as there is no control bit to do
it. Thus, its operation is restricted when timer 0 is in mode 3.
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The only application of this mode is when two timers are used and the 16-bit Timer 1 the
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operation of which is out of control is used as a baud rate generator.

Timer Control (TCON) Register

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TCON register is also one of the registers whose bits are directly in control of timer operation.
Only 4 bits of this register are used for this purpose, while rest of them is used for interrupt
control to be discussed later.
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TF1 bit is automatically set on the Timer 1 overflow.

TR1 bit enables the Timer 1.
o 1 - Timer 1 is enabled.

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o 0 - Timer 1 is disabled.
TF0 bit is automatically set on the Timer 0 overflow.
TR0 bit enables the timer 0.

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o 1 - Timer 0 is enabled.
o 0 - Timer 0 is disabled.

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How to use the Timer 0 ?

In order to use timer 0, it is first necessary to select it and configure the mode of its operation.

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Bits of the TMOD register are in control of it:

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Referring to figure above, the timer 0 operates in mode 1 and counts pulses generated by internal
clock the frequency of which is equal to 1/12 the quartz frequency.
Turn on the timer:
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The TR0 bit is set and the timer starts operation. If the quartz crystal with frequency of 12MHz is
embedded then its contents will be incremented every microsecond. After 65.536 microseconds,
the both registers the timer consists of will be loaded. The microcontroller automatically clears
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them and the timer keeps on repeating procedure from the beginning until the TR0 bit value is
logic zero (0).

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How to 'read' a timer?
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Depending on application, it is necessary either to read a number stored in the timer registers or
to register the moment they have been cleared.
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- It is extremely simple to read a timer by using only one register configured in mode 2 or 3. It is
sufficient to read its state at any moment. That's all!

- It is somehow complicated to read a timer configured to operate in mode 2. Suppose the lower
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byte is read first (TL0), then the higher byte (TH0). The result is:
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TH0 = 15 TL0 = 255

Everything seems to be ok, but the current state of the register at the moment of reading was:
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TH0 = 14 TL0 = 255

In case of negligence, such an error in counting (255 pulses) may occur for not so obvious but
quite logical reason. The lower byte is correctly read (255), but at the moment the program
counter was about to read the higher byte TH0, an overflow occurred and the contents of both
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registers have been changed (TH0: 14→15, TL0: 255→0). This problem has a simple solution.
The higher byte should be read first, then the lower byte and once again the higher byte. If the
number stored in the higher byte is different then this sequence should be repeated. It's about a
short loop consisting of only 3 instructions in the program.There is another solution as well. It is
sufficient to simply turn the timer off while reading is going on (the TR0 bit of the TCON
register should be cleared), and turn it on again after reading is finished.

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Timer 0 Overflow Detection

Usually, there is no need to constantly read timer registers. It is sufficient to register the moment

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they are cleared, i.e. when counting starts from 0. This condition is called an overflow. When it
occurrs, the TF0 bit of the TCON register will be automatically set. The state of this bit can be

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constantly checked from within the program or by enabling an interrupt which will stop the main
program execution when this bit is set. Suppose it is necessary to provide a program delay of
0.05 seconds (50 000 machine cycles), i.e. time when the program seems to be stopped:

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First a number to be written to the timer registers should be calculated:

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Then it should be written to the timer registers TH0 and TL0:

When enabled, the timer will resume counting from this number. The state of the TF0 bit, i.e.
whether it is set, is checked from within the program. It happens at the moment of overflow, i.e.
after exactly 50.000 machine cycles or 0.05 seconds.

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How to measure pulse duration?

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Suppose it is necessary to measure the duration of an operation, for example how long a device
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has been turned on? Look again at the figure illustrating the timer and pay attention to the
function of the GATE0 bit of the TMOD register. If it is cleared then the state of the P3.2 pin
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doesn't affect timer operation. If GATE0 = 1 the timer will operate until the pin P3.2 is cleared.
Accordingly, if this pin is supplied with 5V through some external switch at the moment the
device is being turned on, the timer will measure duration of its operation, which actually was
the objective.
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How to count up pulses?

Similarly to the previous example, the answer to this question again lies in the TCON register.
This time it's about the C/T0 bit. If the bit is cleared the timer counts pulses generated by the
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internal oscillator, i.e. measures the time passed. If the bit is set, the timer input is provided with
pulses from the P3.4 pin (T0). Since these pulses are not always of the same width, the timer
cannot be used for time measurement and is turned into a counter, therefore. The highest
frequency that could be measured by such a counter is 1/24 frequency of used quartz-crystal.

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Timer 1

imer 1 is identical to timer 0, except for mode 3 which is a hold-count mode. It means that they

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have the same function, their operation is controlled by the same registers TMOD and TCON
and both of them can operate in one out of 4 different modes.

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Timer 1 is identical to timer 0, except for mode 3 which is a hold-count mode. It means that they
have the same function, their operation is controlled by the same registers TMOD and TCON
and both of them can operate in one out of 4 different
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modes.
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5.6 UART (Universal Asynchronous Receiver and Transmitter)

One of the microcontroller features making it so powerful is an integrated UART, better known
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as a serial port. It is a full-duplex port, thus being able to transmit and receive data
simultaneously and at different baud rates. Without it, serial data send and receive would be an
enormously complicated part of the program in which the pin state is constantly changed and
checked at regular intervals. When using UART, all the programmer has to do is to simply select
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serial port mode and baud rate. When it's done, serial data transmit is nothing but writing to the
SBUF register, while data receive represents reading the same register. The microcontroller takes
care of not making any error during data transmission.
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Serial port must be configured prior to being used. In other words, it is necessary to determine
how many bits is contained in one serial “word”, baud rate and synchronization clock source.
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The whole process is in control of the bits of the SCON register (Serial Control).

Serial Port Control (SCON) Register

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SM0 - Serial port mode bit 0 is used for serial port mode selection.
SM1 - Serial port mode bit 1.

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SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit.
When set, it enables multiprocessor communication in mode 2 and 3, and eventually
mode 1. It should be cleared in mode 0.

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REN - Reception Enable bit enables serial reception when set. When cleared, serial
reception is disabled.

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TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem
of transmiting the 9th bit in modes 2 and 3. It is set to transmit a logic 1 in the 9th bit.
RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if
9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.

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TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte
is sent. It's a signal to the processor that the line is available for a new byte transmite. It
must be cleared from within the software.
RI - Receive Interrupt flag is automatically set upon one byte receive. It signals that
byte is received and should be read quickly prior to being replaced by a new data. This

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bit is also cleared from within the software.

As seen, serial port mode is selected by combining the SM0 and SM2 bits:

SM0 SM1 Mode Description

no Baud Rate

0 0 0 8-bit Shift Register 1/12 the quartz frequency

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0 1 1 8-bit UART Determined by the timer 1

1 0 2 9-bit UART 1/32 the quartz frequency (1/64 the quartz frequency)

1 1 3 9-bit UART Determined by the timer 1

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In mode 0, serial data are transmitted and received through the RXD pin, while the TXD pin
output clocks. The bout rate is fixed at 1/12 the oscillator frequency. On transmit, the least
significant bit (LSB bit) is sent/received first.

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TRANSMIT - Data transmit is initiated by writing data to the SBUF register. In fact, this process

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starts after any instruction being performed upon this register. When all 8 bits have been sent, the
TI bit of the SCON register is automatically set.

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RECEIVE - Data receive through the RXD pin starts upon the two following conditions are met:
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bit REN=1 and RI=0 (both of them are stored in the SCON register). When all 8 bits have been
received, the RI bit of the SCON register is automatically set indicating that one byte receive is
complete.
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Since there are no START and STOP bits or any other bit except data sent from the SBUF
register in the pulse sequence, this mode is mainly used when the distance between devices is
short, noise is minimized and operating speed is of importance. A typical example is I/O port
expansion by adding a cheap IC (shift registers 74HC595, 74HC597 and similar).

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Mode 1

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In mode 1, 10 bits are transmitted through the TXD pin or received through the RXD pin in the
following manner: a START bit (always 0), 8 data bits (LSB first) and a STOP bit (always 1).
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The START bit is only used to initiate data receive, while the STOP bit is automatically written
to the RB8 bit of the SCON register.

TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data
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transmission is indicated by setting the TI bit of the SCON register.

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RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The following
two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the SCON
register. The RI bit is automatically set upon data reception is complete.

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The Baud rate in this mode is determined by the timer 1 overflow.

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Mode 2

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In mode 2, 11 bits are transmitted through the TXD pin or received through the RXD pin: a
START bit (always 0), 8 data bits (LSB first), a programmable 9th data bit and a STOP bit
(always 1). On transmit, the 9th data bit is actually the TB8 bit of the SCON register. This bit
usually has a function of parity bit. On receive, the 9th data bit goes into the RB8 bit of the same
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register (SCON).The baud rate is either 1/32 or 1/64 the oscillator frequency.

TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data
transmission is indicated by setting the TI bit of the SCON register.

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RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The following
two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the SCON
register. The RI bit is automatically set upon data reception is complete.

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Mode 3

Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is
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variable.
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The parity bit is the P bit of the PSW register. The simplest way to check correctness of the
received byte is to add a parity bit to it. Simply, before initiating data transmit, the byte to
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transmit is stored in the accumulator and the P bit goes into the TB8 bit in order to be “a part of
the message”. The procedure is opposite on receive, received byte is stored in the accumulator
and the P bit is compared with the RB8 bit. If they are the same- everything is OK!
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Baud Rate

Baud Rate is a number of sent/received bits per second. In case the UART is used, baud rate
depends on: selected mode, oscillator frequency and in some cases on the state of the SMOD bit
of the SCON register. All the necessary formulas are specified in the table:

Baud Rate BitSMOD

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Mode 0 Fosc. / 12

1 Fosc.

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Mode 1 BitSMOD
16 12 (256-TH1)

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Fosc. / 32 1
Mode 2
Fosc. / 64 0

1 Fosc.
Mode 3

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16 12 (256-TH1)

Timer 1 as a clock generator

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Timer 1 is usually used as a clock generator as it enables various baud rates to be easily set. The
whole procedure is simple and is as follows:

First, enable Timer 1 overflow interrupt.

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Configure Timer T1 to operate in auto-reload mode.
Depending on needs, select one of the standard values from the table and write it to the
TH1 register. That's all.

Fosc. (MHz)
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Baud Rate Bit SMOD
11.0592 12 14.7456 16 20

150 40 h 30 h 00 h 0
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300 A0 h 98 h 80 h 75 h 52 h 0
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600 D0 h CC h C0 h BB h A9 h 0

1200 E8 h E6 h E0 h DE h D5 h 0
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2400 F4 h F3 h F0 h EF h EA h 0

4800 F3 h EF h EF h 1

4800 FA h F8 h F5 h 0
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9600 FD h FC h 0

9600 F5 h 1

19200 FD h FC h 1

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38400 FE h 1

76800 FF h 1

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Multiprocessor Communication

As you may know, additional 9th data bit is a part of message in mode 2 and 3. It can be used for
checking data via parity bit. Another useful application of this bit is in communication between

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two or more microcontrollers, i.e. multiprocessor communication. This feature is enabled by
setting the SM2 bit of the SCON register. As a result, after receiving the STOP bit, indicating
end of the message, the serial port interrupt will be generated only if the bit RB8 = 1 (the 9th bit).

This is how it looks like in practice:

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Suppose there are several microcontrollers sharing the same interface. Each of them has its own
address. An address byte differs from a data byte because it has the 9th bit set (1), while this bit
is cleared (0) in a data byte. When the microcontroller A (master) wants to transmit a block of
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data to one of several slaves, it first sends out an address byte which identifies the target slave.
An address byte will generate an interrupt in all slaves so that they can examine the received byte
and check whether it matches their address.
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Of course, only one of them will match the address and immediately clear the SM2 bit of the
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SCON register and prepare to receive the data byte to come. Other slaves not being addressed
leave their SM2 bit set ignoring the coming data bytes.

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5.7 8051 Microcontroller Interrupts

There are five interrupt sources for the 8051, which means that they can recognize 5
different events that can interrupt regular program execution. Each interrupt can be enabled or
disabled by setting bits of the IE register. Likewise, the whole interrupt system can be disabled
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by clearing the EA bit of the same register. Refer to figure below.

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Now, it is necessary to explain a few details referring to external interrupts- INT0 and
INT1. If the IT0 and IT1 bits of the TCON register are set, an interrupt will be generated on high
to low transition, i.e. on the falling pulse edge (only in that moment). If these bits are cleared, an
interrupt will be continuously executed as far as the pins are held low.
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IE Register (Interrupt Enable)

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EA - global interrupt enable/disable:

o 0 - disables all interrupt requests.
o 1 - enables all individual interrupt requests.
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ES - enables or disables serial interrupt:

o 0 - UART system cannot generate an interrupt.
o 1 - UART system enables an interrupt.
ET1 - bit enables or disables Timer 1 interrupt:
o 0 - Timer 1 cannot generate an interrupt.
o 1 - Timer 1 enables an interrupt.
EX1 - bit enables or disables external 1 interrupt:
o 0 - change of the pin INT0 logic state cannot generate an interrupt.
o 1 - enables an external interrupt on the pin INT0 state change.

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ET0 - bit enables or disables timer 0 interrupt:
o 0 - Timer 0 cannot generate an interrupt.
o 1 - enables timer 0 interrupt.

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EX0 - bit enables or disables external 0 interrupt:
o 0 - change of the INT1 pin logic state cannot generate an interrupt.

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o 1 - enables an external interrupt on the pin INT1 state change.

Interrupt Priorities

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It is not possible to forseen when an interrupt request will arrive. If several interrupts are
enabled, it may happen that while one of them is in progress, another one is requested. In order
that the microcontroller knows whether to continue operation or meet a new interrupt request,
there is a priority list instructing it what to do.

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The priority list offers 3 levels of interrupt priority:

1. Reset! The apsolute master. When a reset request arrives, everything is stopped and the
microcontroller restarts. no
2. Interrupt priority 1 can be disabled by Reset only.
3. Interrupt priority 0 can be disabled by both Reset and interrupt priority 1.

The IP Register (Interrupt Priority Register) specifies which one of existing interrupt sources
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have higher and which one has lower priority. Interrupt priority is usually specified at the
beginning of the program. According to that, there are several possibilities:

If an interrupt of higher priority arrives while an interrupt is in progress, it will

be immediately stopped and the higher priority interrupt will be executed first.
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If two interrupt requests, at different priority levels, arrive at the same time then
the higher priority interrupt is serviced first.
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If the both interrupt requests, at the same priority level, occur one after another, the
one which came later has to wait until routine being in progress ends.
If two interrupt requests of equal priority arrive at the same time then the interrupt to
be serviced is selected according to the following priority list:
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1. External interrupt INT0

2. Timer 0 interrupt
3. External Interrupt INT1
4. Timer 1 interrupt
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5. Serial Communication Interrupt

IP Register (Interrupt Priority)

The IP register bits specify the priority level of each interrupt (high or low priority).

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PS - Serial Port Interrupt priority bit
o Priority 0
o Priority 1

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PT1 - Timer 1 interrupt priority
o Priority 0
o Priority 1
PX1 - External Interrupt INT1 priority

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o Priority 0
o Priority 1
PT0 - Timer 0 Interrupt Priority
o Priority 0
o Priority 1 no
PX0 - External Interrupt INT0 Priority
o Priority 0
o Priority 1
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Handling Interrupt

When an interrupt request arrives the following occurs:

1. Instruction in progress is ended.

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2. The address of the next instruction to execute is pushed on the stack.

3. Depending on which interrupt is requested, one of 5 vectors (addresses) is written to the
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program counter in accordance to the table below:

4.

Interrupt Source Vector (address)

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IE0 3h

TF0 Bh
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TF1 1B h

RI, TI 23 h

All addresses are in hexadecimal format

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5. These addresses store appropriate subroutines processing interrupts. Instead of them,
there are usually jump instructions specifying locations on which these subroutines
reside.

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6. When an interrupt routine is executed, the address of the next instruction to execute is
poped from the stack to the program counter and interrupted program resumes operation

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from where it left off.

s.
From the moment an interrupt is enabled, the microcontroller is on alert all the time. When an
interrupt request arrives, the program execution is stopped, electronics recognizes the source and
the program “jumps” to the appropriate address (see the table above). This address usually stores
a jump instruction specifying the start of appropriate subroutine. Upon its execution, the program
resumes operation from where it left off.

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Reset

Reset occurs when the RS pin is supplied with a positive pulse in duration of at least 2 machine
no
cycles (24 clock cycles of crystal oscillator). After that, the microcontroller generates an internal
reset signal which clears all SFRs, except SBUF registers, Stack Pointer and ports (the state of
the first two ports is not defined, while FF value is written to the ports configuring all their pins
as inputs). Depending on surrounding and purpose of device, the RS pin is usually connected to a
power-on reset push button or circuit or to both of them. Figure below illustrates one of the
ar
simplest circuit providing safe power-on reset.
t
5s
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Basically, everything is very simple: after turning the power on, electrical capacitor is being
charged for several milliseconds through a resistor connected to the ground. The pin is driven
high during this process. When the capacitor is charged, power supply voltage is already stable

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and the pin remains connected to the ground, thus providing normal operation of the
microcontroller. Pressing the reset button causes the capacitor to be temporarily discharged and

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the microcontroller is reset. When released, the whole process is repeated…

Through the program- step by step...

s.
Microcontrollers normally operate at very high speed. The use of 12 Mhz quartz crystal enables
1.000.000 instructions to be executed per second. Basically, there is no need for higher operating
rate. In case it is needed, it is easy to built in a crystal for high frequency. The problem arises
when it is necessary to slow down the operation of the microcontroller. For example during
testing in real environment when it is necessary to execute several instructions step by step in

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order to check I/O pins' logic state.

Interrupt system of the 8051 microcontroller practically stops operation of the microcontroller
and enables instructions to be executed one after another by pressing the button. Two interrupt
no
features enable that:

Interrupt request is ignored if an interrupt of the same priority level is in progress.

Upon interrupt routine execution, a new interrupt is not executed until at least one
instruction from the main program is executed.
ar

In order to use this in practice, the following steps should be done:

1. External interrupt sensitive to the signal level should be enabled (for example INT0).
t

2. Three following instructions should be inserted into the program (at the 03hex. address):
5s
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What is going on? As soon as the P3.2 pin is cleared (for example, by pressing the button), the
microcontroller will stop program execution and jump to the 03hex address will be executed.
This address stores a short interrupt routine consisting of 3 instructions.

The first instruction is executed until the push button is realised (logic one (1) on the P3.2 pin).
The second instruction is executed until the push button is pressed again. Immediately after that,
the RETI instruction is executed and the processor resumes operation of the main program. Upon

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execution of any program instruction, the interrupt INT0 is generated and the whole procedure is
repeated (push button is still pressed). In other words, one button press - one instruction.

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5.8 INTERFACING OF 8051 WITH IO DEVICES

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5.8.1 Interfacing the Keyboard to 8051 microcontroller

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The contents of the counter is then compared and displayed in the display. This display is
designed using a seven segment display and a BCD to seven segment decoder IC 7447.

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The BCD equivalent number of counter is sent through output part of 8051 displays the number
of pressed key.
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Circuit diagram of INTERFACING KEY BOARD TO 8051.

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The programming algorithm, program and the circuit diagram is as follows. Here program is
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explained with comments.

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Circuit diagram of INTERFACING KEY BOARD TO 8051.

Keyboard is organized in a matrix of rows and columns as shown in the figure. The microcontroller
accesses both rows and columns through the port.
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1. The 8051 has 4 I/O ports P0 to P3 each with 8 I/O pins, P0.0 to P0.7,P1.0 to P1.7, P2.0
to P2.7, P3.0 to P3.7. The one of the port P1 (it understood that P1 means P1.0 to
P1.7) as an I/P port for microcontroller 8051, port P0 as an O/P port of microcontroller
8051 and port P2 is used for displaying the number of pressed key.
t

2. Make all rows of port P0 high so that it gives high signal when key is pressed.
3. See if any key is pressed by scanning the port P1 by checking all columns for non
5s

zero condition.
4. If any key is pressed, to identify which key is pressed make one row high at a time.
5. Initiate a counter to hold the count so that each key is counted.
6. Check port P1 for nonzero condition. If any nonzero number is there in
[accumulator], start column scanning by following step 9.
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7. Otherwise make next row high in port P1.

8. Add a count of 08h to the counter to move to the next row by repeating steps from
step 6.
9. If any key pressed is found, the [accumulator] content is rotated right through the
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carry until carry bit sets, while doing this increment the count in the counter till carry
is found.
10. Move the content in the counter to display in data field or to memory location
11. To repeat the procedures go to step 2.

Program to interface matrix keyboard to microcontroller 8051

Start of main program:

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to check that whether any key is pressed

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start: mov a,#00h
mov p1,a ;making all rows of port p1 zero

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mov a,#0fh
mov p1,a ;making all rows of port p1 high
press: mov a,p2
jz press ;check until any key is pressed

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after making sure that any key is pressed

mov a,#01h ;make one row high at a time

te
mov r4,a
mov r3,#00h ;initiating counter
next: mov a,r4
mov p1,a ;making one row high at a time
mov a,p2 ;taking input from port A
no
jnz colscan ;after getting the row jump to check
column
mov a,r4
rl a ;rotate left to check next row
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mov r4,a
mov a,r3
add a,#08h ;increment counter by 08 count
mov r3,a
sjmp next ;jump to check next row
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after identifying the row to check the colomn following steps are followed
5s

colscan: mov r5,#00h

in: rrc a ;rotate right with carry until get the carry
jc out ;jump on getting carry
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inc r3 ;increment one count

jmp in
out: mov a,r3
da a ;decimal adjust the contents of counter
before display
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mov p2,a
jmp start ;repeat for check next key

5.8.2 LCD INTERFACING

UNDERSTANDING LCD

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Pinout

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• 8 data pins D7:D0

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Bi-directional data/command pins.
Alphanumeric characters are sent in ASCII format.

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• RS: Register Select
RS = 0 -> Command Register is selected
RS = 1 -> Data Register is selected

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• R/W: Read or Write
0 -> Write, 1 -> Read no
• E: Enable (Latch data)
Used to latch the data present on the data pins.
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A high-to-low edge is needed to latch the data.

• VEE : contrast control

t
5s

NOTE: When writing to the display, data is transferred only on the high to low transition of this
signal. However, when reading from the display, data will become available shortly after the low
to high transition and remain available until the signal falls low again.
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Registers

The HD44780 has two 8-bit registers, an instruction register (IR) and a data register (DR). The
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IR stores instruction codes. The DR temporarily stores data to be written into DDRAM or
CGRAM and temporarily stores data to be read from DDRAM or CGRAM. Data written into the
DR is automatically written into DDRAM or CGRAM by an internal operation. . These two
registers can be selected by the register selector (RS) signal. See the table below:

Register Selection

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RS R/W Operation
0 0 IR write as an internal operation (display clear, etc.)

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0 1 Read busy flag (DB7) and address counter (DB0 to DB6)

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1 0 DR write as an internal operation (DR to DDRAM or CGRAM)
1 1 DR read as an internal operation (DDRAM or CGRAM to DR)

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LCD Commands

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The LCD‟s internal controller accept several commands and modify the display accordingly.
These commands would be things like:
– Clear screen
– Return home
– Shift display right/left
no
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Instruction Decimal HEX

Function set (8-bit interface, 2 lines, 5*7 Pixels) 56 38
Function set (8-bit interface, 1 line, 5*7 Pixels) 48 30
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Function set (4-bit interface, 2 lines, 5*7 Pixels) 40 28

Function set (4-bit interface, 1 line, 5*7 Pixels) 32 20
5s

Entry mode set See Below See Below

Scroll display one character right (all lines) 28 1E
Scroll display one character left (all lines) 24 18
Home (move cursor to top/left character position) 2 2
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Move cursor one character left 16 10

Move cursor one character right 20 14
Turn on visible underline cursor 14 0E
Turn on visible blinking-block cursor 15 0F
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Make cursor invisible 12 0C

Blank the display (without clearing) 8 08
Restore the display (with cursor hidden) 12 0C
Clear Screen 1 01
Set cursor position (DDRAM address) 128 + addr 80+ addr
Set pointer in character-generator RAM (CG RAM address) 64 + addr 40+ addr

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INTERFACING LCD TO 8051

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The 44780 standard requires 3

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control lines as well as either 4 or 8
I/O lines for the data bus. The user
may select whether the LCD is to
operate with a 4-bit data bus or an

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8-bit data bus.

If a 4-bit data bus is used, the LCD

will require a total of 7 data lines.
If an 8-bit data bus is used, the LCD

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will require a total of 11 data lines.

The three control lines are EN, RS,

and RW. no
Note that the EN line must be raised/lowered before/after each instruction sent to the LCD
regardless of whether that instruction is read or write, text or instruction. In short, you must
always manipulate EN when communicating with the LCD. EN is the LCD's way of knowing
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that you are talking to it. If you don't raise/lower EN, the LCD doesn't know you're talking to it
on the other lines.

Checking the Busy Flag

t

You can use subroutine for checking busy flag or just a big (and safe) delay.
5s

1. Set R/W Pin of the LCD HIGH(read from the LCD)

2. Select the instruction register by setting RS pin LOW
3. Enable the LCD by Setting the enable pin HIGH
4. The most significant bit of the LCD data bus is the state of the busy flag(1=Busy,0=ready
w.

to accept instructions/data). The other bits hold the current value of the address counter.

If the LCD never come out from "busy" status because of some problems ,The program will
"hang," waiting for DB7 to go low. So in a real applications it would be wise to put some kind of
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time limit on the delay--for example, a maximum of 100 attempts to wait for the busy signal to
go low. This would guarantee that even if the LCD hardware fails, the program would not lock
up.

CODE EXAMPLE

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Busy flag checking
ready:
setb P1.7 ;D7 as input

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clr P3.6 ;RS=0 cmd
setb P3.5 ;RW=1 for read

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again:
setb P3.7 ;H->L pulse on E
clr P3.7

s.
jb P1.7, again
ret

Data write Routine

data:

te
mov P1, A ;move acc. data to port
setb P3.6 ;RS=1 data
clr P3.5 ;RW=0 for write
setb P3.7 ;H->L pulse on E no
clr P3.7
lcall ready
ret

Command write Routine

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command:
mov P1, A ;move acc. data to port
clr P3.6 ;RS=0 for cmd
clr P3.5 ;RW=0 for write
t

setb P3.7 ;H->L pulse on E

clr P3.7
5s

lcall ready
ret

Initialization
initialization:
w.

mov A, #38H ; Initialize, 2-lines, 5X7 matrix.

lcall Command
mov A, #0EH ; LCD on, cursor on
lcall Command
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mov A, #01H ; Clear LCD Screen

lcall Command
mov A, #06H ; Shift cursor right
lcall Command

Display clear

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clear:
setb p3.7 ;enable EN
clr 3.6 ;RS=0 for cmd.

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mov DATA,#01h
clr p3.7 ;disable EN

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lcall ready
RET

Note- As we need to clear the LCD frequently and not the whole initialisation , it is better to use

s.
this routine separately.

Displaying "HI"

lcall initialization

te
lcall clear
mov A,#'H'
acall data
mov A,#'I' no
lcall data

ASSEMBLY LANGUAGE
lcall Initialization
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lcall clear
mov a,#'H'
lcall data
mov a,#'I'
t

lcall data
5s

mov a,#8ah
lcall command

mov a,#'M'
w.

lcall data
mov a,#'A'
lcall data
mov a,#'H'
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lcall data
mov a,#'E'
lcall data
mov a,#'S'
lcall data
mov a,#'H'
lcall data

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5.8.3 ANALOG TO DIGITAL CONVERTION USING 8051

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Analog signals are very common inputs to embedded systems .Most transducers and
sensors such as temperature ,pressure ,velocity ,humidity are analog. Therefore we need to
convert these analog signals in to digital so that 8051 can read it.

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ABOUT IC

PinOut

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• CS – Chip Select , active low
• RD – Read Digital data from ADC, H-L edge triggered
• WR -- Start conversion, L-H pulse edge triggered
no
• INTR -- end of conversion, Goes low to indicate conversion done
• Data bits -- D0-D7
• CLK IN & CLK R
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– CLK IN is an input pin connected to an external clock source when an external clock is used
for timing. However, ADC804 has an internal clock
generator.
t

To use the internal clock generator of the ADC804, the CLK IN and CLK R pins are connected
5s

to a capacitor and a resistor. In that case, the

clock frequency is determined by the equation.
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f = 1/1.1RC
R=10K and C=150pF f=606Hz
the conversion time is 110us.
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Input Voltage range

Vref/2 Vin Step size
(Volts) (Volts) (mV)
Open (2.5) 0 to 5 5/256 = 19.53
2.56 0 to 5.12 5.12/256 =20

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• Default 0-5V. Can be changed by setting different 1.28 0 to 2.56 2.56/256 = 10
value for Vref/2 pin. 0.5 0 to 1 1/256=3.90

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Vin=Vin(+) – Vin (-)

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• Range = 0 to 2x Vref/2.
for Vin = 2x Vref/2. we get 256 as a digital output on D0-D7. (Refer Table)

s.
•Step Size a Smallest change
– (2 x Vref/2)/ 256 for ADC804
for eg for step size 10mv ,digital output on D0-D7 changes by one count for every 10mv change

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of the input analog voltage.

Data Out
Dout = Vin / Step Size
no
for input vtg. of 2.56 volts (Vref=1.28 volts) and stepsize of 10mv Dout =2560/10 =256 or FF
ar
that is full scale output.

Conversion Time
Greater than 110us for ADC804
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Resolution
5s

8 bits for ADC804

INTERFACING ADC804 TO 8051

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Signals to be interfaced (on the ADC804)

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– D0-D7, RD, WR, INTR, CS

Can do both Memory mapping and IO mapping

Memory Mapping (timing is critical)

– Connect D0-D7 of ADC804 to the data bus of the 8051 system

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– Connect RD, WR of the ADC804 to the 8051 system (ensure polarity)
– Connect CS of ADC804 to an appropriate address decoder output

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– Connect INTR of ADC804 to an external interrupt Pin on the 8051 (INT0 or INT1)

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IO Mapping (easiest - I prefer )
– Connect D0-D7, RD, WR, CS, INTR to some port bits on the 8051 (12 in all).

s.
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no
t ar

Algorithm
5s

• Make CS=0 and send a low-to-high to pin WR to start the conversion.

• Keep monitoring INTR
– If INTR =0, the conversion is finished and we can go to the next step.
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– If INTR=1, keep polling until it goes low.

• After INTR=0, we make CS=0 and send a high-to-low pulse to RD to get the data out of the
ADC804 chip.
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ASSEMBLY LANGUEGE (A51)

ADC_IO:

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mov P1, #0xff ; To configure as input

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AGAIN
clr p3.7 ;Chip select

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setb P3.6 ;RD=1
clr P3.5 ;WR=0
setb P3.5 ;WR=1- low to high transition

s.
WAIT:
jb P3.4, WAIT ;wait for INTR
clr p3.7 ;generate cs to ADC

te
clr P3.6 ;RD=0 -High to low transition
mov A, P1 ;read digital o/p

INTERFACING ADC804 TO 8051

no
ADC808/809 Chip with 8 analog channel.
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This means this kind of chip allows to
monitor 8 different transducers.
• ADC804 has only ONE analog input:
t

Vin(+).
• ALE: Latch in the address
5s

• Start : Start of conversion (same as WR

in 804)
• OE: output enable (same as RD in 804)
w.

• EOC: End of Conversion (same as INTR

in 804)
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Algorithm

Notice that the ADC808/809 that there is

no self-clocking and the clock must be provided from an external source to the CLK pin. (you
can use programmable clock oscillator to enable or disable clock by programmable bit. )

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• Select an analog channel by provide bits to A, B, C.
• Enable clock

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• Activate ALE with a low-to-high pulse.

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• Activate SC with a high-to-low pulse (start conversion) The conversion is begun on the falling
edge of the start conversion pulse. you can use circuit like
• Monitor EOC Pin .After conversion this pin goes high.

s.
• Activate OE with a high-to-low pulse to read data out of the ADC chip.

DIGITAL TO ANALOG CONVERTER - DAC

te
Commonly used DAC808 (MC1408)
– R/2R ladder
– Iout = Iref (D7/2 + D6/4 + D5/8 + …… + D0/256)
no
– Iout converted to voltage by a resistive load or op-amp based isolator (Rf from Vout to V- and
V+ to GND)
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PinOut
– D0-D7 à Connected to the Processor‟s IO port
t

– Vref+, Vref-, Vee

5s

Usage:
– Just write a byte to the IO port and the DAC converts it to an
analog value
w.

Some 8051 clones have ADCs and DACs in built

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QUESTION BANK

UNIT – V

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MICROCONTOLLERS

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PART – A (2 MARKS)

1. What is microcontroller?
2. What is the difference between the microprocessor and microcontrollers?

s.
3. List the features of 8051 microcontrollers.
4. State the various modes available for timer in 8051.
5. List the interrupts of 8051 microcontroller?
6. What are the register banks in 8051 microcontroller?
7. Draw and explain the bit pattern of TMOD register.

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8. What are the types of addressing modes in the 8051?
9. Write the DJNZ instructions of intel 8051 microcontroller?
10. State the function of RS1 and RS0 bits in the flag register of Intel 8051.
11. Write the function of the pins PSEN and EA of 8051.
12. Define 16-bit registers DPTR and SP of 8051.
no
13. Name the special functions of registers available in 8051.
14. Write the register IE format of 8051.
15. List the five interrupt sources of 8051.
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PART – B (16 MARKS)

1. With the necessary diagram of control word format and explain the various
Operating modes of timer in 8051 microcontroller. (16)
2. With the help of neat diagram and explain the memory organization of 8051
t

Microcontroller. (16)
3. Give the details of pin diagram of 8051. (16)
5s

4. a) Explain the interrupt structure of 8051. (08)

b) Explain the memory structure of 8051. (08)
5. Explain the instruction set of 8051 with an example. (16)
6. a) Draw and explain the interfacing keyboard with 8051. (08)
b) Describe the interfacing LCD with 8051. (08)
w.

7. a)Describe with necessary diagram of interfacing A/D converter with 8051. (08)
b) Draw and explain the interfacing D/A converter with 8051. (08)
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co
s.
te
no
t ar
5s
w.
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ANNA UNIVERSITY MODEL QUESTION PAPERS
B.E/B.TECH DEGREE EXAMINATION, NOV/DEC 2006

m
FIFTH SEMESTER COMPUTER SCIENCE AND ENGINEERING

co
CS 1304- MICROPROCESSOR AND MICROCONTROLLERS
(REGULATION 2004)
TIME: THREE HOURS MAXIMUM : 100 MARKS
Answer all the questions

s.
PART A (10*2=20)

te
1.Name the various flag bits available in an 8085 microprocessor.
2.Give the significance of SIM and RIM instructions available in 8085.
3.What do you mean by pipelining in an 8086 processor?
4.How the 20 bit effective address is calculated in an 8086 processor?
5.What is the purpose of CLK signal in an 8086 system?
no
6.What is the use of latch signal on the AD0- AD15 bus in an 8086 system?
7.Name the two models used by DMA processor to transfer data.
8.Name the six modes of operation of an 8253 programmable interval timer.
9.Differentiate a microprocessor and a microcontroller.
ar
10.Differentiate RRA and RRCA instructions in 8051 microcontroller.

PART-B- (5*16=80)
t

11.(a) (i) with a neat block diagram explain the architecture of an 8085 microprocessor?
5s

(12)
(ii) list out the maskable and non-maskable interrupts available in an 8085 processor?
(4)
Or
(b) (i) how do the instructions of 8085 is classified based on their functions and word
w.

length? Give an example.

(10)
(ii) write an ALP to add two 8 bit numbers.
(6)
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12 (a) (i). with a neat sketch explain the architecture of an 8086 processor.
(12)
(ii). Give the significance of O flag, T flag and I flag, D flag of 8086.
(4)
Or
(b) (i). explain on detail about the various addressing modes used in 8086 processor ?
give an example.
(12)

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(ii) name the various segment registers and their usage in 8086 processor.
(4)
13. (a) (i) explain the MIN/MAX mode of operation of an 8086 processor

m
(10)
(ii) give a note on the role of a decoder in memory interfacing with an example.

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(6)
Or
(b) (i) explain in detail about 8086 memory banks and the associated signals for byte and
word operations.

s.
(12)
(ii) give the significance of RQ/GTO and IO/M signals
(4)
14. (a) (i) with a neat sketch and explain the operation of an interrupt controller (8259)

te
(14)
(ii) what is the use of CAS0,CAS1 and CAS2 signals?
(2)
Or
no
(b) draw the block diagram of a DMA controller (8237) and explain its operation.
(16)
15 (a) with the help of a functional block diagram explain any one application of 8051
microcontroller.
ar
(16)
Or
(b) give the PIN details of an 8051 microcontroller and explain.
(16).
t
5s

B.E/B.TECH DEGREE EXAMINATION, NOV/DEC 2007

FIFTH SEMESTER
COMPUTER SCIENCE AND ENGINEERING
CS 1304- MICROPROCESSOR AND MICROCONTROLLERS
(REGULATION 2004)
w.

Answer ALL questions. PART A - (10 x 2 = 20 marks)

1. Write an 8085 assembly language program to multiply two 8-bit numbers.

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2. What are the functions of the RST 6.5 and ALE signals of 8085?
3. Write down the functions of the ASSUME and EXTRN assembler directives.
4. Define the functions of the REPEAT and LOCK prefixes.
5. Distinguish between the maximum mode and minimum mode of operation of the 8086
processor.
6. What is a coprocessor? How is it useful?
7. 8253's OUT signal is to be used as a clock input of the desired frequency to a particular
device. Is it possible? How?
8. How is a memory-to-memory transfer accomplished using 8237?

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9. What are the addressing modes supported by 8051?
10. Write an 8051program to divide two 8-bit number.

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PART B - (5 x 16 = 80 marks)

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11. (a) (i) Discuss the architecture of the 8085 processor with a neat diagram (10)
(ii) Write an 8085 program to subtract one 4-digit decimal number from another. (6)
OR
(b) (i) Discuss the interrupts of 8085 (10)

s.
(ii) Write an 8085 program to find the largest of a set of n 8-bit numbers. (6)

12. (a) (i) Assume that a symbol table starting at location TABLE consists of 100 entries. Each
entry has 80 bytes with the first 8 bytes representing the name field and the remaining 72 bytes

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representing the information field. Write an 8086 program sequence to search this table for a
given name of 8 characters stored in NAME. If this name is found, copy the associated
information to INFO: otherwise fill INFO with null characters.
(10)
(ii) Discuss about the interrupts of 8086.
no OR
(b) (i) Discuss the string primitives of 8086 with an examples for each.
(6)

(10)
(ii) Write an 8086 assembly language program using string primitives to find out whether a given
byte is in a string or not. If the byte is a part of the string, find the relative address of this byte
ar
from the start of the string.
(6)

13. (a) A multiprocessor system consists of 2 modules with the following specifications:
t

Module 1 : 8086 with 8087 and a resident bus (8)

Module 2 : 8086 with an I/O bus. (8)
5s

Draw a detailed block diagram showing the various components required and indicate the
interconnections between the various components. Explain briefly how co-ordination and
communication take place between the various masters.
OR
(b) Discuss the maximum mode configuration of 8086 with a neat diagram, clearly pointing out
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the functions of the various signals (16)

14. (a) With a neat diagram discuss the various modes of operation of 8255. Show how two 8255
chip can be connected in an connected in an 8086-based system to form a 16-bit port.
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OR
(b) With a neat diagram discuss the operation of a DMA controller. Show how such a controller
can be connected in an 8086-based system.

15. (a) Discuss the architecture of the 8051 microcontroller with a neat diagram.
OR
(b) Show how the 8051 can be used to control the operation of an elevator system. Assume the
elevator is to operate between three floors. Show the hardware interface and the required 8051

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program.

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B.E/B.TECH.DEGREE EXAMINATION, MAY/JUNE 2007.
Fifth Semester
Computer Science and Engineering
CS1304 – MICROPROCESSORS AND MICROCONTROLLERS
(Regulation 2004)

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Time: Three hours Maximum: 100 marks

Answer ALL questions

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PART A – (10 ´ 2 = 20 marks)
1. How address and data lines are demultiplexed in 8085?
2. What is the function performed by SIM instruction in 8085?
3. What is pipelined architecture? no
4. How the interrupts can be masked/unmasked in 8086?
5. What are the signals involved in memory bank selection in 8086
micro processor?
6. How clock signal is generated n 8086? What is the maximum internal clock
frequency of 8086?
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7. What is the function of gate signal in 8254 timer?
8. Write the format of KW1 in 8259.
9. List the interrupts of 8051 micro controller.
10. What are register banks in 8051 microcontroller?
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PART B – (5 ´ 16 = 80 marks)
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11. (a) (i) Explain the various logical and arithmetic instructions available in 8085
microprocessor. (10)
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(ii) Explain the function of various flags of 8085 microprocessor (6)

Or
(b) (i) Differentiate between I/O mapped I/O and memory mapped I/O. (6)
(ii) Write an 8085 assembly language program to convert 8 bit binary to ASCII code. (10)
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12. (a) (i) Describe the action taken by 8086 when INTR pin is activated. (6)
(ii) Write an assembly language program in 8086j to search the largest data in
an array. (10)
Or
(b) (i) Discuss the various addressing modes of 80896 microprocessor. (10)
(ii) Explain the following assembler directives used in 8086
(1) ASSUME

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(2) EQU
(3) DW (8)

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13. (a) (i) Explain in detail about memory access mechanism in 8086 (8)

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(ii) Explain the function of following 8086 signals.
(1) HLDA
(2) RQ/GTO
(3) DEN
(4) ALE. (8)

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Or
(b) (i) Draw and explain a block diagram showing 8086 in maximum mode
configuration. (12)
(ii) What are the advantages of the multiprocessor systems? (4)

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14. (a) (i) With the help of block diagram explain the operation of USART (8251A) (10)
(ii) Discuss the salient features of 8259 – programmable interrupt controller.
no (6)
Or
(b) (i) Describe the various modes of operations in 8253 programmable interval
Timer. (8)
(ii) Explain the operation of DMA controller (8237).
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15. (a) With a suitable block diagram, explain the architecture of 8051 microcontroller. (16)
Or
(b) Discuss in detail about 8051 based stepper motor control along with necessary
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hardware and software. (16)

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