Appendix: DSP Projects

Project A: Decimation
Project B: FIR Filter Design Variations
Project C: Analytic Filter-Pair Generation
Project D: Newton’s Method for Square Roots in QuickBasic 4.5
Project E: A Fast Square-Root Algorithm Using a Small Look-Up Table in Assembly Language
Project F: A High-Performance DDS
Project G: A Fast Binary Multiplier in High-Speed CMOS Logic

PROJECT A: DECIMATION
This project illustrates the concept of generated using the “Sine” function of the Next, decimate the sequence by a factor
decimation using Alkin’s PC-DSP pro- “Generate” sub-menu under the “Data” of 2 using the “Decimate” function found in
gram, included with the book of that name menu, with parameters Var1 = SIN, A = 1, the “Process” sub-menu under the “Data”
listed in the Bibliography. First, generate B = 0.25, C = 0 and #Samples = 40. Press menu. Use parameters Var1 = SIN2, Var2 =
40 samples of the sinusoid y(n) = sin(n/4), F2 to display the data, which should match SIN, Factor = 2. Display the new sequence
where 0 < n < 39. This sequence may be Fig 16.A1. by pressing F2. It should match Fig 16.A2.

Fig 16.A1—A 40-sample sine wave. Fig 16.A2—Decimated, 20-sample sine wave.

PROJECT B: FIR FILTER DESIGN VARIATIONS

An FIR filter’s ultimate attenuation and A filter obtained by convolving two fil- volved to get some of the benefits of each
its transition BW are largely determined ters of length L has length 2L –1. In one in the final filter.
by the filter’s length: the number of taps example, two LPFs of length 31 may be A look back at Fig 16.29 reveals that
used in its design. Fourier and other de- convolved to produce a filter of length 61. different window functions achieve differ-
sign methods do not always readily opti- The resulting frequency response, plotted ent transition BWs and values of ultimate
mize the trade-off among transition BW, against that of a LPF designed with Fou- attenuation. The rectangular window at-
ultimate attenuation and ripple. One way rier methods for an identical length of 61 tains a narrow transition BW, but a poor
to achieve better ultimate attenuation at taps, would show that the ultimate attenu- ultimate attenuation; the Blackman win-
the expense of passband ripple is to con- ation of the convolved filter is 20 dB or 10 dow, on the other hand, has nearly optimal
volve the impulse responses of two short times greater than that of the plain, Fou- ultimate attenuation and a moderate tran-
filters to obtain a longer filter. The two rier-designed filter. Also, the convolved sition BW. Let’s see what happens when
impulse-response sequences are processed filter would have a greater passband ripple we convolve the impulse responses of fil-
by precisely the same convolution sum that and a narrower transition region. Quite ters designed using each method. We will
is used to compute FIR filter outputs (Eq 3 often, filters that were designed using dif- constrain ourselves to filters with odd
in the main text). ferent window functions may be con- numbers of taps so that the convolved

16.36 Chapter 16

ch16.pmd 36 8/3/2007, 9:26 AM

 impulse response will also have an odd
number of taps.
Using your favorite filter-design soft-
ware, first design a LPF by the Fourier
method with a length of 31, using a rectan-
gular window, and a cut-off frequency
(–6 dB point) of 0.25fs. Its frequency re-
sponse is shown in Fig 16.B1A. We pro-
duce a second filter having the same
cut-off frequency of 0.25f s using a
Blackman window, whose response is
shown in Fig 16.B1B. The response of the
filter formed by the convolution of the two
filters is shown in Fig 16.B1C, along with
that of a standard Fourier-designed LPF.
The final filter has length 61 taps. Notice
that the filter obtains the benefits of the
rectangular window’s sharp transition re-
gion and those of the Blackman window’s
good ultimate attenuation.
A second advantage may be garnered by
convolving two different filters in that
their responses may be governed sepa-
rately, while producing desired changes in
frequency (or phase) response. A good ex-
ample of this arises when it is desired to
alter the audio response of an SSB trans-
mitter (or receiver), but keep the ultimate
attenuation characteristics the same. A
long BPF with excellent transition proper-
ties may be convolved with a much shorter
filter that is manipulated to provide the
desired passband response.
FIR filters used in Amateur Radio trans-
ceivers must usually have at least 60 dB
ultimate attenuation. This generally re-
quires at least 63 taps. As our second FIR
filter variation, let’s consider a case
wherein we want to customize an IF-DSP
transmitter’s frequency response without
impacting opposite-sideband rejection.
We will use a 99-tap BPF in each leg of a
Hilbert transformer (as part of an SSB
modulator) whose response is convolved
with that of a 31-tap filter describing the
variation in frequency response we want.
The 99-tap fixed filter has the frequency
response shown in Fig 16.B2A. The 31-
tap filter has been designed using Fourier
methods to have a 6 dB/octave rise in its
frequency response, as shown in Fig
16.B2B.
The frequency response of the convolu-
tion of the two filters’ impulse responses
is shown in Fig 16.B2C. It is important to
note that the net response is that of the
product of the two filters’ frequency re-
sponses; that is, if H1(ω) and H2(ω) are
the two frequency response functions, the
final response is simply: Fig 16.B1—LPF frequency response, rectangular window (A). LPF frequency
response, Blackman window (B). LPF frequency response, convolution of filters
H composite (ω ) = H1 (ω ) H 2 (ω ) (B1) shown in A and B (C).

DSP and Software Radio Design 16.37

ch16.pmd 37 8/3/2007, 9:26 AM

 Fig 16.B2—BPF for SSB use, L = 99 (A).
LPF having rising frequency response,
L = 31 (B). Frequency response of
convolution of filters shown in A and B
(C).

16.38 Chapter 16

ch16.pmd 38 8/3/2007, 9:26 AM

 PROJECT C: ANALYTIC FILTER PAIR GENERATION
Frequency-translation properties of complex signals from real signals for the resulting impulse response is a BPF filter
complex multiplication work just as well purposes of modulation, demodulation, centered on ω0, the sine wave’s frequency.
on the responses of filters as they do on and other processing algorithms. See Fig 16.C2B. Likewise, the prototype
real signals. In this project, we will ex- An analytic filter pair consists of two LPF’s impulse response is multiplied by a
plore just how these properties are applied filters (usually BPFs) whose frequency cosine-wave sequence to produce a filter
to the generation of analytic filter pairs. responses are identical, but whose phase having the same frequency response as that
Analytic filter pairs are used to produce responses differ at every frequency by 90°. of the sine-wave filter, but with a phase
These filters are used in legs of a Hilbert response differing by 90°. Sample-by-
transformer, as shown in Fig 16.C1. The sample multiplication occurs according to
creation of these filters begins with the de- Eq 21 in the main text.
sign of a LPF prototype having the desired When an analytic filter pair is used in a
passband, transition-band, and stopband demodulator, IF shift may be included by
characteristics. Such a prototype filter, as varying the frequency of w0. In combina-
might suffice for an SSB receiver, would tion with various filter BWs, IF shift is
have a frequency response such as that useful in avoiding interference by modify-
shown in Fig 16.C2A. ing a receiver’s frequency response. Fur-
The filter’s impulse response (L = 63) is ther modification may be obtained by
then multiplied by a sine-wave sequence convolving each filter in the analytic pair
(also L = 63) whose frequency represents with a filter having the desired character-
the amount of upward translation applied istic. The phase relation between the fil-
Fig 16.C1—Hilbert transformer using to the LPF’s frequency response. If the ters in the pair will not be altered by the
an analytic filter pair. sine wave is high enough in frequency, the convolution.

Fig 16.C2—LPF prototype frequency response (A). BPF frequency response of processed impulse response (B).

PROJECT D: NEWTON’S METHOD FOR SQUARE ROOTS IN QUICKBASIC 4.5

In this example of Newton’s method, a As described in the AM Demodulation quantization noise. A loop counter, K, is
generic BASIC program is given that com- section in the main text, Newton’s method established to count iterations. The pro-
putes the root of a 32-bit integer to within an iteratively converges on a result. Experi- gram displays on the computer screen the
error margin, DERROR. The root of a 32-bit ence has shown that three to six iterations argument, its root and the iteration count.
integer is naturally a 16-bit integer. Emphasis are necessary to obtain best accuracy for a Users may readily modify the program to
is placed in what follows on speed of execu- 16-bit result, but here we execute as many use random numbers as arguments to time
tion and accuracy as influenced by truncation iterations as necessary to obtain accuracy the number of roots per second it calculates.
and rounding. 32-bit integer variables are DERROR, initially defined to be one least- The program is included in the 2002
defined DEFLONG, 16-bit integers are significant bit or 1/(215) ≈ 30 × 10-6. Note ARRL Handbook companion software. The
DEFINT. Integer math in QuickBasic is much that if DERROR is small or zero, conver- software is available for free download
faster than floating-point math. gence may never be reached because of from ARRLWeb at: www.arrl.org/notes.

PROJECT E: A FAST SQUARE-ROOT ALGORITHM USING A SMALL LOOP-UP TABLE

This project is a machine-language ex- point DSP. The method is depicted in ware. The software is available for free
ample of a fast square-root algorithm. The Fig 16.16 in the main text. Like the pre- download from ARRLWeb at www.arrl.
target processor in this case is the vious project, this is included in the org/notes.
Motorola MC68HC16Z1, a 16-bit, fixed- 2002 ARRL Handbook companion soft-

DSP and Software Radio Design 16.39

ch16.pmd 39 8/3/2007, 9:26 AM

 16.40 Chapter 16

ch16.pmd 40 8/3/2007, 9:26 AM

 Fig 16.F2—Typical output spectrum of
DDS.

transformed into a serial interface by shift

registers U5 and U6, divider U3 and
counter U4. Each time the frequency is
changed, an internal 32-bit phase-incre-
ment accumulator must be updated. The
phase increment is just fout/fclk, expressed
Fig 16.F1—High-performance DDS schematic diagram. as a 32-bit, unsigned fraction. This value
is written into the chip in two 16-bit seg-
ments, most-significant bit of the most-
significant word first.
PROJECT F: A HIGH-PERFORMANCE DDS During serial programming, a data bit is
placed on the DATA line by the host mi-
A DDS is described below that is used added, eliminating virtually all the AM croprocessor; the clock line is toggled
as a reference for a PLL. See Fig 16.F1. spurs prior to the LPF. high, then low to shift the bit into the shift
This DDS is designed to cover a small The LPF at the output of the circuit is registers. After the first 16 bits have been
range of frequencies near 1 MHz. A crys- a 4-section elliptical type. Design im- shifted, they are written into the DDS by
tal-oscillator clock at 19.2 MHz is applied pedance is 100 Ω. This filter cuts out toggling the ENABLE line. Counter U4
to both the DDS, a Harris/Intersil many high-frequency spurs and stops supplies the necessary write pulse with
HSP45106, and the DAC, a Harris/Intersil clock feed-through. The DAC’s 10 input appropriate timing. The remaining 16 bits
HI5780. Making the DDS output fre- lines are fed from the 10 most-significant are then shifted and written to the chip,
quency a small fraction of the clock fre- bits of one of the DDS’s outputs. The completing the operation.
quency makes it relatively easy to obtain HSP45106 has two 16-bit outputs (sine An example of the output spectrum of this
excellent spurious performance. PM spurs and cosine) to accommodate the needs of circuit is shown in Fig 16.F2. Components
are limited to –90 dBc and AM spurs to complex-mixer designs, but only one is are surface-mount types and care must be
about –60 dBc. If the output is not squared being used here. exercised during construction. See Ulbing’s
at the input to a PLL chip, an external The DDS chip itself is programmed article in the Bibliography for information
Schmitt-trigger squaring stage may be using a 16-bit parallel interface. This is on surface-mount soldering techniques.

DSP and Software Radio Design 16.41

ch16.pmd 41 8/3/2007, 9:26 AM

 PROJECT G: A FAST BINARY MULTIPLIER IN HIGH-SPEED CMOS LOGIC
In this project, a fast 4-bit binary multi-
plier is described that may be constructed
from ‘HC-series logic gates or program-
med into an FPGA. Two variations are
explored: one without pipelining, and one
with pipelining. Pipelining is employed
where the propagation delays of gates limit
throughput.
As seen in Fig 16.45 in the main text,
a 4-bit multiplication may be broken
into several 4-bit additions. In our circuit,
4-bit adders are used to add rows of bits in
the summation, each one producing a
single output bit. The diagram of a fast,
4-bit adder with look-ahead carry is shown
in Fig 16.G1.
In this multiplier, 4-bit adders are used
to add adjacent rows of bits in the tradi-
tional way. A multiplier connected this
way is shown in Fig 16.G2. Not all bits in
each addend have mates in the other, so
4-bit adders suffice. In the case where
execution speed exceeds the reciprocal of
the total propagation delay, pipelining
must be employed to avoid error.
To use pipelining, we place storage
registers between the stages of addition
and one interim result is held by each stage
at each clock time. See Fig 16.G3. The
result is the same, but appears only after a
latency of three clock times. When maxi-
mum gate delays are well known, this
approach also yields more predictable
performance because the latency is inde-
pendent of the input data.

Fig 16.G1—A 4-bit adder schematic diagram.

16.42 Chapter 16

ch16.pmd 42 8/3/2007, 9:26 AM

 Fig 16.G2—Complete 4-bit multiplier, no pipelining.

DSP and Software Radio Design 16.43

ch16.pmd 43 8/3/2007, 9:26 AM

 Fig 16.G3—Complete 4-bit multiplier with pipelining.

16.44 Chapter 16

ch16.pmd 44 8/3/2007, 9:26 AM