AEC DEC Lab Manual New 31-07-19
AEC DEC Lab Manual New 31-07-19
B18EE3070
NAME : __________________
USN : __________________
CLASS : __________________
www.reva.edu.in
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How to read Resistor Color Codes
Now look at the 2nd color band and match that color to the
same chart. Write this number next to the 1st Digit.
The last color band is the number you will multiply the result by. Match the 3rd color band with the
chart under multiplier. This is the number you will multiply the other 2 numbers by. Write it next to
the other 2 numbers with a multiplication sign before it. Example : 2 2 x 1,000.
To pull it all together now, simply multiply the first 2 numbers (1st number in the tens column and
2nd in the ones column) by the Multiplier.
Read the number as the '% Failure rate per 1000 hour' This is rated assuming full wattage being
applied to the resistors. (To get better failure rates, resistors are typically specified to have twice the
needed wattage dissipation that the circuit produces) 1% resistors have three bands to read digits to
the left of the multiplier. They have a different temperature coefficient in order to provide the 1%
tolerance.
Tolerance Explained
Resistors are never the exact value that the color codes indicate. Therefore manufacturers place a
tolerance color band on the resistor to tell you just how accurate this resistor is made. It is simply a
measurement of the imperfections.
No
ban
Tolerance Rating Red = 2% Gold = 5% Silver = 10% d =
20
%
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As the chart indicates, Red means the resistor is within 2%; Gold means the resistor is within 5% of being
dead-on accurate. Silver being within 10% and no color band being within 20%. To determine the exact
range that the resistor may be, take the value of the resistor and multiply it by 5,10, 0r 20%. That is the
number that the resistor may go either way.
A couple of examples:
Example: A 1,000 Ohm resistor with a gold band maybe any value between 950 to 1050 Ohms.
Example: A 22,000 Ohm resistor with a silver band maybe any value between 19,800 and 24,200 Ohms.
Resistor FAQ's
The Gold or Silver band is always set to the right, then you read from left to right. Sometimes there
will be no tolerance band -- Simply find the side that has a band closest to a lead and make that the
first band.
2) Sometimes the colors are hard to make out. How do I make certain what the value of the
resistor really is?
Occasionally the colors are jumbled or burnt off. The only way to read it then is with a multi-meter
across the leads
Big Brown Rabbits Often Yield Great Big Vocal Groans WhenGingerly
Slapped
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INDUCTOR COLOR CODE
First find the tolerance band, it will typically be gold (5%) and sometimes silver (10%).
Starting from the other end, identify the first band - write down the number associated with that
color; in this case Red is 2.
Now 'read' the next color, here it is red so write down a 7 next to the two. (you should have '27' so
far.)
Now read the third or 'multiplier' band and write down that number of 10.
If the 'multiplier' band is Silver move the decimal point two places to the left.
Symbol B C S D F G H J K L M V N
Tolerance ±0.15nH ±0.2nH ±0.3nH ±0.5nH ±1% ±2% ±3% ±5% ±10% ±15% ±20% ±25% ±30%
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List of Experiments
I. Analog Electronics Circuit Design
1. Testing of Diode clipping (Single ended) circuits for peak clipping & peak detection.
2. Wiring of R-C coupled Single stage BJT amplifier and Determination of the gain- frequency
response, input and output Impedances.
3. Testing of a transformer less Class – B push pull power amplifier and determination of its
conversion efficiency.
4. Wiring and testing for the performance of BJT-RC Phase shift Oscillator for
fo = ≤10 kHz.
5. Testing for the performance of BJT – Hartley & Colpitt’s Oscillators for RF range
fo = ≥ 100kHz.
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PART: I Analog Electronics Circuit Design
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PROCEDURE:
RESULT:
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2. R-C COUPLED BJT & FET AMPLIFIERS
AIM: Wiring of R-C coupled single stage BJT and FET amplifier and determination of the gain-frequency
response, input and output impedances.
COMPONENTS/INSTRUMENTS REQUIRED: Transistor, FET, Capacitors, resistors, Power supply, Signal
generator, multimeter, DRB, CRO Probes, connecting wires etc.
BJT AMPLIFIER
CIRCUIT DIAGRAM:
Power Gain
dB
Gain
Bandwidth
(f2 – f1)
f1 f2
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PROCEDURE:
1. Connections are made as shown in circuit diagram. Measure the D.C. condition.
2. The input voltage Vin is adjusted to a convenient value (Approximately 20 to 40 mV) within the distortion
less limit and value must be kept constant throughout the experiment.
3. Frequency of the input signal is varied from 100Hz to 2MHz in steps and at each step, corresponding
output Vo is noted down.
4. All readings are tabulated and graph of Voltage gain in dB V/s frequency is drawn on a semi-log sheet.
OBSERVATIONS:
VBE= Volts. VCE= Volts. (Q – Point Voltage)
TABULAR COLUMN: Input Voltage Vin= mVolts.
Sl. # Frequency in Vo in Volts. Gain dB=20 log10 (Vo/Vin)
Hz.
100Hz
200Hz
300Hz
400Hz
500Hz
600Hz
700Hz
800Hz
900Hz
1KHz
2KHz
3KHz
4KHz
5kHz
6kHz
7kHz
8kHz
9kHz
10kHz
20Khz
30kHz
40kHz
50kHz
60kHz
70kHz
80kHz
90kHz
100kHz
200KHz
300kHz
400kHz
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500kHz
600kHz
700kHz
800kHz
900kHz
1000kHz
2000kHz
2. In the mid frequency region (where the gain is constant) with Ri = 0, (i.e., all the knobs of DRB in Zero
position.) the output voltage is measured.
3. Now the DRB resistance is increased till the output voltage falls to half of the initial value.
2. In the mid frequency region (where the gain is constant) with Ro = max, (i.e., all the knobs of DRB in
Maximum position.) the output voltage is measured.
3. Now the DRB resistance is decreased till the output voltage falls to half of the initial value.
RESULT:
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3. TRANSFORMER-LESS CLASS B PUSH-PULL POWER AMPLIFIER
AIM: Testing of a transformer less Class-B push pull power amplifier & determination of its conversion
efficiency.
COMPONENTS/INSTRUMENTS REQUIRED: Transistors, Resistors, Power supply, Milli Ammeter,
Function generator, DRB, CRO Connecting wire, CRO probes etc.
CIRCUIT DIAGRAM:
PROCEDURE:
1. Rig-up the circuit as shown above.
3. Adjust the input amplitude to get undistorted output at a frequency less than 1 kHz.
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TABULAR COLUMN: Vcc=9V.
100
200
300
WAVEFORMS:
RESULT:
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4. BJT R-C PHASE SHIFT OSCILLATOR
AIM: Wiring & testing the performance of BJT R-C Phase Shift Oscillator for fo = 2.5 kHz.
COMPONENTS/INSTRUMENTS REQUIRED: Power supply, Transistors, Resistors, POT, Capacitors, CRO etc.
CIRCUIT DIAGRAM:
Consider R = 2.2kΩ
Rc
K= = 1k = 0.454
R 2.2k
f= 1
2 RC 6 + 4(0.454)
Note:
• The last resistor in the phase shifting network is chosen to be a 10K Pot. This is done to get a overall
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phase shift of 1800 at frequency of oscillations.
• The maximum hfe required for the Transistor to operate is
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R Rc
h = 23 + 29 • + 4 •
fe min
Rc R
2. Switch on the power supply and the Output Vo (sine wave) is obtained on CRO. The 10 kΩ POT is
adjusted to get a stable output on the CRO.
3. Note down the practical frequency and compare it with the theoretical value.
RESULT:
Theoretical frequency fo = Hz.
Practical frequency fo = Hz.
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5 . BJT – HARTLEY AND COLPITT’S OSCILLATORS
AIM: Testing the performance of BJT – Hartley & Colpitt’s Oscillators for fo =100 kHz.
COMPONENTS/INSTRUMENTS REQUIRED: BJT, Resistors, POT, Capacitors, Inductors, DC power supply,
CRO etc.
HARTLEY OSCILLATOR
CIRCUIT DIAGRAM:
fo = 1 / 2 where Leff = L1 + L2
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COLPITT’S OSCILLATOR
2. Observe the output on CRO & measure the frequency & amplitude
RESULT:
Hartley oscillator: Colpitt’s oscillator:
Theoretical frequency fo = Hz. Theoretical frequency fo = Hz.
Practical frequency fo = Hz. Practical frequency fo =
Hz.
Amplitude = Volts Amplitude = Volts
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PART: II
Digital Electronics Circuit Design
Introduction
In 1854 George Boole introduced a systematic treatment of logic and developed an algebraic system now
known as Boolean algebra. In 1938, C.E. Shannon introduced a two valued Boolean algebra called switching
algebra, which demonstrated that, the properties of bi-stable electrical switching circuits could be represented
through this algebra. With passage of time Boolean algebra has emerged as a powerful tool and forms the
foundation of many theories of computer science and engineering.
Boolean algebra like any other mathematical system may be defined with a set of elements, a set of operators
and number of axioms or postulates. A set of element is a collection of objects having a common property.
logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs and one output.
At any given moment, every terminal is in one of the two binary conditions low (0) or high (1), represented by
different voltage levels. The logic state of a terminal can, and generally does, change often, as the circuit
processes data. In most logic gates, the low state is approximately zero volts (0 V), while the high state is
approximately five volts positive (+5 V).
There are seven basic logic gates: AND, OR, NAND, NOR, NOT, X-OR and X-NOR. The AND gate is so named because,
if 0 is called "false" and 1 is called "true," the gate acts in the same way as the logical "and" operator. The output is
"true" when both inputs are ''true.'' Otherwise, the output is "false." Comparing Boolean algebra with arithmetic and
ordinary algebra we note the following differences:
• Boolean algebra does not have additive or multiplicative inverses; hence there are no subtraction or
divisionoperations.
• Boolean algebra defines an operator called complement which is not available in normal algebra.
• Normal algebra deals with real number, which constitute an infinite set of elements whereas
Boolean algebra deals with a set of only two elements 0 and 1 (defined as two valued Boolean
algebra).
• The distributive law of '+' over '.' i.e., x + (y. z) = (x + y). (x + z) is valid for Boolean algebra but
not for normal algebra.
• Using combinations of logic gates, complex operations can be performed. In theory, there is
no limit to the number of gates that can be arrayed together in a single device. But in practice,
there is a limit to the number of gates that can be packed into a given physical space. Arrays
of logic gates are found in digital integrated circuits (lC’s).
• As IC technology advances, the required physical volume for each individual logic gate
decreases and digital devices of the same or smaller size become capable of performing ever-
more complicated operations at ever-increasing speed.
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Front View of Digital IC Trainer Kit
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1. Realizationof Basic Logic gates
Aim: To study the operation of Basic Logic gates
1. ANDGate
2. OR Gate
3. NOT Gate
4. EX-OR Gate
5. NANDGate
6. NOR Gate
Components & equipment required: 74LS:08, 32, 04, 86, 00 & 02, IC Trainer Kit, 4mm. Patch cards
1. AND Gate: IC 7408:
Truth Table
Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
2. OR Gate: IC 7432:
Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
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3. NOT Gate: IC 7404:
Truth Table
Input Output
A Y
0 1
1 0
Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Truth Table
Input Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
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6. NOR Gate: IC7402:
Truth Table
Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Truth Table verification of Logic gates using NAND & NOR gates (Universal gates)
NOT
gate
AND
gate
OR
gate
EX-OR
gate
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Procedure:
1. The connections are made as shown in Circuit (by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to the Output Connector
(LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table & the Output is
observed on LED’s.
5. Faults & Debugging:
6. Check Continuity of given Patch Chords before circuit Connection.
7. Check the working of Toggle Switch & Output LED Indicator {Initially All output LED Indicators will be in RED
(colour- Logic 1)}
8. Check IC Number for the given circuit & connect the circuit by checking pin details.
9. Check operating voltage connected to IC (+Vcc & Gnd.)
10. Apply Exact Combinations of Inputs as in Truth Table & Verify the output. Observations
Result:
Questions:
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Simplification and realization of given Boolean expression using Basic/Universal gates.
Aim: Simplification and realization of given Boolean expression using Basic/Universal gates.
Components & equipment required: 74LS-08, 32, 00 & 02, Digital IC Trainer Kit, 4mm. Patch cards etc.
a) De-Morgan’s theorem using Universal gates:
Truth Table
Input Output
A B
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
Truth Table
Input Output
A B
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
0 0 1
0 1 0
1 0 0
1 1 1
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ii) Using NOR Gate Only:
b) Realization of POSexpression:
i) UsingNANDgatesonly:
Truth Table
Input Output
A B Y
0 0 0
ii) Using NOR gates only:
0 1 1
1 0 1
1 1 0
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c) Realization of SOP expression:
i) Using AND-ORgates:
Truth Table
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
ii) Using only NAND gates: 0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
d) Realisation of POS expression:
1 1 1 1 1
Truth Table
i) Using AND-OR gates:
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
b) Using only NOR gates: 1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
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e) Realise the following expression using only NAND gates:
Truth Table
A B C D
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
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i) Simplification and Realization of given Boolean Expression in SOP form using Logic
Gates/Universal Gates
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
i) Using basicgates:
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
ii) UsingNANDgates: 1 1 1 1 1
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i) Using Basicgates:
Procedure:
1. The connections are made as shown in Circuit (by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to the Output
Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table & the Output is
observed on LED’s.
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Faults & Debugging:
1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output LED Indicators will be
in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc & Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.
Note: Students has to Simplify, Realize any given Boolean expression in the examination.
Result:
Questions:
What is the difference between SOP and POS?
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2. Realization of Combinational circuits
a) Multiplexer/DemultiplexerUsing IC74153&74139
Aim: Realizationof 4-bitMultiplexerand Demultiplexer. Multiplexer:
The demultiplexer is the inverse of the multiplexer, in that it takes a single data input and n address inputs. It has 2n
outputs.OutputisinvertedinIC741391:4 Demultiplixer.
Components & equipments required: IC 74153, 74139, 7404 & 7420. Digital IC Trainer Kit,4mm. Patchcardsetc.
Connection Diagram MUX
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Address
Enable
Select Data Inputs Output
Inputs
Inputs Comments
S1 S0 I0 I1 I2 I3 Y
0 0
0 0 0 X X X I0 Selected
1 1
0 0
0 0 1 X X X I1 Selected
1 1
0 0
0 1 0 X X X I2 Selected
1 1
0 0
0 1 1 X X X I3 Selected
1 1
1 X X X X X X X MUX Disabled
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Arithmetic Circuit Using IC74153 (4:1 MUX)
TRUTH TABLE
Input Output
A B S C
0 0 0 0 0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 1
Circuit Diagram:
Truth Table:
Input Output
A B S C
S1 S0 Ia Ib
0 0 0 0 0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 1
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Circuit Diagram:
Input Output
A B Cin S Cout
0 0 0 0 0 0
1 0 0 1 1 0
2 0 1 0 1 0
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 1
6 1 1 0 0 1
7 1 1 1 1 1
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Circuit Diagram:
Input Output
A B Cin S Cout
S1 S0 Ia Ib
0 0 0 0 0 0
cin Logic 0
1 0 0 1 1 0
2 0 1 0 1 0
cin
3 0 1 1 0 1
4 1 0 0 1 0
cin
5 1 0 1 1
0
6 1 1 0 0 1
cin Logic 1
7 1 1 1 1 1
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Circuit Diagram
Input Output
A B D B
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0
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Circuit Diagram:
OR
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Realization of Full Subtractor Using IC 74153
TruthTable: Implementation Table:
TRUTH TABLE
Input Output
A B Bin D Bout
0 0 0 0 0 0
1 0 0 1 1 1
2 0 1 0 1 1
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 0
6 1 1 0 0 0
7 1 1 1 1 1
Circuit Diagram:
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TruthTable: Implementation Table:
Input Output
A B Bin D Bout
0 0 0 0 0 0
Bin Bi
1 0 0 1 1 1
n
2 0 1 0 1 1
Logic 1
3 0 1 1 0 1
4 1 0 0 1 0
Logic 0
5 1 0 1 0
0
6 1 1 0 0 0
Bin Bi
7 1 1 1 n
1
Circuit Diagram
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Procedure:
1. The connections are made as shown in Circuit (by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to the Output
Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table & the Output is
observed on LED’s.
Result:
3. Whataretheapplicationsofmultiplexerandde-multiplexer?
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A digital comparatorcompares the two unsigned binary numbers A & B. The digital comparator has three outputs
A>B, A=B &A<B. An n Bitdigitalcomparator consistsof n Bits of A & n Bits of B. IC 7485 is a 4 Bit digital comparator
with capability of extendinginincrements of4 Bitsbyusingthecascadingfeature.
Magnitude Comparatoris a logicalcircuit, whichcompares two numbers Aand B andgeneratesthreelogical
outputs,whetherA>B,A=B,orA<B.IC7485isahigh speed
4- bit Magnitude comparator, which compares two 4-bit words. The A = B Input must be held high for proper
compare operation.
Components & equipments required: IC 7400, 7404, 7408, 7410, 7485 & 7486. Digital IC Trainer Kit, 4mm. Patch
cards etc.
Inputs Outputs
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
K-Map
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Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
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Maps:
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Compare any two arbitrary4 bitassumed binarynumbers and verify the results Example:
A B
Result
A3 A2 A1 A0 B3 B2 B1 B0
0 0 0 1 0 0 0 0 A>B
0 0 0 1 0 0 0 1 A=B
0 0 0 0 0 0 0 1 A<B
Procedure:
1. The connections are made as shown in Circuit (by referring IC PIN diagram)
2.The input terminals are connected to the toggle switches & the output is connected to the Output
Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4.The Logic levels are applied at the Input for all combinations indicated in Truth Table & the Output is
observed on LED’s.
5.X in the truth table indicates Don’t care condition since depending on the selection line the data line
will be selected.
6. Faults & Debugging:
7. Check Continuity of given Patch Chords before circuit Connection.
8.Check the working of Toggle Switch & Output LED Indicator {Initially All output LED Indicators will be
in RED (color- Logic 1)}
9. Check IC Number for the given circuit & connect the circuit by checking pin details.
10. Check operating voltage connected to IC (+Vcc & Gnd.)
11. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.
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Result:
1. What is a comparator?
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c) Binary to Gray Code conversion and Vice-Versa
Aim: Realization of Binary to Gray Code conversion and Vice-Versa. Binary to Gray Code Conversion:
• Invented by Emile Baudot (1845-1903) Originally called a "cyclic-permuted" code.
• Telegraph -5 bit codes, Bits stored on a code wheel in the receiver Wheel connected to the printing disk.
• Matched pattern on wheel and received pattern and then actuated head to print.
• Exhibited at Universal Exposition, Paris (1878).
Binary Codes:
• The usual way of expressing a decimal number in terms of a binary number is
known as pure binary coding. A number of other techniques can be used to represent a decimal number.
Gray Code:
• Gray coding is an important code and is used for its speed, it is also relatively free from errors. In pure
binary coding or 8421 BCD then counting from 7 (0 1 1 1) to 8 (1000) requires 4 bits to be changed
simultaneously. If this does not happen then various numbers could be momentarily generated during
the transition so creating spurious numbers which could be read.
• Gray coding avoids this since only one bit changes between subsequent numbers.
• To construct the code there are two simple rules. First start with all 0s and then proceed by changing the
least significant bit (LSB) which will bring about a new state.
• Components & equipments required: IC 7486, Digital IC Trainer Kit, 4mm. Patch cards etc.
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1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
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K - Maps:
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Truth Table for Grayto Binary Code conversion:
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
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Procedure:
1. The connections are made as shown in Circuit (by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to the Output Connector
(LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table & the Output is
observed on LED’s.
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Result:
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AEC & DEC Lab
3. Flip-Flops
Aim: To verify the truth table of JK Master-Slave, T type & D type Flip-Flops
JK Flip-Flop: One way of overcoming the problem with oscillation that occurs with a JK Flip-Flop when J= K =
1 is to use a so-called master-slave flip- flop which is illustrated in the circuit diagram.
The master-slave flip-flop is essentially two back-to-back JKFFs, note however, that feedback from
this device is fed back both to the master FF and the slave FF.
Any input to the master-slave flip-flop at J and K is first seen by the master FF part of the circuit while
CLK is High (= 1). This behavior effectively "locks" the input into the master FF. An important feature here is
that the complement of the CLK pulse is fed to the slave FF. Therefore, the outputs from the master FF are
only "seen" by the slave FF when CLK is Low (=0). Therefore, on the High-to-Low CLK transition the outputs
of the master are fed through the slave FF. This means that at most one change of state can occur when J=K
= 1 and so oscillation between the states Q=O and Q= 1 during the same CLK pulse does not occur.
Circuit Diagram
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Truth Table:
Inputs Outputs
Comments
J K CLK Qn n
0 0 X X X 1 1 Indeterminate State
0 1 X X X 1 0 FF Preset(Set)
1 0 X X X 0 1 FF Cleared(Reset)
1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
Note:
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Truth Table:
Inputs Outputs
Comments
T CLK Qn n
0 0 X X 1 1 Indeterminate State
0 1 X X 1 0 FF Preset(Set)
1 0 X X 0 1 FF Cleared(Reset)
Circuit Diagram:
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Truth Table:
Inputs Outputs
Comments
D CLK Qn n
0 0 X X 1 1 Indeterminate State
0 1 X X 1 0 FF Preset(Set)
1 0 X X 0 1 FF Cleared(Reset)
1 1 0 0 1 Data transferred
1 1 1 1 0 Data transferred
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Procedure:
1. The connections are made as shown in Circuit (by referring IC PIN diagram)
2. input terminals (JK, T & D) are connected to the toggle switches & the output is connected to the
Output Connector (LED’s).
6. The power is applied between the VCC & Ground terminals.
7. Connect clock pin to the bounce less pulsar HIGH or LOW
8. The Logic levels are applied at the Inputs as indicated in Truth Table & the Output is observed on
LED’s.
9. X in the truth table indicates Don’t Care condition.
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Result:
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School of EEE, REVA University
AEC & DEC Lab
4 JOHNSONCOUNTER
Aim:To realize & study of Ring Counter & Johnson
Ring counter: A ring counter is a circular shift register with only one flip-flop being set at any particular time; all
others are cleared. The single bit is shifted from one flip-flop to the other to produce the sequence of timing
signals. The initial value of the register is 1 0 0 0, which produces the variable 4. The single bit is shifted right with
every clock pulse and circulates back from Q0 to Q3.
Johnson counter: A twisted ring counter (or Johnson counter) is like a ring counter except the complement of the
output of last flip-flop is connected to input of first flip- flop, this results in a string of ones followed by zeros
moving around the ring. The register shifts its contents once to the right with every clock pulse.
Starting from a cleared state, the counter goes through a sequence of eight states. In general, a k-bit Johnson
counter will go through a sequence of 2k states.
Registers are used to store data or information. A register is basically an array of D-flip flops. An N-bit register
requires 'n' flip-flop to store data. The data may be transmitted from one digital system to the other either on a
single line or multiple lines. Accordingly, data transfer schemes are referred to as serial or parallel transfer
respectively.
Ring counter is a basic register with direct feedback that the contents of the registers simply circulate around the
register when the clock is provided.
Components & equipments required: IC 7404, 7495, Digital IC Trainer Kit, 4mm. Patch cards etc.
Circuit Diagram:
Truth Table:
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Mode Outputs
Clock Pulse
Control Q3 Q2 Q1 Q0
1 Clock-2 1 1 0 0 0
0 Clock-1 2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
7 0 0 1 0
8 0 0 0 1
CircuitDiagram
Truth Table
Mode Outputs
Clock Pulse
Control Q3 Q2 Q1 Q0
1 Clock-2 1 1 0 0 0
0 Clock-1 2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0
9 1 0 0 0
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Procedure:
1. Make Connections as shown in the circuit diagram.
2. Set mode control to High (Logic 1) & Connect clock 2 (PIN No. 8).
3. Apply input D3 D2 D1 D0 as 1 0 0 0 respectively and apply single clock pulse.
4. The output loaded with 1 0 0 0.
5. Change mode control to Low (Logic 0).
6. Connect 1 Hz. clock to clock 1 (PIN No. 9).
7. Apply clock pulse & observe output according to truth table.
Result:
1. What is aringcounter?
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5. 3- BitCounters
Aim: Realisation of 3-Bit ripple counters as sequential circuit & Mod N counter design.
Counters: The synchronous design of any sequential circuit application for example counter is a design in which all the
flip-flops are connected to a common clock input that is, all the flip-flops are clocked simultaneously. Therefore, to get
the next state of application actual inputs of the flip-flop should be designed according to the requirement.
Hence excitation tables are used to design the actual inputs of the flip-flops to get the next stage. The excitation table
gives the combination of input for the required output condition before and after the application of clock.
Components & equipments required: IC 7476, 7400, 7404, 7408, 7410, 7411, 7420, 7490, 74192, & 74193. Digital IC
Trainer Kit, 4mm. Patch cards etc.
Circuit Diagram:
Note:
• J & K inputs of Flip-Flops are connected to logic 1 or Keep it open to operate under toggle mode.
• When Preset = 1, Clear = 0; Counter is cleared Q0 = Q1 = Q2 = 0
• When Preset = 0, Clear = 1; Counter is preset Q0 = Q1 = Q2 = 1 Keep Preset = 1, Clear = 1 for count mode.
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Table
Flip-Flop Outputs
No. of
Clock Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
Truth Table:
Flip-Flop Outputs
No. of
Clock Pulses Q2 Q1 Q0
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1
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Flip-Flop Outputs
No. of
Clock Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 0 0 0
Circuit Diagram:(DEMO)
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When Mode control is at logic 1 counter works as an Up-counter. When Mode control is at logic 0 counter
works as a Down-counter
Result:
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