Random Notes for COA - Karim Zakka

• If address bus width = 10 bits => memory = 210 = 1024 bytes ≈ 1KB (kilobyte)

20 bits => memory = 220 = 1024K ≈ 1MB

30 bits => memory = 230 = 1024MB ≈ 1GB

32 bits => memory = 232 = 210 x 22 = 4086MB ≈ 1GB

• Byte to Kbyte -> ÷103 Byte to MB -> ÷106

• Kbyte to MB -> ÷103 MB to GB -> ÷103

• Volatile Memories examples: RAM, Cache, Registers. (Loses data when power source turns off).
• Non-volatile Memories examples: ROM, SSD, HDD. (Retains data when power source turns off).

• DRAM: cheap, slow, high-storage capacity.

• SRAM: expensive, fast, low-storage capacity.

• Stored charge (bit) in DRAM might leak away even with power continuously applied.

• Cache memory is sometimes called CPU memory, because it is typically integrated directly into
the CPU chip or placed on a separate chip that has a separate bus interconnect with the CPU.

• Memory in the CPU is called registers.

• Number of locations in memory = 2number of address lines/pins.

Chapter 2:

• Moore observed that the number of transistors that could be put on a single chip was
• doubling every year.

• Speedup = Old Execution Time / New Execution Time

Where OET is time to execute on 1 Processor, while NET is time to execute on N parallel processors.

• Speedup = 1 1: total execution time using one processor.

(1-f) +f f: fraction (%) of program that can be (process) parallelized.
N N: number of processors/Number of parallel parts.
NOTE:1-f = Sequential(can’t be accelerated)part of the program.
 • Amdahl’s law states that the program can’t be any faster than the sequential part of the
program no matter how much we parallelized.

• CPI = (CPI1 x I1) + (CPI2 x I2) + … (CPIn x In) CPI: Cycle Per Instruction.
Ic In: number of executed instructions.
Ic: sum of all number of executed instructions.

• MIPS Rate = f f: frequency in Hertz (processor clock speed).

CPI x 106
-OR-
MIPS Rate = Ic T: Processor time to execute a program.
T x 106

• Ic = T × [(MIPS rate)/106 ]

• T = Ic x CPI x t t: constant cycle time

• t= 1
f

• Arithmetic mean = 1/n x ( x1 + x2 +… xn) -OR- sum of values / total number of values (N).
• Harmonic mean = total number of values / (1/x1 + 1/x2 + … + 1/xn).

• 4 Main Components of any general-purpose computer:

➢ Main Memory, which stores both data and instructions.
➢ Arithmetic and Logic Unit (ALU) capable of operating on binary data/performs
data processing functions.
➢ Control Unit, which interprets the instructions in memory and causes them to
be executed.
➢ Input and Output (I/O) equipment operated by the control unit.

Chapter 3:

• Instruction Cycle: Fetch -> Decode -> (Load) -> Execute -> (Store).

• Instruction Format:

Opcode Operand / Address

ASA

svdv
 (ADD, JUMP, SUB…)

• If 4 bits for opcode => 12 bits for address => memory = 212.
• Possible states that define an instruction execution: Instruction Address Calculation (IAC) ->
Instruction Fetch (IF) -> Instruction Operation Decoding (IOD) -> Operand Address Calculation
(OAC) -> Operand Fetch (OF) -> Data Operation (DO) -> Operand Store (OS).

• Types of transfers must a computer’s interconnection structure (e.g., bus) support:

➢ Memory to Processor (processor reads from memory).
➢ Processor to Memory (processor writes from memory).
➢ I/O to Processor (processor reads from I/O) .
➢ Processor to I/O (processors sends to I/O).
➢ I/O to or from Memory. (I/O exchanges data directly with memory, without
going through the processor, using Direct Access Memory-DMA).

• 32-bit microprocessor -> 16-bit external data bus -> Data transferred per bus cycle = 32/16 = 2B.
• Maximum bus cycle rate = Bus Clock/Minimum Bus Cycle Duration.
• Data transfer rate (Bytes/sec) = bus cycle rate * data per bus cycle.

Chapter 4:

• Direct Mapping:
Direct mapping maps each block of main memory into only one possible cache line.
S W

Tag r
s-r
r: number of lines
w: word

Cache = 64K = 216.

Block size = 4 bytes (either given OR 2s+w)= 2 2 => Word = 2 bits.
Number of lines in Cache = Cache Size / Word. (216/22 = 214 = 14 bits).
Main memory size = ??? (Sometimes blocks x words/block) = 224.
Number of addressable units = 2 24.
Tag = Number of addressable units – (r + w) = 24 – (14+2) = 8 bits.
Mapping formula-> i = j modulo m where: i: cache line number.
j: main memory block number.
n: number of lines in cache.
• Set Associative Mapping:
In set-associative mapping, the cache is divided into a number of sets of cache lines; each main
memory block can be mapped into any line in a particular set.

Tag Set Word

Main memory size = ??? (Sometimes blocks x words/block) = 8K x 128 = 23 * 210 * 27 = 220.
Number of addressable units = 2 20.
Number of Sets in cache =
example: 128 lines divided into 2-line sets => 27/21 = 26 = 6 bits (if two-way set associative).
example: 128 lines divided into 4-line sets => 27/22 = 25 = 5 bits (if four-way set associative).
Number of blocks in main memory = 8K = 213 = 13.
We know that Sets + Tag = blocks => 6 + Tag = 13 => Tag = 7 bits.
Word = Number of addressable units – (Tag + Set) = 20 – (7+6) = 7 bits.

• Associative Mapping:
Associative mapping permits each main memory block to be loaded into any line of the cache.

Tag W

Very similar to set-associate, but with the absence of Set and Tag takes up most of the
addressable units.
 Direct Mapping Equations Associative Mapping Set-Associative Mapping
Equations Equations
Address length = s+w bits Address length = s+w bits Address length = s+w bits
Number of addressable units Number of addressable units Number of addressable units
= 2s+w = 2s+w = 2s+w
Block size = line size = 2w Block size = line size = 2w Block size = line size = 2w
Number of blocks in main Number of blocks in main Number of blocks in main
memory = 2s+w/2w = 2s memory = 2s+w/2w = 2s memory = 2s+w/2w = 2s
Number of lines in cache = 2r Number of lines in cache = Number of lines in set = k
undetermined (can’t be
determined in address)
Size of Cache= 2r+w Size of tag = s Number of sets = v = 2d
Size of tag = s-r Number of lines in cache = m
= kv = k x 2d
Size of Cache = k x 2d+w
Size of tag = s-d