MC74HC4538A

Dual Precision Monostable

Multivibrator (Retriggerable,
Resettable)
The MC74HC4538A is identical in pinout to the MC14538B. The
device inputs are compatible with standard CMOS outputs; with http://onsemi.com
pullup resistors, they are compatible with LSTTL outputs.
This dual monostable multivibrator may be triggered by either the MARKING
positive or the negative edge of an input pulse, and produces a DIAGRAMS
precision output pulse over a wide range of pulse widths. Because the
device has conditioned trigger inputs, there are no trigger–input rise 16
16
and fall time restrictions. The output pulse width is determined by the MC74HC4538AN
1
external timing components, Rx and Cx. The device has a reset AWLYYWW
function which forces the Q output low and the Q output high, PDIP–16
N SUFFIX 1
regardless of the state of the output pulse circuitry.
CASE 648
• Unlimited Rise and Fall Times Allowed on the Trigger Inputs
• Output Pulse is Independent of the Trigger Pulse Width
• ± 10% Guaranteed Pulse Width Variation from Part to Part (Using
the Same Test Jig) 16
16
• Output Drive Capability: 10 LSTTL Loads 1 HC4538A
• Outputs Directly Interface to CMOS, NMOS and TTL SO–16
AWLYWW

• Operating Voltage Range: 3.0 to 6.0 V D SUFFIX 1

• Low Input Current: 1.0 µA CASE 751B

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A 16
•
16
Chip Complexity: 145 FETs or 36 Equivalent Gates HC
1
4538A
TSSOP–16 ALYW
GND 1 16 VCC DT SUFFIX
CASE 948F 1
CX1/RX1 2 15 GND
RESET 1 3 14 CX2/RX2
A1 4 13 RESET 2 A = Assembly Location
B1 5 12 A2 L, WL = Wafer Lot
Y, YY = Year
Q1 6 11 B2
W, WW = Work Week
Q1 7 10 Q2
GND 8 9 Q2

Figure 1. Pin Assignment ORDERING INFORMATION

Device Package Shipping
MC74HC4538AN PDIP–16 2000/Box
MC74HC4538AD SOIC–16 48/Rail
MC74HC4538ADR2 SOIC–16 2500/Reel
MC74HC4538ADT TSSOP–16 96/Rail
MC74HC4538ADTR2 TSSOP–16 2500/Reel

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

April, 2001 – Rev. 8 MC74HC4538A/D
 MC74HC4538A

CX 1 RX 1
VCC

1 2

4 6
TRIGGER A1 Q1
INPUTS 5 7
B1 Q1

3
RESET 1
CX 2 RX 2
VCC

15 14

12 10
TRIGGER A2 Q2
INPUTS 11 9
B2 Q2

13
PIN 16 = VCC RESET 2
PIN 8 = GND
RX AND CX ARE EXTERNAL COMPONENTS
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND

Figure 2. Logic Diagram

FUNCTION TABLE
Inputs Outputs
Reset A B Q Q
H H
H L
H X L Not Triggered
H H X Not Triggered
H L,H, H Not Triggered
H L L,H, Not Triggered
L X X L H
X X Not Triggered

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 MC74HC4538A

MAXIMUM RATINGS (Note 1)

Symbol Parameter Value Unit
VCC DC Supply Voltage 0.5 to 7.0 V
VI DC Input Voltage 0.5  VI  VCC 0.5 V
VO DC Output Voltage (Note 2) 0.5  VO  VCC 0.5 V
IIK DC Input Diode Current A, B, Reset
20 mA
CX, RX
30

IOK DC Output Diode Current
25 mA

IO DC Output Sink Current
25 mA
ICC DC Supply Current per Supply Pin
100 mA
IGND DC Ground Current per Ground Pin
100 mA
TSTG Storage Temperature Range 65 to 150
C
TL Lead temperature, 1 mm from Case for 10 Seconds 260
C
TJ Junction temperature under Bias 150
C
JA Thermal resistance PDIP 78
C/W
SOIC 112
TSSOP 148
PD Power Dissipation in Still Air at 85
C PDIP 750 mW
SOIC 500
TSSOP 450
MSL Moisture Sensitivity Level 1
FR Flammability Rating Oxygen Index: 30% – 35% UL–94–VO (0.125 in)
VESD ESD Withstand Voltage Human Body Model (Note 3) >2000 V
Machine Model (Note 4) >100
Charged Device Model (Note 5) >500
ILatch–Up Latch–Up Performance Above VCC and Below GND at 85
C (Note 6)
300 mA

1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated
conditions is not implied.
2. IO absolute maximum rating must be observed.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
7. For high frequency or heavy load considerations, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0* 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types –55 +125
C
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figure 7) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
A or B (Figure 5) – No Limit
Rx External Timing Resistor VCC < 4.5 V 1.0 † k

VCC ≥ 4.5 V 2.0 †

Cx External Timing Capacitor 0 † F

*The HC4538A will function at 2.0 V but for optimum pulse–width stability, VCC should be above 3.0 V.
†The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due to board layout
and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 F/1.0 M
. Values of Cx > 1.0 F may cause a
problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for Rx > 1.0 M
.
8. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
9. Information on typical parametric values can be found in the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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 MC74HC4538A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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DC CHARACTERISTICS

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Guaranteed Limits

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–55 to 25
C  85
C  125
C
VCC

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ÎÎÎ
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Symbol Parameter Test Conditions Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VIH Minimum High–Level Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Input Voltage |Iout|  20 µA 4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2

ÎÎÎÎ
ÎÎÎÎÎÎÎ
VIL

ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Input Voltage ÎÎÎ
Maximum Low–Level

ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Vout = 0.1 V or VCC – 0.1 V

ÎÎ
|Iout|  20 µA
2.0
4.5
0.5
1.35
0.5
1.35
0.5
1.35
V

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VOH Minimum High–Level Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Output Voltage |Iout|  20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
6.0 5.9 5.9 5.9

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Vin = VIH or VIL
|Iout|  –4.0 mA

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ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
4.5 3.98 3.84 3.7
|Iout|  –5.2 mA 6.0 5.48 5.34 5.2

ÎÎÎÎ
ÎÎÎÎÎÎÎ
VOL

ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Maximum Low–Level

ÎÎÎ
Output Voltage ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VIH or VIL

ÎÎ
|Iout|  20 µA
2.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
V

ÎÎÎÎ
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6.0 0.1 0.1 0.1

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Vin = VIH or VIL
|Iout|  4.0 mA 4.5 0.26 0.33 0.4

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ÎÎÎ
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|Iout|  5.2 mA 6.0 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Iin Maximum Input Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Leakage Current
(A, B, Reset)

ÎÎÎÎ
ÎÎÎÎÎÎÎ
Iin

ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Maximum Input

ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Leakage Current ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Vin = VCC or GND

ÎÎ
6.0 ± 50 ± 500 ± 500 nA

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
(Rx, Cx)
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ICC Maximum Quiescent Vin = VCC or GND 6.0 130 220 350
Supply Current Q1 and Q2 = Low

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
(per package) Iout = 0 µA
Standby State

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ICC
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Maximum Supply
Current
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ
Vin = VCC or GND
Q1 and Q2 = High 25
C –45
C to 85
C –55
C to 125
C

ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
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(per package) Iout = 0 µA
Active State Pins 2 and 14 = 0.5 VCC 6.0 400 600 800 µA

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 MC74HC4538A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ
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ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Guaranteed Limits

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Î ÎÎ
ÎÎÎ
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ÎÎÎ
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–55 to 25
C  85
C  125
C
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Symbol Parameter Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
tPLH Maximum Propagation Delay 2.0 175 220 265 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
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ÎÎÎ
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Input A or B to Q 4.5 35 44 53
(Figures 6 and 8) 6.0 30 37 45

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Input A or B to NQ

ÎÎÎÎÎ
Maximum Propagation Delay

ÎÎ
2.0
4.5
195
39
245
49
295
59
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
(Figures 6 and 8) 6.0 33 42 50

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
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ÎÎÎÎÎ
tPHL Maximum Propagation Delay 2.0 175 220 265 ns
Reset to Q 4.5 35 44 53

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
(Figures 7 and 8) 6.0 30 37 45

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
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ÎÎÎÎÎ
tPLH Maximum Propagation Delay 2.0 175 220 265 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Reset to NQ 4.5 35 44 53
(Figures 7 and 8) 6.0 30 37 45

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH,

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎ
(Figures 7 and 8)

ÎÎÎÎÎ
2.0
4.5
75
15
95
19
110
22
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
6.0 13 16 19

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
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ÎÎÎÎÎ
Cin Maximum Input Capacitance (A. B, Reset) — 10 10 10 pF
(Cx, Rx) 25 25 25

10. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (per Multivibrator)* 150 pF

*Used to determine the no–load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . For load considerations, see the ON Semiconductor
High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
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ÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING CHARACTERISTICS (Input tr = tf = 6.0 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limits

ÎÎÎÎ
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ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
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ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
–55 to 25
C  85
C  125
C
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Symbol Parameter Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
trec Minimum Recovery Time, Inactive to A or B 2.0 0 0 0 ns
(Figure 7) 4.5 0 0 0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
6.0 0 0 0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(Figure 6)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Minimum Pulse Width, Input A or B

ÎÎ
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(Figure 7) ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
Minimum Pulse Width, Reset

ÎÎÎ
ÎÎÎÎÎ
2.0
4.5
60
12
75
15
90
18
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times, Reset 2.0 1000 1000 1000 ns
(Figure 7) 4.5 500 500 500

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
6.0 400 400 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
A or B 2.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 7) 4.5 No Limit
6.0

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 MC74HC4538A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
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OUTPUT PULSE WIDTH CHARACTERISTICS (CL = 50 pF)t

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ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Conditions Guaranteed Limits

ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
–55 to 25
C  85
C  125
C
VCC

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Symbol Parameter Timing Components Volts Min Max Min Max Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
τ Output Pulse Width* Rx = 10 kΩ, Cx = 0.1 µF 5.0 0.63 0.77 0.6 0.8 0.59 0.81 ms

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
(Figures 6 and 8)

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
— Pulse Width Match — — ± 5.0 %
Between Circuits in the

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
same Package

ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
— Pulse Width Match — — ± 10 %

ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Variation (Part to Part)

*For output pulse widths greater than 100 µs, typically τ = kRxCx, where the value of k may be found in Figure 3.

0.8 10 s
k, OUTPUT PULSE WIDTH CONSTANT

TA = 25°C
1s VCC = 5 V, TA = 25°C

OUTPUT PULSE WIDTH (τ)

0.7
100 ms

0.6 10 ms
(TYPICAL)

1 ms
0.5 100 µs 1 MΩ

10 µs 100 kΩ
0.4
1 µs 10 kΩ

0.3 100 ns 1 kΩ
1 2 3 4 5 6 7 0.00001 0.0001 0.001 0.01 0.1 1 10 100
VCC, POWER SUPPLY VOLTAGE (VOLTS) CAPACITANCE (µF)

Figure 3. Typical Output Pulse Width Constant, Figure 4. Output Pulse Width versus Timing Capacitance
k, versus Supply Voltage
(For output pulse widths > 100 µs: τ = kRxCx)

1.1
Rx = 100 kΩ TA = 25°C
(NORMALIZED TO 5 V NUMBER)

Cx = 1000 pF
1
OUTPUT PULSE WIDTH (τ)

0.9

0.8
Rx = 1 MΩ
0.7 Cx = 0.1 µF

0.6

0.5
1 2 3 4 5 6 7
VCC, POWER SUPPLY VOLTAGE (VOLTS)

Figure 5. Normalized Output Pulse Width versus Power Supply Voltage

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 MC74HC4538A

1.1

(NORMALIZED TO 25
C NUMBER)

1.05

OUTPUT PULSE WIDTH (τ)

1
VCC = 6 V Rx = 10 kΩ
0.95 Cx = 0.1 µF

0.9

0.85
VCC = 3 V
0.8
–75 –50 –25 0 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (°C)

Figure 6. Normalized Output Pulse Width versus Power Supply Voltage

1.03
(NORMALIZED TO 25
C NUMBER)
OUTPUT PULSE WIDTH (τ)

1.02 Rx = 10 kΩ
Cx = 0.1 µF
1.01

VCC = 5.5 V
0.99

0.98 VCC = 5 V
VCC = 4.5 V
0.97
–75 –50 –25 0 25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (°C)

Figure 7. Normalized Output Pulse Width versus Power Supply Voltage

tw(H)
VCC
50%
A GND

tw(L)

B VCC
50%
GND

tPLH τ tPLH τ

50%
Q

tPHL τ tPHL τ
Q
50%

Figure 8. Switching Waveform

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 MC74HC4538A

tr tf
VCC
90%
A 10% GND

trr
VCC
50%
B GND

tf tf
VCC
90%
RESET 50%
10% GND
tw(L) trec
tTLH τ + trr
tPHL
90% (RETRIGGERED PULSE)
50% 50%
Q 10%

tTHL tPLH
Q
90%
50%
10%

Figure 9. Switching Waveform

TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL *

*Includes all probe and jig capacitance

Figure 10. Test Circuit

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 MC74HC4538A

PIN DESCRIPTIONS
INPUTS capacitors (see the Block Diagram). Polystyrene capacitors
A1, A2 (Pins 4, 12) are recommended for optimum pulse width control.
Electrolytic capacitors are not recommended due to high
Positive–edge trigger inputs. A rising–edge signal on
leakages associated with these type capacitors.
either of these pins triggers the corresponding multivibrator
when there is a high level on the B1 or B2 input. GND (Pins 1 and 15)
B1, B2 (Pins 5, 11) External ground. The external timing capacitors discharge
to ground through these pins.
Negative–edge trigger inputs. A falling–edge signal on
either of these pins triggers the corresponding multivibrator
OUTPUTS
when there is a low level on the A1 or A2 input.
Reset 1, Reset 2 (Pins 3, 13) Q1, Q2 (Pins 6, 10)
Reset inputs (active low). When a low level is applied to Noninverted monostable outputs. These pins (normally
one of these pins, the Q output of the corresponding low) pulse high when the multivibrator is triggered at either
multivibrator is reset to a low level and the Q output is set to the A or the B input. The width of the pulse is determined by
a high level. the external timing components, RX and CX.
CX1/RX1 and CX2/RX2 (Pins 2 and 14) Q1, Q2 (Pins 7, 9)
External timing components. These pins are tied to the Inverted monostable outputs. These pins (normally high)
common points of the external timing resistors and pulse low when the multivibrator is triggered at either the A
or the B input. These outputs are the inverse of Q1 and Q2.

RxCx

UPPER
REFERENCE OUTPUT
CIRCUIT LATCH
–
VCC + Vre,
UPPER

M1 LOWER
VCC REFERENCE
CIRCUIT
2 kΩ –
M2 + Q
Vre,
LOWER
M3

TRIGGER
CONTROL CIRCUIT
A
C Q
TRIGGER CONTROL
CB RESET CIRCUIT
B R

RESET

POWER
ON
RESET
RESET LATCH

Figure 11. Logic Detail (1/2 the Device)

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 MC74HC4538A

CIRCUIT OPERATION

Figure 12 shows the HC4538A configured in the TRIGGER OPERATION

retriggerable mode. Briefly, the device operates as follows The HC4538A is triggered by either a rising–edge signal
(refer to Figure 10): In the quiescent state, the external at input A (#7) or a falling–edge signal at input B (#8), with
timing capacitor, Cx, is charged to VCC. When a trigger the unused trigger input and the Reset input held at the
occurs, the Q output goes high and Cx discharges quickly to voltage levels shown in the Function Table. Either trigger
the lower reference voltage (Vref Lower  1/3 VCC). Cx signal will cause the output of the trigger–control circuit to
then charges, through Rx, back up to the upper reference go high (#9).
voltage (Vref Upper  2/3 VCC), at which point the The trigger–control circuit going high simultaneously
one–shot has timed out and the Q output goes low. initiates two events. First, the output latch goes low, thus
The following, more detailed description of the circuit taking the Q output of the HC4538A to a high state (#10).
operation refers to both the logic detail (Figure 9) and the Second, transistor M3 is turned on, which allows the
timing diagram (Figure 10). external timing capacitor, Cx, to rapidly discharge toward
ground (#11). (Note that the voltage across Cx appears at the
QUIESCENT STATE input of both the upper and lower reference circuit
In the quiescent state, before an input trigger appears, the comparator).
output latch is high and the reset latch is high (#1 in When Cx discharges to the reference voltage of the lower
Figure 10). Thus the Q output (pin 6 or 10) of the monostable reference circuit (#12), the outputs of both reference circuits
multivibrator is low (#2, Figure 10). will be high (#13). The trigger–control reset circuit goes high,
The output of the trigger–control circuit is low (#3), and resetting the trigger–control circuit flip–flop to a low state
transistors M1, M2, and M3 are turned off. The external (#14). This turns transistor M3 off again, allowing Cx to begin
timing capacitor, Cx, is charged to VCC (#4), and both the to charge back up toward VCC, with a time constant t = RxCx
upper and lower reference circuit has a low output (#5). (#15). Once the voltage across Cx charges to above the lower
In addition, the output of the trigger–control reset circuit reference voltage, the lower reference circuit will go low
is low. allowing the monostable multivibrator to be retriggered.
QUIESCENT TRIGGER CYCLE TRIGGER CYCLE
STATE (A INPUT) (B INPUT) RESET RETRIGGER

7
trr
TRIGGER INPUT A
(PIN 4 OR 12)

TRIGGER INPUT B
(PIN 5 OR 11) 8
24
9
TRIGGER-CONTROL 3 14
CIRCUIT OUTPUT
4 11 21 23
15 17
RX/CX INPUT
12
(PIN 2 OR 14)
Vref UPPER 25
Vref LOWER 13

5 18
UPPER REFERENCE
CIRCUIT 13

LOWER REFERENCE 6 16
CIRCUIT
RESET INPUT
20
(PIN 3 OR 13)
1
RESET LATCH
22

10

2 19
Q OUTPUT
(PIN 6 OR 10)
τ τ τ + trr

Figure 12. Timing Diagram

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 MC74HC4538A

When Cx charges up to the reference voltage of the upper occurs, the output of the reset latch goes low (#22), turning
reference circuit (#17), the output of the upper reference on transistor M1. Thus Cx is allowed to quickly charge up to
circuit goes low (#18). This causes the output latch to toggle, VCC (#23) to await the next trigger signal.
taking the Q output of the HC4538A to a low state (#19), and On power up of the HC4538A the power–on reset circuit
completing the time–out cycle. will be high causing a reset condition. This will prevent the
trigger–control circuit from accepting a trigger input during
POWER–DOWN CONSIDERATIONS this state. The HC4538A’s Q outputs are low and the Q not
Large values of Cx may cause problems when powering outputs are high.
down the HC4538A because of the amount of energy stored
in the capacitor. When a system containing this device is RETRIGGER OPERATION
powered down, the capacitor may discharge from VCC When used in the retriggerable mode (Figure 12), the
through the input protection diodes at pin 2 or pin 14. HC4538A may be retriggered during timing out of the
Current through the protection diodes must be limited to 30 output pulse at any time after the trigger–control circuit
mA; therefore, the turn–off time of the VCC power supply flip–flop has been reset (#24), and the voltage across Cx is
must not be faster than t = VCC
Cx /(30 mA). For example, above the lower reference voltage. As long as the Cx voltage
if VCC = 5.0 V and Cx = 15 µF, the VCC supply must turn off is below the lower reference voltage, the reset of the
no faster than t = (5.0 V)
(15 µF)/30 mA = 2.5 ms. This is flip–flop is high, disabling any trigger pulse. This prevents
usually not a problem because power supplies are heavily M3 from turning on during this period resulting in an output
filtered and cannot discharge at this rate. pulse width that is predictable.
When a more rapid decrease of VCC to zero volts occurs, The amount of undershoot voltage on RxCx during the
the HC4538A may sustain damage. To avoid this possibility, trigger mode is a function of loop delay, M3 conductivity,
use an external damping diode, Dx, connected as shown in and VDD. Minimum retrigger time, trr (Figure 7), is a
Figure 11. Best results can be achieved if diode Dx is chosen function of 1) time to discharge Rx Cx from VDD to lower
to be a germanium or Schottky type diode able to withstand reference voltage (Tdischarge); 2) loop delay (Tdelay); 3)
large current surges. time to charge Rx Cx from the undershoot voltage back to the
lower reference voltage (Tcharge).
RESET AND POWER ON RESET OPERATION Figure 13 shows the device configured in the
A low voltage applied to the Reset pin always forces the non–retriggerable mode.
Q output of the HC4538A to a low state. For additional information, please see Application Note
The timing diagram illustrates the case in which reset (AN1558/D) titled Characterization of Retrigger Time in
occurs (#20) while Cx is charging up toward the reference the HC4538A Dual Precision Monostable Multivibrator.
voltage of the upper reference circuit (#21). When a reset

DX

CX VCC

RX

Q
A
B Q

RESET

Figure 13. Discharge Protection During Power Down

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 MC74HC4538A

TYPICAL APPLICATIONS

CX RX CX RX

RISING–EDGE RISING–EDGE
TRIGGER TRIGGER VCC
VCC

Q Q
A A
B Q
B Q

B = VCC

RESET = VCC RESET = VCC

CX RX CX RX
FALLING–EDGE
VCC TRIGGER VCC
A = GND
Q
Q
A
B Q B Q
FALLING–EDGE
TRIGGER
RESET = VCC RESET = VCC

Figure 14. Retriggerable Monostable Circuitry Figure 15. Non–retriggerable Monostable Circuitry

GND N/C
A = GND
RX CX
Q N/C
VCC
B
Q N/C
RESET

Figure 16. Connection of Unused Section

ONE–SHOT SELECTION GUIDE

100 ns 1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1 s 10 s

MC14528B
MC14536B 23 HR
MC14538B
MC14541B 5 MIN
HC4538A*

*Limited operating voltage (2–6 V)

TOTAL OUTPUT PULSE WIDTH RANGE

RECOMMENDED PULSE WIDTH RANGE

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 MC74HC4538A

PACKAGE DIMENSIONS

PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C A 0.740 0.770 18.80 19.55
L
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0
10
0
10

0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

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 MC74HC4538A

PACKAGE DIMENSIONS

SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE J J 0.19 0.25 0.008 0.009
M
K 0.10 0.25 0.004 0.009
D 16 PL M 0
7
0
7

P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

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 MC74HC4538A

PACKAGE DIMENSIONS

TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O

16X K REF

0.10 (0.004) M T U S V S NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
0.15 (0.006) T U S
K Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.

ÉÉ
ÇÇ
K1 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR

ÇÇ
ÉÉ
16 9
2X L/2 J1 PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
B SECTION N–N REFERENCE ONLY.
L 5. THE LEAD WIDTH DIMENSION (b) DOES NOT
–U– INCLUDE DAMBAR PROTRUSION. ALLOWABLE
J DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
PIN 1
TOTAL IN EXCESS OF THE LEAD WIDTH
IDENT. DIMENSION AT MAXIMUM MATERIAL CONDITION.
1 8 DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
N BETWEEN PROTRUSIONS AND ADJACENT LEAD
0.25 (0.010) TO BE 0.46 ( 0.018).
0.15 (0.006) T U S
A M
MILLIMETERS INCHES
–V–
DIM MIN MAX MIN MAX
N A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
F C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
DETAIL E F 0.50 0.75 0.020 0.030

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 MC74HC4538A

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