1.

4 CMOS Logic 9

1.4 CMOS Logic

1.4.1 The Inverter
Figure 1.11 shows the schematic and symbol for a CMOS inverter or NOT gate using one VDD
nMOS transistor and one pMOS transistor. The bar at the top indicates VDD and the trian-
gle at the bottom indicates GND. When the input A is 0, the nMOS transistor is OFF and
A Y
the pMOS transistor is ON. Thus, the output Y is pulled up to 1 because it is connected to
VDD but not to GND. Conversely, when A is 1, the nMOS is ON, the pMOS is OFF, and Y
is pulled down to ‘0.’ This is summarized in Table 1.1. GND
(a)
TABLE 1.1 Inverter truth table
A Y A Y
0 1
(b)
1 0
FIGURE 1.11
Inverter schematic
1.4.2 The NAND Gate (a) and symbol
(b) Y = A
Figure 1.12(a) shows a 2-input CMOS NAND gate. It consists of two series nMOS tran-
sistors between Y and GND and two parallel pMOS transistors between Y and VDD. If
either input A or B is 0, at least one of the nMOS transistors will be OFF, breaking the
path from Y to GND. But at least one of the pMOS transistors will be ON, creating a
path from Y to VDD. Hence, the output Y will be 1. If both inputs are 1, both of the nMOS Y
A
transistors will be ON and both of the pMOS transistors will be OFF. Hence, the output
will be 0. The truth table is given in Table 1.2 and the symbol is shown in Figure 1.12(b). B
Note that by DeMorgan’s Law, the inversion bubble may be placed on either side of the
gate. In the figures in this book, two lines intersecting at a T-junction are connected. Two (a)
lines crossing are connected if and only if a dot is shown.

TABLE 1.2 NAND gate truth table

(b)
A B Pull-Down Network Pull-Up Network Y
0 0 OFF ON 1 FIGURE 1.12 2-input NAND
gate schematic (a) and symbol
0 1 OFF ON 1 (b) Y = A · B
1 0 OFF ON 1
1 1 ON OFF 0

k-input NAND gates are constructed using k series nMOS transistors and k parallel Y
A
pMOS transistors. For example, a 3-input NAND gate is shown in Figure 1.13. When any
B
of the inputs are 0, the output is pulled high through the parallel pMOS transistors. When
C
all of the inputs are 1, the output is pulled low through the series nMOS transistors.

FIGURE 1.13 3-input NAND

1.4.3 CMOS Logic Gates gate schematic Y = A · B · C

The inverter and NAND gates are examples of static CMOS logic gates, also called comple-
mentary CMOS gates. In general, a static CMOS gate has an nMOS pull-down network to
connect the output to 0 (GND) and pMOS pull-up network to connect the output to 1
(VDD), as shown in Figure 1.14. The networks are arranged such that one is ON and the
other OFF for any input pattern.
 10 Chapter 1 Introduction

The pull-up and pull-down networks in the inverter each consist of a single
transistor. The NAND gate uses a series pull-down network and a parallel pull-
pMOS up network. More elaborate networks are used for more complex gates. Two or
pull-up
network
more transistors in series are ON only if all of the series transistors are ON.
Two or more transistors in parallel are ON if any of the parallel transistors are
Inputs
ON. This is illustrated in Figure 1.15 for nMOS and pMOS transistor pairs.
Output By using combinations of these constructions, CMOS combinational gates
can be constructed. Although such static CMOS gates are most widely used,
nMOS Chapter 9 explores alternate ways of building gates with transistors.
pull-down In general, when we join a pull-up network to a pull-down network to
network
form a logic gate as shown in Figure 1.14, they both will attempt to exert a logic
level at the output. The possible levels at the output are shown in Table 1.3.
From this table it can be seen that the output of a CMOS logic gate can be in
FIGURE 1.14 General logic gate using
pull-up and pull-down networks
four states. The 1 and 0 levels have been encountered with the inverter and
NAND gates, where either the pull-up or pull-down is OFF and the other
structure is ON. When both pull-up and pull-down are OFF, the high-
impedance or floating Z output state results. This is of importance in multiplexers, memory
elements, and tristate bus drivers. The crowbarred (or contention) X level exists when both
pull-up and pull-down are simultaneously turned ON. Contention between the two net-
works results in an indeterminate output level and dissipates static power. It is usually an
unwanted condition.

a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

a a a a a

0 0 1 1
g1
g2
0 1 0 1
b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF
FIGURE 1.15 Connection and behavior of series and parallel transistors
 1.4 CMOS Logic 11

TABLE 1.3 Output states of CMOS logic gates

pull-up OFF pull-up ON
pull-down OFF Z 1
pull-down ON 0 crowbarred (X)

1.4.4 The NOR Gate

A 2-input NOR gate is shown in Figure 1.16. The nMOS transistors are in parallel to pull
the output low when either input is high. The pMOS transistors are in series to pull the A
output high when both inputs are low, as indicated in Table 1.4. The output is never crow- B
barred or left floating. Y

TABLE 1.4 NOR gate truth table

A B Y (a)
0 0 1
0 1 0
1 0 0 (b)
1 1 0 FIGURE 1.16 2-input NOR
gate schematic (a) and symbol
(b) Y = A + B
Example 1.1
Sketch a 3-input CMOS NOR gate.
SOLUTION: Figure 1.17 shows such a gate. If any input is high, the output is pulled low A
through the parallel nMOS transistors. If all inputs are low, the output is pulled high B
through the series pMOS transistors. C
Y

1.4.5 Compound Gates

A compound gate performing a more complex logic function in a single stage of logic is FIGURE 1.17 3-input NOR
formed by using a combination of series and parallel switch structures. For example, the gate schematic Y = A + B + C
derivation of the circuit for the function Y = (A · B) + (C · D) is shown in Figure 1.18.
This function is sometimes called AND-OR-INVERT-22, or AOI22 because it per-
forms the NOR of a pair of 2-input ANDs. For the nMOS pull-down network, take the
uninverted expression ((A · B) + (C · D)) indicating when the output should be pulled to
‘0.’ The AND expressions (A · B) and (C · D) may be implemented by series connections
of switches, as shown in Figure 1.18(a). Now ORing the result requires the parallel con-
nection of these two structures, which is shown in Figure 1.18(b). For the pMOS pull-up
network, we must compute the complementary expression using switches that turn on
with inverted polarity. By DeMorgan’s Law, this is equivalent to interchanging AND and
OR operations. Hence, transistors that appear in series in the pull-down network must
appear in parallel in the pull-up network. Transistors that appear in parallel in the pull-
down network must appear in series in the pull-up network. This principle is called con-
duction complements and has already been used in the design of the NAND and NOR
gates. In the pull-up network, the parallel combination of A and B is placed in series with
the parallel combination of C and D. This progression is evident in Figure 1.18(c) and
Figure 1.18(d). Putting the networks together yields the full schematic (Figure 1.18(e)).
The symbol is shown in Figure 1.18(f ).
 12 Chapter 1 Introduction

A C A C
B D B D

(a) (b)

C D
A B C D
A B

(c) (d)

C D
A
A B
B
Y Y
C
A C
D
B D

(e) (f)
FIGURE 1.18 CMOS compound gate for function Y = (A · B) + (C · D)

This AOI22 gate can be used as a 2-input inverting multiplexer by connecting C = A

as a select signal. Then, Y = B if C is 0, while Y = D if C is 1. Section 1.4.8 shows a way to
improve this multiplexer design.

A
Example 1.2
B Sketch a static CMOS gate computing Y = (A + B + C) · D.
C D
Y SOLUTION: Figure 1.19 shows such an OR-AND-INVERT-3-1 (OAI31) gate. The
D nMOS pull-down network pulls the output low if D is 1 and either A or B or C are 1,
A B C so D is in series with the parallel combination of A, B, and C. The pMOS pull-up net-
work is the conduction complement, so D must be in parallel with the series combina-
FIGURE 1.19 tion of A, B, and C.
CMOS compound gate
for function
Y = (A + B + C) · D 1.4.6 Pass Transistors and Transmission Gates
The strength of a signal is measured by how closely it approximates an ideal voltage source.
In general, the stronger a signal, the more current it can source or sink. The power sup-
plies, or rails, (VDD and GND) are the source of the strongest 1s and 0s.
An nMOS transistor is an almost perfect switch when passing a 0 and thus we say it
passes a strong 0. However, the nMOS transistor is imperfect at passing a 1. The high
voltage level is somewhat less than VDD, as will be explained in Section 2.5.4. We say it
passes a degraded or weak 1. A pMOS transistor again has the opposite behavior, passing
strong 1s but degraded 0s. The transistor symbols and behaviors are summarized in Figure
1.20 with g, s, and d indicating gate, source, and drain.
When an nMOS or pMOS is used alone as an imperfect switch, we sometimes call it
a pass transistor. By combining an nMOS and a pMOS transistor in parallel (Figure
1.21(a)), we obtain a switch that turns on when a 1 is applied to g (Figure 1.21(b)) in
which 0s and 1s are both passed in an acceptable fashion (Figure 1.21(c)). We term this a
transmission gate or pass gate. In a circuit where only a 0 or a 1 has to be passed, the appro-
priate transistor (n or p) can be deleted, reverting to a single nMOS or pMOS device.