CARRY look ahead ADDERS

-------------------------------------
module CLA_Adder(a,b,cin,sum,cout);
input[3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;
assign p0=(a[0]^b[0]),
p1=(a[1]^b[1]),
p2=(a[2]^b[2]),
p3=(a[3]^b[3]);
assign g0=(a[0]&b[0]),
g1=(a[1]&b[1]),
g2=(a[2]&b[2]),
g3=(a[3]&b[3]);
assign c0=cin,
c1=g0|(p0&cin),
c2=g1|(p1&g0)|(p1&p0&cin),
c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin),
c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);
assign sum[0]=p0^c0,
sum[1]=p1^c1,
sum[2]=p2^c2,
sum[3]=p3^c3;
assign cout=c4;
endmodule

Testbench Code- Carry Look Ahead Adder

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: CLA_Adder
// Project Name: Carry Look Ahead Adder
///////////////////////////////////////////////////////////////////////////
module TestModule;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [3:0] sum;
wire cout;

// Instantiate the Unit Under Test (UUT)

CLA_Adder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 5;
b = 6;
cin = 1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

--------------------------------------------------------
CARRY SKIP ADDERS
--------------------------------------------------
module carry_skip_4bit(a, b, cin, sum, cout);
input [3:0] a,b; // a= 4 bits b= 4 bits
input cin;
output [3:0] sum; // 4 bit of A with 4 bit of B = 4 bits
output cout;
wire [3:0] p; // interconnecting blocks
wire c0;
wire bp;
ripple_carry_4_bit rca1 (a[3:0],b[3:0],cin,sum[3:0],c0);
generate_p p1(a,b,p,bp);
mux2X1 m0(c0,cin,bp,cout);
endmodule
///////////////////////////////////////////////////////////////////////////////////
///
// Propagate Generation
///////////////////////////////////////////////////////////////////////////////////
//
module generate_p(a,b,p,bp);
input [3:0] a,b;
output [3:0] p;
output bp;
assign p= a^b;//get all propagate bits
assign bp= &p;// and p0p1p2p3 bits
endmodule
///////////////////////////////////////////////////////////////////////////////////
///
//4-bit Ripple Carry Adder
///////////////////////////////////////////////////////////////////////////////////
//
module ripple_carry_4_bit(a, b, cin, sum, cout);
input [3:0] a,b;
input cin;
wire c1,c2,c3;
output [3:0] sum;
output cout;
full_adder fa0(a[0], b[0],cin, sum[0],c1);
full_adder fa1(a[1], b[1],c1, sum[1],c2);
full_adder fa2(a[2], b[2],c2, sum[2],c3);
full_adder fa3(a[3], b[3],c3, sum[3],cout);
endmodule
///////////////////////////////////////////////////////////////////////////////////
///
//1bit Full Adder
///////////////////////////////////////////////////////////////////////////////////
//
module full_adder(a,b,cin,sum, cout);
input a,b,cin;
output sum, cout;
wire x,y,z;
half_adder h1(a,b,x,y);
half_adder h2(x,cin,sum,z);
or or_1(cout,z,y);
endmodule
/////////////////////////////////////////////////////////////////////////////
// 1 bit Half Adder
//////////////////////////////////////////////////////////////////////
module half_adder( a,b, sum, cout );
input a,b;
output sum, cout;
xor xor_1 (sum,a,b);
and and_1 (cout,a,b);
endmodule
///////////////////////////////////////////////////////////////////////////////////
///
//2X1 Mux
///////////////////////////////////////////////////////////////////////////////////
//
module mux2X1( in0,in1,sel,out);
input in0,in1;
input sel;
output out;
assign out=(sel)?in1:in0; // conditional operator
endmodule

----------------------------------------

Carry Skip Adder_TB

module carry_skip_4bit_tb_v;
reg [3:0] a; reg [3:0] b; reg cin;
wire [3:0] sum;
wire cout;
carry_skip_4bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
#0 a = 0; b = 0; cin = 0;
#100 a=1010;b=1000;cin=1;
#100 a=1001;b=1010;cin=0;
#100 a=0101;b=0010;cin=1;
#100 a=0010;b=0101;cin=0;
end
endmodule

--------------------------------------------------------------------
Wallace tree multiplier

module wallace (prod,a,b);

input [3:0] a,b;
output [7:0] prod;
wire s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11;
reg p [3:0][3:0];
integer i,j;

always@(a or b)
begin
for (i =0; i<=3; i=i+1)
for (j=0; j<=3; j = j+1)
p[j][i]<= a[j]&b[i];
end

ha h1(s0,c0,p[0][1],p[1][0]);
fa f1(s1,c1,p[0][2],p[1][1],p[2][0]);
fa f2(s2,c2,p[0][3],p[1][2],p[2][1]);
fa f3(s3,c3,p[1][3],p[2][2],1'b0);

fa f4(s4,c4,s1,c0,1'b0);
fa f5(s5,c5,s2,c1,p[3][0]);
fa f6(s6,c6,s3,c2,p[3][1]);
fa f7(s7,c7,p[2][3],c3,p[3][2]);

fa f8(s8,c8,s5,c4,1'b0);
fa f9(s9,c9,s6,c8,c5);
fa f10(s10,c10,s7,c6,c9);
fa f11(s11,c11,p[3][3],c7,c10);

assign prod[0] = p[0][0];

assign prod[1] = s0;
assign prod[2] = s4;
assign prod[3] = s8;
assign prod[4] = s9;
assign prod[5] = s10;
assign prod[6] = s11;
assign prod[7] = c11;

endmodule

module ha(s,c,a,b);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

module fa(s,c,a,b,cin);
input a,b,cin;
output s,c;
wire s1,c1,c2;
ha h1(s1,c1,a,b);
ha h2(s,c2,s1,cin);
or(c,c2,c1);
endmodule

Test bench
----------

module hfhf;

// Inputs
reg [3:0] a;
reg [3:0] b;

// Outputs
wire [7:0] prod;

// Instantiate the Unit Under Test (UUT)

wallace uut (
.prod(prod),
.a(a),
.b(b)
);

initial begin
// Initialize Inputs
a = 1101;
b = 1100;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule