NCP4205

Dual Output 1 Phase and

2 Phase Controller with
Single SVI2 Interface for
Desktop and Notebook CPU
Applications www.onsemi.com

The NCP4205 dual output one plus two phase buck solution is
optimized for AMD® SVI2 CPUs. The controller combines true MARKING
differential voltage sensing, differential inductor DCR current DIAGRAM
sensing, input voltage feed−forward, and adaptive voltage positioning
to provide accurately regulated power for both desktop and notebook NCP4205
applications.
The control system is based on Dual−Edge pulse−width modulation FAWLYYWW
G
(PWM) combined with DCR current sensing providing an ultra fast
initial response to dynamic load events and reduced system cost. The
NCP4205 provides the mechanism to shed to single phase during light QFN44
load operation and can auto frequency scale in light load conditions CASE 485CH
while maintaining excellent transient performance. F = Wafer Fab
Dual high performance operational error amplifiers are provided to A = Assembly Location
simplify compensation of the system. Patented Dynamic Reference WL = Wafer Lot ID
YY = Year
Injection further simplifies loop compensation by eliminating the need WW = Work Week
to compromise between closed−loop transient response and Dynamic G = Pb−Free Package
VID performance. Patented Total Current Summing provides highly
accurate current monitoring for droop and digital current monitoring.
ORDERING INFORMATION
Features See detailed ordering and shipping information on page 43 of
• Meets AMD’S SVI2 Specifications this data sheet.

• One Phase Mail Rail

• Two Phase North Bridge Voltage Regulator • Switching Frequency Range of 240 kHz – 1.0 MHz
• Current Mode Dual Edge Modulation for Fast Initial • “Lossless” DCR Current Sensing for Current Balancing
Response to Transient Loading • Startup into Pre−Charged Loads while avoiding False
• Dual High Performance Operational Error Amplifier OVP
• One Digital Soft Start Ramp for Both Rails • Power Saving Phase Shedding
• Dynamic Reference Injection • Vin Feed Forward Ramp Slope
• Accurate Total Summing Current Amplifier • Pin Programming for Internal SVI2 parameters
• DAC with Droop Feed−forward Injection • Over Voltage Protection (OVP) and Under Voltage
• Dual High Impedance Differential Voltage and Total Protection (UVP)
Current Sense Amplifiers • Over Current Protection (OCP)
• Phase−to−Phase Dynamic Current Balancing • Dual Power Good Output with Internal Delays
• Summed Compensated Inductor Current Sensing for • These Devices are Pb−Free and are RoHS Compliant
Droop
Applications
• True Differential Current Balancing Sense Amplifiers
for Each Phase • Desktop and Notebook Processors
• Adaptive Voltage Positioning (AVP) • Gaming Applications

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

April, 2016 − Rev. 1 NCP4205/D
 NCP4205

ADD SDA SCL

ENABLE
VDDNB_PWRGD
ENABLE_NB DIGITAL VSS_SENSE VDDNB_PWRGD
INTERFACE VDDNB_SENSE COMPARATOR
EN/ENNB NB_DAC
UVLO & EN ENABLE PWROK
GND
Digital Config and
ENABLE
value registers
VCC VSS_SENSE VDD_PWRGD
VDD_SENSE COMPARATOR VDD_PWRGD
VDD_SENSE DAC
NORTH BRIDGE OVP_NB DROOP
OVP
VSS_SENSE
OCP_L THERMAL
MONITOR OVP
VDDNB_SENSE OVP
VDDNB
ENABLE DAC
ENABLE_NB
VDDNB−VSS_SENSE VSS
DIFFAMP GND
VDD−VSS_SENSE
SVD ADC IMAX CSREF
SVI2 MUX IMAXNB
SVC DROOPNB
INTERFACE SR
SVT SRNB
VDDIO DAC
DAC
VBOOT
DIFFNB
NB_DAC
DAC
VSS
DAC CS CSSUMNB
VDD ILIM AMP_NB
GND DIFFAMP IOUT CSREFNB
NORTH BRIDGE
CSREF
CSCOMPNB
DROOP
ILIMNB

IOUTNB
DIFF
FBNB
ERROR
FB AMP_NB
ERROR RAMP
AMP GENERATORS
TRANSIENT
CONTROL COMPNB
COMP ENABLE
COMP
TRBST CSP1NB
OVP ENABLE_NB
NORTH
CSN1NB
BRIDGE
CSSUM
CS CURRENT CSP2NB
CSN1 AMP BALANCE
ENABLE CSN2NB

MAIN RAIL RAMP1 RAMP

CSCOMP PHASE
GENERATOR GENERATORS

ILIM ILIM
IOUT
IOUT

ENABLE_NB
COMPNB
CSP1 MAIN RAIL
CURRENT OVP_NB
CSN1 BALANCE

PWM1NB/SRNB
RAMP1NB
NORTH BRIDGE PWM2NB
RAMP2NB PWM
GENERATOR
PWM1/SR

DRON

VRMP

Figure 1. Block Diagram

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 NCP4205

CSCOMPNB
DROOPNB

CSSUMNB
COMPNB
PWROK

IOUTNB
DIFFNB
VDDNB

ILIMNB
FBNB
SVD
44
43
42
41
40
39
38
37
36
35
34
SVT 1 33 CSREFNB
SVC 2 32 CSN2NB
VDDIO 3 31 CSP2NB
SCL 4 30 CSN1NB
SDA 5 NCP4205 29 CSP1NB

VDD_PWRGD 6 Pin Package 28 DRON

VDDNB_PWRGD 7 (PIN 45 AGND) 27 PWM1NB/SRNB

EN/ENNB 8 26 PWM2NB

9 25 ADD
VCC
10 24 PWM1/SR
VRMP
11 23 CSN1
OCP_L
12
13
14
15
16
17
18
19
20
21
22
CSCOMP

CSSUM
COMP

IOUT

CSP1
DROOP
ILIM
VSS

FB
DIFF
VDD

Figure 2. NCP4205 PINOUTS

PIN DESCRIPTION
Pin No. Symbol Description
1 SVT Serial VID telemetry line
2 SVC Serial VID clock line
3 VDDIO VDDIO is an interface power rail that serves as a reference for SVI2 interface
4 SCL Serial clock line, Open drain, requires pull−up resistor
5 SDA Bi directional serial data line. Open drain, requires pull−up resistor.
6 VDD_PWRGD Open drain output. High output on this pin indicates that the Main Rail output is regulating.
7 VDDNB_PWRGD Open drain output. High indicates that the North Bridge output is regulating.
8 EN/ENNB Logic input. Logic high enables both the Main and North Bridge rail output and logic low disables main
rail output.

9 VCC Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground.
10 VRMP Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used to
control of the ramp of PWM slope

11 OCP_L Open drain output. Signals an over temperature event has occurred
12 VSS Inverting input to the Main Rail differential remote sense amplifier.
13 VDD Non−inverting input to the Main Rail differential remote sense amplifier.
14 FB Error amplifier voltage feedback for Main Rail output
15 DIFF Output of the Main Rail differential remote sense amplifier.
16 COMP Output of the error amplifier and the inverting inputs of the PWM comparators for the Main Rail output.
17 ILIM Over current shutdown threshold setting for Main Rail output. Resistor to CSCOMP to set threshold.
18 DROOP Used to program droop function for Main Rail output. It’s connected to the resistor divider placed be-
tween CSCOMP and CSREF summing node.

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 NCP4205

PIN DESCRIPTION
Pin No. Symbol Description
19 CSCOMP Output of total current sense amplifier for Main Rail output.
20 IOUT Total output current for Main Rail.
21 CSSUM Inverting input of total current sense amplifier for Main Rail output.
22 CSP1 Non−inverting input to current balance sense amplifier for phase 1
23 CSN1 Inverting input to current balance sense amplifier for phase1
24 PWM1/SR Phase1 PWM output. A resistor to ground on start up sets the slew rate for the main rail
25 ADD A resistor to ground on this pin programs the SMBus address on start−up
26 PWM2NB North Bridge Phase 2PWM output.
27 PWM1NB/SRNB North Bridge Phase 1PWM output. A resistor to ground on start−up sets the slew rate for the NB rail
28 DRON Bidirectional gate driver enable for external drivers for both core and North Bridge rails. It should be
left floating if unused.

29 CSP1NB Non−inverting input to current balance sense amplifier for North Bridge phase 1
30 CSN1NB Non−inverting input to current balance sense amplifier for North Bridge phase 1
31 CSP2NB Non−inverting input to current balance sense amplifier for North Bridge phase 2
32 CSN2NB Inverting input to current balance sense amplifier for North Bridge phase2
33 CSREFNB Total output current sense amplifier reference voltage input for North Bridge. And inverting input to
North Bridge current balance sense amplifier for phase 1 and 2

34 IOUTNB Total output current for North Bridge Rail.

35 CSSUMNB Inverting input of total current sense amplifier for North Bridge output
36 CSCOMPNB Output of total current sense amplifier for North Bridge output
37 DROOPNB Used to program droop function for North Bridge output. It’s connected to the resistor divider placed
between CSCOMPNB and CSREFNB.

38 ILMNB Over current shutdown threshold setting for North Bridge output. Resistor to CSCOMPNB to set
threshold.

39 COMPNB Output of the North Bridge error amplifier and the inverting input of the PWM comparator for North
Bridge output

40 FBNB Error amplifier voltage feedback for North Bridge output

41 DIFFNB Output of the North Bridge differential remote sense amplifier.
42 VDDNB Non−inverting input to the North Bridge differential remote sense amplifier
43 PWROK Active high system wide power ok signal
44 SVD Serial VID data line
45 AGND Analog Ground bottom

Table 1. ABSOLUTE MAXIMUM RATINGS

Pin Symbol VMAX VMIN ISOURCE ISINK
COMP, COMPNB VCC + 0.3 V −0.3 V 2 mA 2 mA
CSCOMP, CSCOMPNB VCC + 0.3 V −0.3 V 2 mA 2 mA
VSS, GND + 0.3 V GND – 0.3 V 1 mA 1 mA
VDD_PWRGD, VDDNB_PWRGD VCC + 0.3 V −0.3 V N/A 2 mA
VCC 6.5 V −0.3 V N/A N/A
VRMP +25 V −0.3 V
All Other Pins VCC + 0.3 V −0.3 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to GND unless noted otherwise.

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 NCP4205

Table 2. THERMAL INFORMATION

Thermal Characteristic − QFN Package (Note 1) RqJA Typ _C/W
Operating Junction Temperature Range (Note 2) TJ −10 to 125 C
Operating Ambient Temperature Range −10 to 100 _C
Maximum Storage Temperature Range TSTG −40 to +150 _C
Moisture Sensitivity Level − QFN Package MSL 1
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM

Table 3. NCP4205 (1+2) ELECTRICAL CHARACTERISTICS

Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter Test Conditions Min Typ Max Units
ERROR AMPLIFIER
Input Bias Current −400 400 nA
Open Loop DC Gain CL = 20 pF to GND, RL = 10 KW to GND 80 dB
Open Loop Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 KW to GND 55 MHz
Slew Rate DVin = 100 mV, G = −10 FV/V, 20 mV/ms
DVout = 1.5 V – 2.5 V,
CL = 20 pF to GND,
DC Load = 10 k to GND
Maximum Output Voltage ISOURCE = 2.0 mA 3.5 − − V
Minimum Output Voltage ISINK = 2.0 mA − − 1.0 V
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current −400 − 400 nA
VSP Input Voltage Range −0.3 − 3.0 V
VSN Input Voltage Range −0.3 − 0.3 V
−3 dB Bandwidth CL = 20 pF to GND, 12 MHz
RL = 10 KW to GND
Closed Loop DC gain VS to DIFF VS+ to VS− = 0.5 to 1.3 V 1.0 V/V
Droop Accuracy CSREF−DROOP = 80 mV −73.5 −70.5 mV
DAC = 0.8 V to 1.2 V

Maximum Output Voltage ISOURCE = 2 mA 3.0 − − V

Minimum Output Voltage ISINK = 2 mA − − 0.5 V
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos) −300 300 mV
Input Bias Current CSSUM = CSREF = 1 V −1.0 1.0 mA
Open Loop Gain 80 dB
Current Sense Unity Gain CL = 20pF to GND, 10 MHz
Bandwidth RL = 10K to GND

Maximum CSCOMP (NB) Output Isource = 2mA 3.5 − − V

Voltage

Minimum CSCOMP(NB) Output Isink = 500 mA − − 0.15 V

Voltage

CURRENT BALANCE AMPLIFIER

Input Bias Current CSP1 − 2NB = CSN1 − 2NB = 1.2 V −50 − 50 nA
CSP = CSN = 1.2 V 100 100

Common Mode Input Voltage CSPx = CSREF 0 − 2.0 V

Range

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 NCP4205

Table 3. NCP4205 (1+2) ELECTRICAL CHARACTERISTICS

Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter Test Conditions Min Typ Max Units
CURRENT BALANCE AMPLIFIER
Differential Mode Input Voltage CSNx = 1.2 V −100 − 100 mV
Range

Closed loop Input Offset Voltage CSPx = CSNx = 1.2 V, −1.5 − 1.5 mV
Matching Measured from the average

Current Sense Amplifier Gain 0 V < CSPx − CSNx < 0.1 V 5.7 6.0 6.3 V/V
Multiphase Current Sense Gain CSN = CSP = 10 mV to 30 mV −3 3 %
Matching

−3 dB Bandwidth 8.0 MHz

BIAS SUPPLY
Supply Voltage Range 4.75 5.25
VCC Quiescent Current EN = high 49 mA
EN = low 49 mA
UVLO Threshold VCC rising 4.5 V
VCC falling 3.9 V
VCC UVLO Hysteresis 200 mV
DAC SLEW RATE
Main Rail Soft Start Slew Rate 2.5 mV/ms
Main Rail Slew Rate Slow 5.0 mV/ms
Main Rail Slew Rate Fast 20 mV/ms
NORTH BRIDGE Soft Start Slew 2.5 mV/ms
Rate

NORTH BRIDGE Slew Rate Slow 2.5 mV/ms

NORTH BRIDGE Slew Rate Fast 10 mV/ms
ENABLE INPUT
Enable High Input Leakage External 1 K pull−up to 3.3 V − 1.0 mA
Current

Upper Threshold VUPPER 2.0 V

Lower Threshold VLOWER 0.8 V
Enable delay time Enable high−DRVON high 15 us
VCC high to DRVON UVLO rising threshold with Enable high 2.5 ms
DRON
Output High Voltage Sourcing 500 mA 3.0 − − V
Output Low Voltage Sinking 500 mA − − 0.1 V
Pull Up Resistances 2.0 kW
Rise/Fall Time CL (PCB) = 20 pF, DVo = 10% to 90% − 160 ns
Internal Pull Down Resistance VCC = Low 70 kW
IOUT OUTPUT /IOUTNB
Input Referred Offset Voltage Ilimit to CSREF −3.0 +3.0 mV
Output current max Current Ratio − − 800 mA
Current Gain (IOUTCURRENT) / (ILIMITCURRENT), 10
RILIM = 20 k, RIOUT = 5.0 k,
DAC = 0.8 V, 1.25 V, 1.52 V

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 NCP4205

Table 3. NCP4205 (1+2) ELECTRICAL CHARACTERISTICS

Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter Test Conditions Min Typ Max Units
OSCILLATOR
Switching Frequency Range 240 − 1000 KHz
Switching Frequency Accuracy 240 KHz < Fsw < 1 MHz −10 − 10 %
2 Phase Operation 360 400 440 kHz
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Threshold During 2.175 2.2 2.5 V
Soft−Start

Over Voltage Threshold Above VDD/VDDNB rising 270 325 380 mV

DAC

Over Voltage Delay VDD/VDDNB rising to PWMx low 50 ns

Under Voltage Threshold Below VDD/VDDNB falling 170 325 380 mV
DAC−DROOP

Under−voltage Hysteresis VDD/VDDNB rising 25 mV

Under−voltage Delay 5.0 ms
SVI2 DAC
System Voltage Accuracy 1.2 V ≤ DAC < 1.55 V −2 2 LSB
0.8 V< DAC < 1.2 V −10 10 mV
0 V < DAC < 0.8 V −2 2 LSB
Droop Feed−Forward Current Measure on DROOP, DROOPNB pin 59 66 71 mA
Droop Falling current Measure on DROOP, DROOPNB pin 23 29 mA
Droop Feed−Forward Pulse On− 0.16 ms
Time

OVERCURRENT PROTECTION
ILIM Threshold Current Main Rail, Rlim = 20 kW 8.0 10 11 mA
(OCP shutdown after 50 ms delay)
ILIM Threshold Current Main Rail, Rlim = 20 k 13 15 16.5 mA
(immediate OCP shutdown)

ILIM Threshold Current (OCP Main Rail, RLIM = 20 K 10 mA

shutdown after 50 ms delay)
ILIM Threshold Current Main Rail, RLIM = 20 K 15 mA
(immediate OCP shutdown)

ILIM Threshold Current (OCP North Bridge Rail, Rlim = 20 kW 8.0 10 11 mA

shutdown after 50 ms delay)
ILIM Threshold Current North Bridge Rail, Rlim = 20 k 13 15 16.5 mA
(immediate OCP shutdown)

ILIM Threshold Current (OCP North Bridge Rail RLIM = 20 K, 10/N mA

shutdown after 50 ms delay) N = number of phases in PSI mode

ILIM Threshold Current North Bridge Rail, RLIM = 20 K 15/N mA

(immediate OCP shutdown) N = number of phases in PSI mode

MODULATORS (PWM COMPARATORS) FOR MAIN RAIL & NORTH BRIDGE

Minimum Pulse Width Fsw = 360 KHz 60 ns
0% Duty Cycle COMP voltage when the PWM outputs 1.3 − V
remain Low

100% Duty Cycle COMP voltage when the PWM outputs − 2.5 − V
remain High VRMP = 12.0 V

PWM Ramp Duty Cycle Matching COMP = 2 V, PWM Ton matching 1 %

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 NCP4205

Table 3. NCP4205 (1+2) ELECTRICAL CHARACTERISTICS

Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter Test Conditions Min Typ Max Units
MODULATORS (PWM COMPARATORS) FOR MAIN RAIL & NORTH BRIDGE
PWM Phase Angle Error Between adjacent phases ±5 Deg
Ramp Feed−forward Voltage 5.0 22 V
range

OCP_L#
Output Low Voltage 0.3 V
Output Leakage Current High Impedance State −1.0 − 1.0 mA
ADC
Voltage Range 0 2.0 V
Total Unadjusted Error (TUE) −1.25 +1.25 %
Differential Nonlinearity (DNL) 8−bit, no missing codes 1 LSB
Power Supply Sensitivity ±1 %
Conversion Time 8.0 ms
Round Robin 45 ms
VDD_PWRGD, VDDNB_PWRGD OUTPUT
Output Low Saturation Voltage IVDD(NB)_PWRGD = 4 mA − − 0.3 V
Rise Time External pull−up of 1 KW to 3.3 V, − 100 ns
CTOT = 45 pF, DVo = 10% to 90%
Fall Time External pull−up of 1 KW to 3.3 V, 10 ns
CTOT = 45 pF, DVo = 90% to 10%
Output Voltage at Power−up VDD_PWRGD, VDDNB_PWRGD pulled − − 1.0 V
up to 5 V via 2 KW
Output Leakage Current When VDD_ PWRGD& VDDNB_PWRGD = −1.0 − 1.0 mA
High 5.0 V

VDD_PWRDG Delay (rising) DAC = TARGET to VDD_PWRGD 5.0 ms

VDD_PWRGD Delay (falling) From OCP or OVP − 5.0 − ms
PWM, PWMNB OUTPUTS
Output High Voltage Sourcing 500 mA VCC – 0.2 V − − V
Output Mid Voltage No Load 1.9 2.0 2.1 V
Output Low Voltage Sinking 500 mA − − 0.7 V
Rise and Fall Time CL (PCB) = 50 pF, DVo = GND to VCC − 10 ns
Tri−State Output Leakage Gx = 2.0V, x = 1−2, EN = Low −1.0 − 1.0 mA
1/2 PHASE DETECTION OR NORTH BRIDGE
CSN2NB Pin Threshold Voltage 4.2 V
Phase Detect Timer 2.3 ms
SVC,SVD,SVT
VDDIO Nominal Bus voltage 1.14 1.95 V
VDDIO Current VDDIO = 1.95 V 100 mA
VIL Input Low Voltage 35 %
VIH Input High Voltage 70 %
VHYS Hysteresis Voltage 10 %
VOH Output High Voltage VDDIO−0.2 VDDIO V
VOL Output Low Voltage 0 0.2 V

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 NCP4205

Table 3. NCP4205 (1+2) ELECTRICAL CHARACTERISTICS

Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter Test Conditions Min Typ Max Units
SVC,SVD,SVT
Leakage Current −100 100 mA
Pin Capacitance 4.0 pF
Clock to data delay (Tco) 4.0 10 ns
Setup time (Tsu) 5.0 10 ns
Hold time (Thold) 5.0 10 ns
SMBUS INTERFACE, SDA, SCL
Logic High Input Voltage VIH(SDA, SCL) 2.1 V
Logic Low Input Voltage VIL(SDA, SCL) 0.8 V
Hysteresis 500 mV
SDA Output low voltage, VOL ISDA = −6 mA 0.4 V
Input Current −1.0 1.0 mA
Input Capacitance 5.0 pF
Clock Frequency 400 kHz
SCL Falling Edge to SDA Valid 1.0 ms
Time
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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 NCP4205

Table 4. SVI2 VID CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage (V) HEX
0 0 0 0 0 0 0 0 1.55000 00
0 0 0 0 0 0 0 1 1.54375 01
0 0 0 0 0 0 1 0 1.53750 02
0 0 0 0 0 0 1 1 1.53125 03
0 0 0 0 0 1 0 0 1.52500 04
0 0 0 0 0 1 0 1 1.51875 05
0 0 0 0 0 1 1 0 1.51250 06
0 0 0 0 0 1 1 1 1.50625 07
0 0 0 0 1 0 0 0 1.50000 08
0 0 0 0 1 0 0 1 1.49375 09
0 0 0 0 1 0 1 0 1.48750 0A
0 0 0 0 1 0 1 1 1.48125 0B
0 0 0 0 1 1 0 0 1.47500 0C
0 0 0 0 1 1 0 1 1.46875 0D
0 0 0 0 1 1 1 0 1.46250 0E
0 0 0 0 1 1 1 1 1.45625 0F
0 0 0 1 0 0 0 0 1.45000 10
0 0 0 1 0 0 0 1 1.44375 11
0 0 0 1 0 0 1 0 1.43750 12
0 0 0 1 0 0 1 1 1.43125 13
0 0 0 1 0 1 0 0 1.42500 14
0 0 0 1 0 1 0 1 1.41875 15
0 0 0 1 0 1 1 0 1.41250 16
0 0 0 1 0 1 1 1 1.40625 17
0 0 0 1 1 0 0 0 1.40000 18
0 0 0 1 1 0 0 1 1.39375 19
0 0 0 1 1 0 1 0 1.38750 1A
0 0 0 1 1 0 1 1 1.38125 1B
0 0 0 1 1 1 0 0 1.37500 1C
0 0 0 1 1 1 0 1 1.36875 1D
0 0 0 1 1 1 1 0 1.36250 1E
0 0 0 1 1 1 1 1 1.35625 1F
0 0 1 0 0 0 0 0 1.35000 20
0 0 1 0 0 0 0 1 1.34375 21
0 0 1 0 0 0 1 0 1.33750 22
0 0 1 0 0 0 1 1 1.33125 23
0 0 1 0 0 1 0 0 1.32500 24
0 0 1 0 0 1 0 1 1.31875 25
0 0 1 0 0 1 1 0 1.31250 26
0 0 1 0 0 1 1 1 1.30625 27
0 0 1 0 1 0 0 0 1.30000 28
0 0 1 0 1 0 0 1 1.29375 29
0 0 1 0 1 0 1 0 1.28750 2A

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Table 4. SVI2 VID CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage (V) HEX
0 0 1 0 1 0 1 1 1.28125 2B
0 0 1 0 1 1 0 0 1.27500 2C
0 0 1 0 1 1 0 1 1.26875 2D
0 0 1 0 1 1 1 0 1.26250 2E
0 0 1 0 1 1 1 1 1.25625 2F
0 0 1 1 0 0 0 0 1.25000 30
0 0 1 1 0 0 0 1 1.24375 31
0 0 1 1 0 0 1 0 1.23750 32
0 0 1 1 0 0 1 1 1.23125 33
0 0 1 1 0 1 0 0 1.22500 34
0 0 1 1 0 1 0 1 1.21875 35
0 0 1 1 0 1 1 0 1.21250 36
0 0 1 1 0 1 1 1 1.20625 37
0 0 1 1 1 0 0 0 1.20000 38
0 0 1 1 1 0 0 1 1.19375 39
0 0 1 1 1 0 1 0 1.18750 3A
0 0 1 1 1 0 1 1 1.18125 3B
0 0 1 1 1 1 0 0 1.17500 3C
0 0 1 1 1 1 0 1 1.16875 3D
0 0 1 1 1 1 1 0 1.16250 3E
0 0 1 1 1 1 1 1 1.15625 3F
0 1 0 0 0 0 0 0 1.15000 40
0 1 0 0 0 0 0 1 1.14375 41
0 1 0 0 0 0 1 0 1.13750 42
0 1 0 0 0 0 1 1 1.13125 43
0 1 0 0 0 1 0 0 1.12500 44
0 1 0 0 0 1 0 1 1.11875 45
0 1 0 0 0 1 1 0 1.11250 46
0 1 0 0 0 1 1 1 1.10625 47
0 1 0 0 1 0 0 0 1.10000 48
0 1 0 0 1 0 0 1 1.09375 49
0 1 0 0 1 0 1 0 1.08750 4A
0 1 0 0 1 0 1 1 1.08125 4B
0 1 0 0 1 1 0 0 1.07500 4C
0 1 0 0 1 1 0 1 1.06875 4D
0 1 0 0 1 1 1 0 1.06250 4E
0 1 0 0 1 1 1 1 1.05625 4F
0 1 0 1 0 0 0 0 1.05000 50
0 1 0 1 0 0 0 1 1.04375 51
0 1 0 1 0 0 1 0 1.03750 52
0 1 0 1 0 0 1 1 1.03125 53
0 1 0 1 0 1 0 0 1.02500 54
0 1 0 1 0 1 0 1 1.01875 55

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Table 4. SVI2 VID CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage (V) HEX
0 1 0 1 0 1 1 0 1.01250 56
0 1 0 1 0 1 1 1 1.00625 57
0 1 0 1 1 0 0 0 1.00000 58
0 1 0 1 1 0 0 1 0.99375 59
0 1 0 1 1 0 1 0 0.98750 5A
0 1 0 1 1 0 1 1 0.98125 5B
0 1 0 1 1 1 0 0 0.97500 5C
0 1 0 1 1 1 0 1 0.96875 5D
0 1 0 1 1 1 1 0 0.96250 5E
0 1 0 1 1 1 1 1 0.95625 5F
0 1 1 0 0 0 0 0 0.95000 60
0 1 1 0 0 0 0 1 0.94375 61
0 1 1 0 0 0 1 0 0.93750 62
0 1 1 0 0 0 1 1 0.93125 63
0 1 1 0 0 1 0 0 0.92500 64
0 1 1 0 0 1 0 1 0.91875 65
0 1 1 0 0 1 1 0 0.91250 66
0 1 1 0 0 1 1 1 0.90625 67
0 1 1 0 1 0 0 0 0.90000 68
0 1 1 0 1 0 0 1 0.89375 69
0 1 1 0 1 0 1 0 0.88750 6A
0 1 1 0 1 0 1 1 0.88125 6B
0 1 1 0 1 1 0 0 0.87500 6C
0 1 1 0 1 1 0 1 0.86875 6D
0 1 1 0 1 1 1 0 0.86250 6E
0 1 1 0 1 1 1 1 0.85625 6F
0 1 1 1 0 0 0 0 0.85000 70
0 1 1 1 0 0 0 1 0.84375 71
0 1 1 1 0 0 1 0 0.83750 72
0 1 1 1 0 0 1 1 0.83125 73
0 1 1 1 0 1 0 0 0.82500 74
0 1 1 1 0 1 0 1 0.81875 75
0 1 1 1 0 1 1 0 0.81250 76
0 1 1 1 0 1 1 1 0.80625 77
0 1 1 1 1 0 0 0 0.80000 78
0 1 1 1 1 0 0 1 0.79375 79
0 1 1 1 1 0 1 0 0.78750 7A
0 1 1 1 1 0 1 1 0.78125 7B
0 1 1 1 1 1 0 0 0.77500 7C
0 1 1 1 1 1 0 1 0.76875 7D
0 1 1 1 1 1 1 0 0.76250 7E
0 1 1 1 1 1 1 1 0.75625 7F
1 0 0 0 0 0 0 0 0.75000 80

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Table 4. SVI2 VID CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage (V) HEX
1 0 0 0 0 0 0 1 0.74375 81
1 0 0 0 0 0 1 0 0.73750 82
1 0 0 0 0 0 1 1 0.73125 83
1 0 0 0 0 1 0 0 0.72500 84
1 0 0 0 0 1 0 1 0.71875 85
1 0 0 0 0 1 1 0 0.71250 86
1 0 0 0 0 1 1 1 0.70625 87
1 0 0 0 1 0 0 0 0.70000 88
1 0 0 0 1 0 0 1 0.69375 89
1 0 0 0 1 0 1 0 0.68750 8A
1 0 0 0 1 0 1 1 0.68125 8B
1 0 0 0 1 1 0 0 0.67500 8C
1 0 0 0 1 1 0 1 0.66875 8D
1 0 0 0 1 1 1 0 0.66250 8E
1 0 0 0 1 1 1 1 0.65625 8F
1 0 0 1 0 0 0 0 0.65000 90
1 0 0 1 0 0 0 1 0.64375 91
1 0 0 1 0 0 1 0 0.63750 92
1 0 0 1 0 0 1 1 0.63125 93
1 0 0 1 0 1 0 0 0.62500 94
1 0 0 1 0 1 0 1 0.61875 95
1 0 0 1 0 1 1 0 0.61250 96
1 0 0 1 0 1 1 1 0.60625 97
1 0 0 1 1 0 0 0 0.60000 98
1 0 0 1 1 0 0 1 0.59375 99
1 0 0 1 1 0 1 0 0.58750 9A
1 0 0 1 1 0 1 1 0.58125 9B
1 0 0 1 1 1 0 0 0.57500 9C
1 0 0 1 1 1 0 1 0.56875 9D
1 0 0 1 1 1 1 0 0.56250 9E
1 0 0 1 1 1 1 1 0.55625 9F
1 0 1 0 0 0 0 0 0.55000 A0
1 0 1 0 0 0 0 1 0.54375 A1
1 0 1 0 0 0 1 0 0.53750 A2
1 0 1 0 0 0 1 1 0.53125 A3
1 0 1 0 0 1 0 0 0.52500 A4
1 0 1 0 0 1 0 1 0.51875 A5
1 0 1 0 0 1 1 0 0.51250 A6
1 0 1 0 0 1 1 1 0.50625 A7
1 0 1 0 1 0 0 0 0.50000 A8
1 0 1 0 1 0 0 1 0.49375 A9
1 0 1 0 1 0 1 0 0.48750 AA
1 0 1 0 1 0 1 1 0.48125 AB

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Table 4. SVI2 VID CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage (V) HEX
1 0 1 0 1 1 0 0 0.47500 AC
1 0 1 0 1 1 0 1 0.46875 AD
1 0 1 0 1 1 1 0 0.46250 AE
1 0 1 0 1 1 1 1 0.45625 AF
1 0 1 1 0 0 0 0 0.45000 B0
1 0 1 1 0 0 0 1 0.44375 B1
1 0 1 1 0 0 1 0 0.43750 B2
1 0 1 1 0 0 1 1 0.43125 B3
1 0 1 1 0 1 0 0 0.42500 B4
1 0 1 1 0 1 0 1 0.41875 B5
1 0 1 1 0 1 1 0 0.41250 B6
1 0 1 1 0 1 1 1 0.40625 B7
1 0 1 1 1 0 0 0 0.40000 B8
1 0 1 1 1 0 0 1 0.39375 B9
1 0 1 1 1 0 1 0 0.38750 BA
1 0 1 1 1 0 1 1 0.38125 BB
1 0 1 1 1 1 0 0 0.37500 BC
1 0 1 1 1 1 0 1 0.36875 BD
1 0 1 1 1 1 1 0 0.36250 BE
1 0 1 1 1 1 1 1 0.35625 BF
1 1 0 0 0 0 0 0 0.35000 C0
1 1 0 0 0 0 0 1 0.34375 C1
1 1 0 0 0 0 1 0 0.33750 C2
1 1 0 0 0 0 1 1 0.33125 C3
1 1 0 0 0 1 0 0 0.32500 C4
1 1 0 0 0 1 0 1 0.312875 C5
1 1 0 0 0 1 1 0 0.31250 C6
1 1 0 0 0 1 1 1 0.30625 C7
1 1 0 0 1 0 0 0 0.30000 C8
1 1 0 0 1 0 0 1 0.29375 C9
1 1 0 0 1 0 1 0 0.28750 CA
1 1 0 0 1 0 1 1 0.28125 CB
1 1 0 0 1 1 0 0 0.27500 CC
1 1 0 0 1 1 0 1 0.26875 CD
1 1 0 0 1 1 1 0 0.26250 CE
1 1 0 0 1 1 1 1 0.25625 CF
1 1 0 1 0 0 0 0 0.25000 D0
1 1 0 1 0 0 0 1 0.24375 D1
1 1 0 1 0 0 1 0 0.23750 D2
1 1 0 1 0 0 1 1 0.23125 D3
1 1 0 1 0 1 0 0 0.22500 D4
1 1 0 1 0 1 0 1 0.21875 D5
1 1 0 1 0 1 1 0 0.21250 D6

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Table 4. SVI2 VID CODES

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage (V) HEX
1 1 0 1 0 1 1 1 0.20625 D7
1 1 0 1 1 0 0 0 0.20000 D8
1 1 0 1 1 0 0 1 0.19375 D9
1 1 0 1 1 0 1 0 0.18750 DA
1 1 0 1 1 0 1 1 0.18125 DB
1 1 0 1 1 1 0 0 0.17500 DC
1 1 0 1 1 1 0 1 0.16875 DD
1 1 0 1 1 1 1 0 0.16250 DE
1 1 0 1 1 1 1 1 0.15625 DF
1 1 1 0 0 0 0 0 0.15000 E0
1 1 1 0 0 0 0 1 0.14375 E1
1 1 1 0 0 0 1 0 0.13750 E2
1 1 1 0 0 0 1 1 0.13125 E3
1 1 1 0 0 1 0 0 0.12500 E4
1 1 1 0 0 1 0 1 0.11875 E5
1 1 1 0 0 1 1 0 0.11250 E6
1 1 1 0 0 1 1 1 0.10625 E7
1 1 1 0 1 0 0 0 0.10000 E8
1 1 1 0 1 0 0 1 0.09375 E9
1 1 1 0 1 0 1 0 0.08750 EA
1 1 1 0 1 0 1 1 0.08125 EB
1 1 1 0 1 1 0 0 0.07500 EC
1 1 1 0 1 1 0 1 0.06875 ED
1 1 1 0 1 1 1 0 0.06250 EE
1 1 1 0 1 1 1 1 0.05625 EF
1 1 1 1 0 0 0 0 0.05000 F0
1 1 1 1 0 0 0 1 0.04375 F1
1 1 1 1 0 0 1 0 0.03750 F2
1 1 1 1 0 0 1 1 0.03125 F3
1 1 1 1 0 1 0 0 0.02500 F4
1 1 1 1 0 1 0 1 0.01875 F5
1 1 1 1 0 1 1 0 0.01250 F6
1 1 1 1 0 1 1 1 0.00625 F7
1 1 1 1 1 0 0 0 OFF F8
1 1 1 1 1 0 0 1 OFF F9
1 1 1 1 1 0 1 0 OFF FA
1 1 1 1 1 0 1 1 OFF FB
1 1 1 1 1 1 0 0 OFF FC
1 1 1 1 1 1 0 1 OFF FD
1 1 1 1 1 1 1 0 OFF FE
1 1 1 1 1 1 1 1 OFF FF

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1 2 3 4 5 6 7 8
STATE

DC_IN

VDDIO
Boot_VID

SVC

SVD

SVT VOTF
COMPLETE Telemetry Telemetry

ENABLE/ENABLE_NB

VDD&VDDNB

VDD_PWGD

VDDNB_PWRGD
9
RESET_L

10
PWROK

Figure 3. Start−Up Timing Diagram

Table 5. SVD SERIAL PACKET BIT DESCRIPTION

Bit Default Description
1:5 11000 Start code
6 1 VDD domain selector bit, if set then the following two data bytes contain the VID for VDD, the PSI state for VDD
and the loadline slope trim and offset

7 0 VDDNB domain selector bit, if set then the following two data bytes contain the VID for VDD, the PSI state for
VDDNB and the loadline slope trim and offset

8 0
9 0 ACK
10 0 PSI0 power state indicator level 0. When this signal is asserted the NCP4205 is in a lower power state, and
phase shedding is initialized.

11:17 XXXXXXX VID code [7:1] see Table 4

18 0 ACK
19 X VID code LSB [0] see Table 4
20 PSI1, when this bit is asserted the NCP4205 is in a low power state and operated in diode mode emulation mode
21 1 TFN, this is an active high signal that allows the processor to control the telemetry functionality of the NCP4205.
22:24 011 Loadline slope Trim [2:0]
25:26 10 Offset Trim [1:0]
27 0 ACK

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 NCP4205

1 9 10
SVC

SVD 1 1 0 0 0

DOMAIN 0+ VID CODE BIT 7:1

START SEQUENCE PSI0
SELECTION ACK

18 27 STOP

ACK PSI1 TFN LOADLINE OFFSET

VID ACK
SLOPE TRIM TRIM
CODE
BIT 0

Figure 4. SVI2 Timing Diagram

SVI2 Interface Telemetry
The NCP4205 is designed to accept commands over The TFN bit along with the VDD and VDDNB domain
AMD’s SVI2 bus. The communication is accomplished selectors are used to change the functionality of the
using 3 lines, a data line SVD, a clock line SVC and a telemetry. See table below for description.
telemetry line SVT. The SVD line can be used not only to set
the voltage level of the Main rail and North bridge rail, but Table 7. TELEMETRY FUNCTIONALITY
can also set the load line slope, programmed offset and also TFN = 1
the PSI (power state indicator bits). The SVT line from the VDD VDDNB Description
NCP4205 communicates voltage, current and status updates
0 1 Telemetry is in voltage and current
back to the processor. mode. V&I is sent back for both VDD and
VDDNB rails
Power state Indicator (PSI)
The SVI2 protocol defines two PSI levels, PSI0 and PSI1. 0 0 Telemetry is in voltage only mode. Volt-
age information is sent back for both
These are active low signals which indicate when the VDD and VDDNB rails
NCP4205 can enter low power states to improve system
1 0 Telemetry is disabled
efficiency and performance. Increasing levels of PSI state
indicates low current consumption of the processor. 1 1 Reserved for future use
It is possible for the processor to assert PSI0 and PSI1 out
of order i.e. to enter PSI1 prior to PSI0 however; PSI0 Loadline Slope
always takes priority over PSI1. Within the SVI2 protocol the NCP4205 controller has the
With increasing load current demand the number of active ability to manipulate the loadline slope of both the VDD and
phases increase instantaneous. The NCP4205 can potentially VDDNB rails independently of each other, when Enable and
change from single−phase to user−configured multiphase PWROK are asserted. Loadline slope trim information is
operation in a single step, depending on PSI state. transmitted in 3 bits (22:24) over the SVD packet. Please see
PSI0 is activated once the system power is in the region of table below for description.
20−30 Amps, in this mode the NCP4205 controller reduces
the number of phases in operation thus reducing switching Table 8. LOADLINE SLOPE THROUGH SVI2
losses of the system. If the current continues to drop to 1−3 Loadline slope
Amps PSI1 is asserted and the NCP4205 enters diode trim [0:2] Description
emulation mode, operating in single phase mode. See below 000 Remove all LL droop from output
table for PSI mode operation.
001 Initial LL slope −40%
Table 6. POWER STATES 010 Initial LL slope −20%
PSI0 PSI1 State 011 Initial LL slope (38.7% default)
0 0 PSI1 100 Initial LL slope +20%
0 1 PSI0 101 Initial LL slope +40%
1 0 Full current draw 110 Initial LL slope +60%
1 1 Full current draw 111 Initial LL slope +80%

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 NCP4205

Offset Trim Table 10. SVT PACKET INFORMATION

Within the SVI2 protocol the NCP4205 controller has the
Parameter Value Units
ability to manipulate the offset of both the VDD and
VDDNB rails independent of each other, when Enable and Number of voltage Bits 9 Bits
PWROK are asserted. Descriptions of offset codes are Maximum reporting Voltage 3.15 V
described below. Minimum reported Voltage 0.00 V

Table 9. OFFSET TRIM THROUGH SVI2 Voltage resolution 6.25 mV

Offset Trim [1:0] Description Voltage accuracy from 1.2 V ±1 LSB
to 800 mV
00 0 mV offset
Voltage accuracy for volt- ±2 LSB
01 Initial offset −25 mV ages greater than 1.2 V and
10 Use initial offset (default) less than 800 mV

11 Initial offset +25 mV Recommended voltage mov- 50 ms

ing average window size

SVT Serial Packet Minimum voltage only 20 KHz

telemetry reporting rate
The NCP4205 has the ability to sample and report voltage
and current for both the VDD and VDDNB domain. This Number of bits in current data 8 Bits
information is reported serially over the SVT line which is Max reported current 100 % of IDD spike _ocp
clocked using the processor driven SVC line. When the (FFh = OCP)
PWROK is de−asserted, the NCP4205 is not collecting or Max reported current (00h) 0 % of IDD spike _ocp
reporting telemetry information. When PWROK is asserted,
the telemetry information reported back is as described If the NCP4205 is configured in voltage and current mode,
below. If the NCP4205 is configured in voltage only then the samples voltage and current information for VDD
telemetry, then the sampled voltage for VDD and the is sent out in one SVT telemetry packet, while the voltage
sampled voltage for the VDDNB are sent together in every and current information for the VDDNB domain is sent out
SVT telemetry packet. in the next SVT telemetry packet. The telemetry report rate,
while the NCP4205 is in current and voltage mode, is double
that which is observed in voltage only mode. The reported
voltage and current are moving average representations.

Table 11. TELEMETRY DATA BITS INFORMATION

Bit Time Description Bit Time
1 SVT1 See Table 12 for description 11 Voltage Bit 0
2 SVT0 12 Voltage Bit 8 in V only mode, 0’ in V & I mode
3 Voltage Bit 8 13 Voltage or current Bit 7
4 Voltage Bit 7 14 Voltage or current Bit 6
5 Voltage Bit 6 15 Voltage or current Bit 5
6 Voltage Bit 5 16 Voltage or current Bit 4
7 Voltage Bit 4 17 Voltage or current Bit 3
8 Voltage Bit 3 18 Voltage or current Bit 2
9 Voltage Bit 2 19 Voltage or current Bit 1
10 Voltage Bit 1 20 Voltage or current Bit 0

Table 12. SVT1, SVT0 DESCRIPTION

SVT1, SVT0 Description
0,0 Telemetry packet belongs to the VDD domain and in V&I mode.
0,1 Telemetry packet belongs to the VDDNB domain and in V&I mode.
1,0 VOTF Complete, a stop immediately follows these two bits during the next SVC high period. Telemetry data does
not follow this bit configuration

1,1 Telemetry package in voltage representation only. (default)

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 NCP4205

SVI2 VR to Processor Data Communication

As described previously, the NCP4205 has the ability to collectively, at the requested stepped−up VID voltage. The
send digitally encoded voltage and current values for the VOTF complete mechanism is not used for VID changes to
VDD and VDDNB domains to the processor, it also has the lower or for repeated VID codes.
capability to send VID on the Fly (VOTF) complete VOTF Complete is transmitted as an SVT packet. Since
mechanism. The processor uses this information as an a VOTF request could apply to one or two voltage domains,
indicator for when the VDD, VDDNB are independently, or rules are suggested below to handle these cases.

Table 13. VTOF RULES

VID Change Offset Change Loadline Change VOTF Timing Force or Decay Change
UP Unchanged Unchanged After slewing Force voltage change
Down Unchanged Unchanged NO VOTF Voltage Decay
X UP Unchanged After slewing Force voltage change
X Down Unchanged After slewing Force voltage change
X Unchanged UP After slewing Force voltage change
X Unchanged Down After slewing Force voltage change

SVC

STOP
SVD

SVT

VID−RLL*IOUT+−OFFSET−TOB

VDD or
VDDNB
Tsc
Slew Rate Measured here

Figure 5. A Typical VID−UP Transaction

*Max Tsc = 5 ms
• Telemetry takes priority over VOTF Complete signals NCP4205 waits to send the telemetry until after the
• VOTF complete can be sent if the net voltage change is SVD packet has stopped transmitting.
0 or negative • If the processor stops sending the SVD packet while the
• VOTF Complete is only used to indicate that a rail(s) NCP4205 is sending telemetry then no action has to be
has finish slewing to a higher voltage. taken, the NCP4205 shifts in the new SVD packet and
finishes sending the telemetry while the processor is
• If a VOTF request for a higher voltage is sent for both
sending the SVD packet.
VDD and VDDNB rails, but only domain will go up in
voltage then the returned VOTF Complete will indicate • SVT packets are not sent while PWROK is deasserted
that the increasing domain has finished slewing • The NCP4205 will not collect or send telemetry data
• If the processor starts a VOTF request but the VOTF is when telemetry functionality is disabled by the TFN bits
incomplete then the NCP4205 will not sent the VOTF The following timing diagrams cover the SVC, SVD and
Complete sequence until after the new VOTF request. SVT timing when PWROK is asserted and data is being
• If the processor is sending a SVD packet when the transmitted, the table that follows defines the min and max
NCP4205 is sending telemetry packet to send, then the value for each timing specification.

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 NCP4205

SVC

SVD
HiZ HiZ

TSTART TLow THigh TQuiet TSetup THold TQuiet TSetup TStop

TPeriod
THold
TZack

SVC

SVD

TSetup THold

Figure 6. SVD & SVC Timing

SVC

SVT

Tsetup Tstop

Figure 7. SVT Stop Timing

SVC

SVD/SVT

TReStart

Figure 8. SVD or SVT Re−Start Timing

SVC

SVD

SVT

TSVD−STOPto SVT−START TRISING EDGE SVCto SVD−START

Figure 9. SVT Start and Stop Timing

Slew Rate Programming Table 14. SLEW RATE OPTIONS
Slew rate is programmable on power up; a resistor from
Slew Rate Resistance (W)
the SR pin to ground sets the slew rate. Each rail can be
programmed independently between 10 mV/ms, see 10 mv/ms 10 K
Table 14 for resistor values. 20 mv/ms 25 K
30 mv/ms 45 K

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 NCP4205

Boot Voltage Programming High Performance Voltage Error Amplifier

The NCP4205 has a VBOOT voltage register that can be A high performance error amplifier is provided for high
externally programmed for both Main Rail and North Bridge bandwidth transient performance. A standard type 3
boot−up output voltage. The VBOOT voltage can be compensation circuit is normally used to compensate the
programmed when PWROK is deasserted, through the logic system.
levels present on SVC and SVD. The table below defines the
Boot−VID codes Differential Current Balance Amplifier
In NCP4205, the inductor DCR current sensing method is
Table 15. BOOT VOLTAGE PROGRAMMING used, to extract accurate per phase current information. For
SVC SVD Boot Voltage this purpose RCSN and CCSN is connected in parallel to the
inductor as shown in Figure 10.
0 0 1.1

CSREF
0 1 1.0

CSPx
1 0 0.9 RCSN CCSN
1 1 0.8

VOUT
Address Programming
The NCP4205 supports 8 possible SMBus Addresses. DCR LPHASE
1 2
ADD pin is used to set the SMBus Address. On power up a
10 mA current is sourced from this pin through a resistor Figure 10. Inductor DCR Current Sensing
connected to this pin and the resulting voltage is measured. The voltage across CCSN is used by a low offset
The Table below provides the resistor values for each differential amplifier to sense the phase current. The inputs
corresponding SMBus Address. The address value is CSPx and CSNx are high impedance inputs, but it is
latched at startup. recommended that the external filter resistor RCSN should
not exceed 10 kW to avoid offset issues from leakage
Table 16. SMBUS ADDRESS
current. It is also recommended that voltage sense element
Resistor Value SMBus (Hex)
(DCR) should not be less than 0.5 mW for accurate current
10 k 20 balance.
25 k 21 The external filter’s time constant should match the
L/DCR time constant, however, fine tuning is not required.
45 k 22
The expression for RSCN can be written as:
70 k 23
RCSN + L (eq. 1)
95 k 24 CCSN DCR
125 k 25 The accuracy of the per−phase current sensing scheme
depends on the variation of:
165 k 26
1. DCR with temperature.
220 k 27 2. Manufacturing tolerances of RCSN and CCSN.
3. Change of inductance of L with bias current.
Remote Sense Amplifier Changes in DCR vary the dc gain whereas changes in the
A high performance high input impedance true L, CCSN and RCSN vary the ac gain. The individual phase
differential amplifier is provided to accurately sense the current information feeds into the individual PWM
output voltage of the regulator. The VSP and VSN inputs comparators. This will dynamically influence the PWM ON
should be connected to the regulator’s output voltage sense time and by extension help balance load across active
points. The remote sense amplifier takes the difference of phases.
the output voltage with the DAC voltage and adds the droop
Example:
voltage to: VDIFF =
• L = 0.36 mH
ǒVVSP * VVSNǓ ) ǒ1.3 V * VDACǓ ) ǒVDROOP * VCSREFǓ • DCR = 1.15mW
This signal then goes through a standard error • Suppose CCSN=0.047mF
compensation network and into the inverting input of the By using Equation 1 the value of RCSN can be calculated as
error amplifier. The non−inverting input of the error follows:
amplifier is connected to the same 1.3 V reference used for
the differential sense amplifier output bias. 0.36 m
R CSN + + 6.66 kW
0.047 m 1.15 m

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 NCP4205

The individual phase current is summed into to the PWM I OUT DCR V * V CSCOMP
comparator feedback in this way current is balanced is via + CSREF (eq. 4)
R Ph R CS
a current mode control approach.
Rearranging Equation 4, we can return an equation to
Total Current Sense Amplifier determine the system droop:
The total current information in all the phases is required
to produce voltage droop (AVP) and to monitor total output V CSCOMP * V CSREF + − ǒ Ǔǒ R CS
R PH
I OUT DCRǓ
current. This monitoring will enable the AVP i.e. variation
in output voltage with the load current (Load line) and also The droop can be adjusted by changing the value of the
to turn off switching if total current exceeds the set limit RPH resistor to make the ratio of the total current signal to
(Over Current Protection). The currents from all phases are output current equal to the desired Load line as follows:
summed together in a single temperature compensated total V CSCOMP * V CSREF R
+ − CS DCR
current signal. I OUT R PH
The Rref resistors average the voltages at the output sides
The above expression sets the impedance gain RCSA of the
of the inductors to create a low impedance reference voltage
regulator which is also the DC load line.
CSREF. The RPH resistors sum currents from the switch
nodes to the CSSUM pin. V CSCOMP * V CSREF
+ R CSA
I OUT

R CS
R CSA + − DCR (eq. 5)
R PH
For accurate current information it is essential that the
inductor voltage contains only the inductor voltage
component across the DCR while cancelling any voltage
component across the inductance L. In order to achieve it the
filter network components must be selected in such a way
that the pole frequency of CSCOMP filter is equal to the zero
of the output inductor. In this way total current signal is
proportional to component of inductor voltage caused by
DCR drop and thus proportional to inductor current.
Connecting CCS2 in parallel with CCS1 allows the fine tuning
of the pole frequency. It is best to fine tune this filter
frequency during transient testing.
DCR@25oC
fz + (eq. 6)
2pL
(eq. 7)
fP + 1
Figure 11. A Typical Total Current Sense Amplifier
for North Bridge Rail ǒ
2p R CS2 )
RCS1RTH@25oC
RCS1)RTH@25oC
Ǔ ǒC CS1 ) C CS2Ǔ
KCL at CSSUM pin will give
At fZ = fP;
ȍ V SW * V CSSUM
ȍ V CSSUM * V CSCOMP
N N
+ C CS + L (eq. 8)
Ph1
R PH Ph1
R CS DCR R CS
Where An NTC Thermistor (RTH) is placed in the feedback
R CS1R th network of total current sense amplifier. This Thermistor
R CS + R CS2 ) (eq. 2) must be placed near the phase inductor to sense the inductor
R CS1 ) R th
temperature and compensates both the DC gain and the filter
Due to operational amplifier operation it is known that time constant for the DCR change with temperature. The
VCSSUM=VCSREF values of RCS1 and RCS2 are set based on the effect of
temperature on both the Thermistor and inductor.
ȍ VSW *R VCSREF + ȍ VCSREF R* VCSCOMP(eq. 3)
N N

Ph1 PH Ph1 CS Load Line Programming:

Iout is divided evenly between all phases, and the The Load line is created by the voltage between DROOP
resulting DC voltage across each inductor is (Iout/N) x DCR. and the CSREF pins. If the voltage between CSCOMP and
As the voltage drop across inductor is output current times CSREF is larger than the desired Load line it should be
the DCR of the inductor, it can be written as: divided down to correct value for the Load line at the Droop

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 NCP4205

pin by a resistor divider between CSCOMP and CSREF. The RPH Selection & RCS Calculation:
resistor divider consists of an external RDROOP whose value The selection of Rph is an important task as it will set the
is fixed to 1 kW and an internal variable 10 kW resistor. This gain of the current summing Amplifier. To ensure the current
internal 10 kW resistor can be programmed through SMBUS monitored is tracked correctly, there are two conditions that
or SVI2 interfaces to do the AMD dynamic Load line need to be fulfilled:
attenuation settings. The default value of this resistor is 1. The bandwidth of the current summing
3.8 kW which corresponds to 38.7% Load line slope. The amplifier must be equal or greater than the
Load line slope can be programmed by setting bits 0:2 in the three times of the switching frequency.
Load line register 0xE4 as shown in Table 3. Therefore, the gain of the current summing
Amplifier must not exceed the recommended
Table 17. LOAD LINE SLOPE PROGRAMMING SMBUS calculated maximum limit.
Load line Slope Trim[0:2] Description 2. The current the CS amplifier has to drive
000 Remove all LL Droop should not exceed 500 mA.
001 LL slope of 12.9% Note:
The above mentioned conditions are recommended for
010 LL slope of 25.8%
proper operation under all circumstances. These should be
011 LL slope (default 38.7%) taken as an advisable design practice. However, considering
100 LL slope of 51.6% the low DCR inductors that are being used by end market
101 LL slope of 64.8%
which may restrict the selection of certain parameters
(specially for load lines greater than 1 mW) in the light of
110 LL slope of 77.4%
above mentioned criteria, in those cases some deviation
111 LL slope of 90.2% around these recommendations may be acceptable.
Here is a quick example in
From the discussion above and Equation 8 the Load line
expression for NCP4205 can be written as follows: Table 18. A TYPICAL SYSTEM EXAMPLE

LL +
R CS
R PH
DCR ǒ103.87
k)1k
k
Ǔ Component
fSW
Value
400
Unit
kHz
RDROOP 1 kW
R
LL + CS DCR 0.352 RTH 220 kW
R PH
Rearranging above expression we can write expression RCS1 165 kW
for RPH as follows: RCS2 73.2 kW
R DCR 1.15 mW
R PH + CS DCR 0.352 (eq. 9)
LL Required Load Line 2 mW
The design parameters are:
• L = 0.36 mH Check for Condition 1:
• DCR = 1.15 mW The expression of minimum bandwidth can be written as
follows:
CSSUM
BW + 3 f SW (eq. 10)
_
CSCOMP It is known that the unity gain BW of the amplifier is
+
10 MHz. Therefore, the expression for maximum allowed
gain can be written as:
Gain max + 10 6 (eq. 11)
CSREF BW REQUIRED
The gain of the total current sense amplifier is decided by
the ratio of RCS and RPH. By using Equation 14 the
1kW Cdroop maximum allowed gain is 8.33.
The value of RCS can be calculated as follows:
R CS R TH
R CS + R CS2 )
R CS1 ) R TH
DROOP
Internal10kW to
accommodate
AMD’s Load line 73.2 k 220 k
Attenuation R CS + 165 k )
73.2 k ) 220 k
Figure 12. DROOP Network

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 NCP4205

R CS + 220 kW how Load line variations can affect the selection of

As we know that from Equation 12 compensation components.
Substituting the values of DCR and LL in the inequality
R CS
R PH + DCR 0.352 expression above we can estimate the RCS values for Load
LL lines of 2 mW and 1 mW as follows:
Substituting corresponding values above the value of Rph
R CS(2mW) w 395.26 kW
can be calculated as follows:
R PH + 44.528 kW R CS(1mW) w 210 kW
If we select the above calculated value as Rph then the
gain of the current sense amplifier can be written as: Current Sense Amplifier Design Example:
R CS
The user should choose RTH near to the calculated value
220 k
Gain + + +5 of RCS. Thus for 1 mW Load Line the nearest available
R PH 44.528 k
Thermistor value will be 220 kW. Similarly for 2 mW Load
The calculated gain is well below the maximum allowed line the nearest available Thermistor value will be 470 kW.
gain of 8.33. Therefore condition 1 is satisfied. The design parameters are:
Check for Condition 2: • L = 0.36 mH
The worst case driving current for the above example • DCR = 1.15 mW
would be: • RPH = 80 kW
V IN
Current + NumberOfPhases (eq. 12) CCS Calculation:
R PH
We can calculate CCS by using Equation 11 below:
Current + 13.2 NumberOfPhases For 2 mW Load Line:
44.5 k
0.36 m
Current + 2.966 mA NumberOfPhases C CS + + 792 pF
1.15 m 395.26 k
As 2.966 mA < 500 mA therefore the calculated value of
Rph will be good enough for a single phase rail. However for For 1 mW Load Line:
multiphase rail this value is too small and needs to be
C CS + 1.49 nF
increased until the maximum current driven by CS
Amplifier is less than 500 mA. Thus depending upon the As discussed earlier CCS is divided between CCS1 and
number of phases the value of Rph to limit the CS amplifier’s CCS2 which allows fine tuning specially during transient
maximum driving current to 450 mA (to give extra headroom testing.
for a 500 mA maximum specification) can be written as:
DCR Temperature Compensation:
R PH w 13.2 NumberOfPhases When the DCR is used as a current sense element the
450 m
designer needs to compensate for the temperature changes
From the above inequality the minimum value of RPH for of the inductor’s winding. The copper has a well known
a two phase and four phase rail is 58.6kW & 117.33kW temperature coefficient TC of 0.39% /°C. The value of RCS
respectively. It is always a good idea to select a RPH value needs to be designed in such a manner that it has an equal and
above these minimum calculated values. opposite percentage change in resistance to that of DCR. In
In the calculation below we have selected the value of RPH this way it will cancel the temperature variation of the
for a two phase rail to be greater than or equal to 80kW. This inductor DCR.
is to avoid any amplifier saturation and BW issues The following procedure and equations will give rise to
accompanied by layout of the board and other non the values of RCS1, RCS2 and RTH (at 25°C) for the selected
linearities. RCS value.
R PH w 80 kW 1. Select an NTC (negative temperature coefficient)
Thermistor close to selected RCS. The Thermistor
From Equation 12 it can be written as should have an initial tolerance of better than 5%.
R CS Examples of such Thermistors are
DCR 0.352 w 80 k
LL
For 1 mW Load Line:
80 k LL
R CS w NCP18WM224J03RB: It is a NTC 220 kW (at 25°C)
DCR 0.352
Thermistor.
241.5 k LL
R CS w
DCR For 2 mW Load Line:
All the calculations will be made for Load line values of NCP18WM474p03RB. It is a NTC 470 kW (at 25°C)
2 mW and 1 mW respectively. This will give us an idea about Thermistor.

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 NCP4205

Figure 13. Variation in required Rth with increase in the Load Line

2. The next step is to calculate the relative resistance The relative values for RCS1, RCS2 and RTH are called
of the selected Thermistor at two temperatures. rCS1, rCS2 and rTH respectively. These values are calculated
The temperatures that work well for this purpose by using the expressions below:
are 50°C and 90°C. These relative resistance ratios (A * B)r 1r 2 * A(1 * B)r 2 ) B(1 * A)r 1
are called A and B as follows: r CS2 + (eq. 17)
A(1 * B)r 1 * B(1 * A)r 2 * (A * B)
R TH(50o C) (1 * A)
A+ (eq. 13) r CS1 + (eq. 18)
R TH(25o C) 1 * A
1*r cs2 r1*r cs2
R TH(90o C)
B+ (eq. 14)
r TH + 1 (eq. 19)
R TH(25o C) 1 * 1
From the datasheets of the Thermistors the values of A and 1*rcs2 rcs1
B can be calculated as follows: Where
146.215 k A = 0.311
A+ + 0.311
470 k B = 0.0634
29.828 k
r1 = 0.9112
B+ + 0.0634 r2 = 0.7978
470 k
Using the above values and Equations 17, 18 and 19 the
3. Find the relative value of RCS required for each of
values of rCS1, rCS2 and rTH are calculated as follows:
these temperatures. This is based on the percentage
rcs2 = 0.738996
temperature change needed, which is initially
rcs1 = 0.340186
0.39% /°C. These are called r1 and r2 respectively
rTH = 1.121334
and can be calculated as follows:
r1 + 1 (eq. 15)
Calculation of RTH:
1 ) TC (T 1 * 25oC) Calculate the required value of RTH by using the
1 expression below:
r2 + (eq. 16)
1 ) TC (T 2 * 25oC) R TH + r TH R CS (eq. 20)
Where
T1 = 50°C For 2 mW Load Line:
T2 = 90°C R TH + 1.121334 395.26 k + 442.7 kW
TC = 0.0039 The closest value to 442.7 kW is 470 kW. Therefore, we
Substituting above values in Equations 15 and 16 the values select a NTC Thermistor of value 470 kW.
of r1 and r2 can be calculated as follows:
For 1 mW Load Line:
r1 + 1 + 0.9112
1 ) 0.0039 (50 * 25) R TH + 235.41 kW

r2 + 1 + 0.7978
1 ) 0.0039 (90 * 25)

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 NCP4205

The closest value to 235.41 kW is 220 kW. Therefore, we Substituting values in Equation 22
select a NTC Thermistor of value 220 kW.
For 2 mW Load Line:
Calculation of Scaling Factor R CS1 + 395.26 k 1.06 0.34 + 142.5 kW
Compute a scaling factor k based on the ratio of the actual
Thermistor used relative to the computed one. For 1 mW Load Line:
R TH(ACTUAL) R CS1 + 69 kW
k+ (eq. 21)
R TH(CALCULATED)
Substituting the values in Equation 21 the value of k can Calculation of RCS2
be calculated as: The expression of RCS2 can be written as
R CS2 + R CS ǒ(1 * k) ) (k r 2)Ǔ (eq. 23)
For 2 mW Load Line:
470 k Substituting values in Equation 23
k+ + 1.06
442.7 k
For 2 mW Load Line:

For 1 mW Load Line: R CS2 + 395.6 k ((1 * 1.06) ) (1.06 0.738)) + 285.733 kW

k + 0.936
For 1 mW Load Line:
Calculation of RCS1 R CS2 + 158.5 kW
The value of RCS1 can be calculated by using Equation 22 Finally we can select the closest ±1% resistor values for
below: RCS1 and RCS2.
R CS1 + R CS k r cs1 (eq. 22)

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 NCP4205

Programming Droop and DAC Feed Forward R DROOP + C OUT_TOTAL LL 453.6 10 6

Programming Rdroop sets the gain of the DAC
feed−forward and Cdroop provides the time constant to Importance of Droop Filter
cancel the time constant of the system per the equations In the absence of a droop filter the droop that would appear
below. Cout_total is the total output capacitance of the will also include voltage due to current in to the output
system design. capacitances (due to increasing output voltage). As it is not
Depending on the load current the output capacitors will the load current therefore, must not be allowed to affect the
charge to an output voltage with a time constant of COUT * output voltage.
LL. The droop filter needs to have the same time constant to
Note: It is recommended that RDROOP be kept constant at
cancel the effect of current in the output capacitances.
1 kW. This is required to keep the SVI2 loadline % offsets
Therefore, it can be written as
accurate. They currently range from −40% up to +80%. If
C OUT LL RDROOP is not 1 kW then these percentages will not be
C DROOP + (eq. 24)
R DROOP correct.

DIFF

VSS
DACFF VDD
DAC
& GND
DIFFAMP
VCC
DROOP CSREF
DROOP
1.3V

RDROOP CDROOP
CSCOMP

RCS CCS
RPH CSSUM
CS
CSREF AMP

NCP4205
DCR

CBULK
Rdroop=(Cout_total)*loadline*453.6*106 (Note)
Cdroop=(loadline*(Cout_total))/Rdroop
Figure 14. Droop Pin RC

Programming Current Limit For 2 mW Load Line:

The current limit of the converter is programmed with a Suppose the maximum current limit is 66 A. For a load
resistor RILIM between ILIM and CSCOMP pins. The ILIM line of 2 mW and load current of 66 A it can be written as:
pin’s voltage is a buffered replica of CSREF voltage. The
current in RILIM is mirrored internally to the current limit CSREF * CSCOMP + I L LL + 66
0.352
ǒ 2m
Ǔ
0.352
+ 375 mV
comparator and to the IOUT pin. The current in the IOUT
pin is compared with an internal 10 mA reference current. If Using Equation 25
current IILIM in resistor RILIM exceeds 10 mA then it means 375 m
that load current exceeds the maximum current limit and R ILIM + + 37.5 kW
10 m
current limit protection will be tripped.
Similarly using Equation 26
Setting the Value of RILIM: 395 k
The expressions for RILIM can be written as (66 1.15 m)
80 k
R ILIM + + 37.5 kW
(CSREF * CSCOMP)@ILIM 10 mA
R ILIM + (eq. 25)
10 mA Thus by selecting 37.5 kW as RILIM a current limit of 66 A
RCS will be set.
(I OUT DCR)
RPH
Or R ILIM + (eq. 26)
10 mA

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 NCP4205

For 1 mW Load Line: The maximum current limit is 66 A. This violates the
Suppose the maximum current limit is 33 A. For a load maximum allowable current limit and over current
line of 1 mW and load current of 33 A it can be written as: protection must be tripped to indicate an over current event.
LL + 93.75 mV The current in resistor RILIM can be calculated as:
CSREF * CSCOMP + I L
0.352
397.7 m
Using Equation 25 I LIM + + 10.6 mA
37.5 k
R ILIM + 9.375 kW This 10.6 mA will be compared against the reference
Similarly using Equation 26 10 mA in the internal current comparator and the open drain
over current protection will be tripped.
R ILIM + 9.96 kW
Thus by selecting 9.96 kW as RILIM a current limit of 33 A RIOUT SELECTION:
will be set. The IOUT pin sources a current equal to ILIM sink current
gained by the IOUT Current Gain of 10. The voltage on the
CSREF IOUT pin is monitored by the internal A/D converter and
should be scaled with an external resistor to ground such that
CSSUM
a load current equal to IOUT max generates a 2 V signal on
the IOUT pin. The IOUTmax is the maximum target rated
_
current of the application.
CSCOMP
R IOUT + 2 (eq. 27)
+
10 ǒIRILIM@IOUTmaxǓ
From Equation 26 it can be written as
RCS
RILIM
ǒIOUTmax DCRǓ
RPH
I RILIM@IOUTmax +
R ILIM
Substituting above in Equation 27 the value of RIOUT can
1
be calculated as follows:
ILIM 2 R ILIM
R IOUT +
ǒ Ǔ
(eq. 28)
RCS
10 DCR I OUTmax
RPH
IOUT

ILIM X 10
It is known that
ILIM X 1 DCR = 1.15 mW
RPH = 80 kW
RIOUT
The value of RIOUT for 2 mW and 1 mW Load lines is
calculated as follows:
_
For 2 mW Load Line:
10 mA
+ OCP _ L • RILIM = 37.5 kW
Internal Current
• Target IOUTmax = 55 A
Comparator • RCS = 395 kW
Figure 15. Maximum Current setting Resistor Substituting above values in Equation 28
RIOUT and Current Limit Resistor RILIM
2 37.5 k
R IOUT + + 68.226kW
Over Current Protection 10 395k 1.15 m 0.352 55
The difference between CSREF and CSCOMP is used as 80k
a differential input for current limit comparator. The current For 1 mW Load Line:
limit is programmed by RILIM. Suppose a load current of
70 A flows then it can be written as:
• RILIM = 9.96 kW
• Target IOUTmax = 30 A
LL + 70 2m
CSREF * CSCOMP + I L
0.352 0.352
+ 397.7 mV • RCS = 210 kW

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 NCP4205

Substituting above values in Equation 28 of 4.5 V. If the pin is tied to VCC, its voltage is above the
R IOUT + 62.488kW threshold. Otherwise, an internal current sink pulls the pin
to GND, which is below the threshold. After this time, if the
Phase Detection Sequence remaining CSN outputs are not pulled to VCC, the 50 mA
During start−up, the number of operational phases and current sink is removed. If the CSNs are pulled to VCC, the
their phase relationship is determined by the internal 50 mA current source is removed after the phase detection
circuitry monitoring the CSN Pins. Normally, NCP4205 period, and the PWM outputs are driven into a high
operates as a 1+2−phase PWM controller. Connecting impedance state.
CSN2NB pin to VCC programs 1+1−phase operation, also The PWM outputs are logic−level devices intended for
it is possible to disable the main rail by pulling CSN1 to VCC driving fast response external gate drivers such as the
however phase one of the north bridge rail cannot be NCP5901 and NCP5911. Because each phase is monitored
disabled. independently, operation approaching 100% duty cycle is
Prior to soft start, while ENABLE is high, CSN2NB as possible. In addition, more than one PWM output can be on
well as CSN1 pins sink approximately 50 mA. An internal at the same time to allow overlapping phases.
comparator checks the voltage of each pin versus a threshold

Table 19. NCP4205 PHASE CONFIGURATION

Programming Pin CSNXNB Unused Pins
1+1 Connect CSN2NB to VCC through a 2K resistor. Float: PWM2NB
All other CSN pins connected normally Ground: CSP2NB

0+2 Connect CSN1, VCC through a 2K resistor, Float: PWM1, ILIM, DIFFOUT, COMP, and CSCOMP
all other CSN pins connected normally Ground: CSP1, IOUT, DROOP, FB, CSSUM AND VDD

0+1 Connect CSN1 and CSN2NB to VCC through a 2K Float: PWM1, PWM2NB ILIM, DIFFOUT, COMP and CSCOMP
resistor, all other CSN pins connected normally Ground: CSP1, CSP2NB, IOUT, DROOP, FB, CSSUM AND VDD

Precision Oscillator
A programmable precision oscillator is provided. The powers up with a default frequency of 400 kHz. The
clock oscillator serves as the master clock to the ramp switching frequency range is between 240 KHz/phase to
generator circuit. This oscillator is programmed over the 1.0 MHz/phase.
SMBus interface through register 0xF7. The NCP4205

1400

1200

1000
Frequency (kHz)

800

600

400

200

0
0 5 10 15 20 25 30 35
Register 0xF7 (Decimal)

Figure 16. PWM vs. Register Code

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 NCP4205

Programming the Ramp Feed−Forward Circuit

The ramp generator circuit provides the ramp used by the a 4 V UVLO function. The VRMP UVLO is only active
PWM comparators. The ramp generator provides voltage after the controller is enabled. The VRMP pin is a high
feed−forward control by varying the ramp magnitude with impedance input when the controller is disabled.
respect to the VRMP pin voltage. The VRMP pin also has

Vin

Vramp _pp
Comp−IL

Duty

Figure 17. Ramp Feed Forward

During steady state operation, the duty cycle is centered Protection Features
on the valley of the triangle ramp waveform and both edges Output voltage out of regulation is defined as either a UVP
of the PWM signal are modulated. During a transient event or OVP event. The protection mechanism in case of either
the duty will increase rapidly and proportionally turning on type of fault is described in this section.
all phases as the error amp signal increases with respect to
Input Under Voltage Protection
the ramps to provide a highly linear and proportional
response to the step load. NCP4205 monitors the 5 V VCC supply and the VRMP
pin for under voltage protection.

Gate Driver UVLO Restart

VCC
If DRON is pulled low the
DAC controller will hold off its
startup

Gate Driver Pulls DRON

Low during driver UVLO
UVLO and Calibration

DRON

Figure 18. Under Voltage Lock−OUT

Soft Start
Soft start is implemented internally. A digital counter COMP pin released to begin soft−start. The DAC will ramp
steps the DAC up from zero to the target voltage based on the from zero to the target DAC codes and the PWM outputs will
predetermined slew rate programmed on startup. The begin to fire. Each phase will move out of the MID state
controller enables and sets the PWM signal to the 2.0 V MID when the first PWM pulse is produced preventing the
state to indicate that the drivers should be in diode mode. The discharge of a pre−charged output.

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 NCP4205

DRON

Figure 19. Soft−Start Sequence

Over Current Latch−Off Protection Under Voltage Monitor

The NCP4205 support IDDSPIKE, an amount of current Both output, VDD and VDDNB, must be protected from
drawn by the processor that exceeds the sustained design an under−voltage fault, which is indicative or a short circuit
current limit, TDC, for a thermally significant period of time fault. The UVP threshold is shown in the table below. The
<10 ms. The NCP4205 incorporates a dual threshold current output voltage is monitored at the output of the differential
based protection mechanism for both the VDD and the amplifier for UVLO. If the output falls more than 300 mV
VDDNB output to protect the NCP4205 if the output current below the DAC−DROOP voltage the UVLO comparator
exceeds TDC. will trip sending the VDD_PWRGD/VDDNB_PWRGD
The NCP4205 provides two different types of current signal low. If a UVP event occurs, the NCP4205 need to be
limit protection. During normal operation a programmable re−enabled by cycling the enable pin.
total current limit is provided that scales with the phase
count during power saving operation. A second fixed Over Voltage Protection
per−phase current limit is provided for VID lower than During normal operation the output voltage is monitored
0.25 V, such as during soft−start. at the differential inputs VDD/VDDNB and VSS. If the
The level of total current limit is set with the resistor from output voltage exceeds the DAC voltage by approximately
the ILIM pin to CSCOMP pin. Internally the current through 325 mV, PWM/PWMNB1−2 will be forced low when OVP
ILIM pin is scaled and then compared to two current is triggered. And then the DAC will ramp down to zero to
thresholds 10 mA and 15 mA, where 10 mA threshold is scaled avoid a negative output voltage spike during shutdown.
to indicate the 100% current limit and 15 mA indicates the When the DAC gets to zero, PWM/PWMNB1−2 will be
150% current limit. If 100% current limit is exceeded, an forced low with DRON remaining high. To reset the part the
internal latch−off counter starts. The controller shuts down EN pin must be cycled low.
if the over current fault is not removed after 50 ms. If 150%
current limit is exceeded, the controller shuts down
immediately. To recover from an OCP fault the EN pin must
be cycled low. The current limit is scaled when phase
shedding is in operation. Phase shedding from 2−phase to
single phase scales the current limit to its half.
During start−up the per−phase current limit is active to
protect the individual output stages. This limit monitors the
voltage drop across the DCR through the CSPx and CSREF
pins. The minimum threshold is 36 mV.

Figure 20. OVP Threshold Behaviour

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 NCP4205

VID Down to Zero and ILIM monitoring. Give the first priority in component
When the VID is changed from a non−zero value to zero placement and trace routing to per phase and total current
the controller adopts the Soft−Off phenomenon to decay to sensing circuit. The per phase inductor current sense RC
0 V. The VID down slew rate to 0V is 2.5mV/ms and is filters should always be placed as close to the CSREF and
independent of the slew rate setting of the controller. This is CSP pins on the controller as possible. The filter cap from
implemented to avoid undershoot and it guarantees a smooth CSCOMP to CSREF should also be close to the controller.
VID down. The PWRGD pin remains high when a 0 V VID The temperature−compensate resistor RTH should be placed
code is asserted. as close as possible to the Phase 1 inductor. The wiring path
between RCSx and RPHx should be kept as short as possible
Layout Notes
and well away from switch node lines. The Refx resistors
The NCP4205 has differential voltage and current (10 W) connected to CSREF pin should be placed near the
monitoring. This improves signal integrity and reduces inductors to reduce the length of traces. The above layout
noise issues related to layout for easy design use. To insure notes are shown in Figure 21.
proper function there are some general rules to follow:
Careful layout in per phase and total current sensing are
critical for jitter minimization, accurate current balancing

To V OUT
RTH To Switch Nodes Sense
Place as close as possible
to nearest inductor
RPH1 RPH2 R REF 1 R REF 2
RCS 1 RCS 2
CSCOMP

CCS 2 CCS 1 REFx resistors could

CSSUM Keep this path as short as
− possible and well away be placed near the
CSREF from switch node lines inductors to reduce
+ the number of long
traces
RCSN 1
CSP1
−
C CSN 1 To
+
Switch
RCSN 2 Nodes
CSP2
−

+ CCSN 2
Per phase current sense
RC should be placed
close to CSPx pins

Figure 21. Layout Guidelines

Place the VCC decoupling caps as close as possible to the Once the user configures the part to accept commands
controller VCC pin. For any RC filter on the VCC, the from the SMBus the part is setup to write to the main rail by
resistor should be no higher than 2.2 W to prevent large default, to allow communication to the North bridge rail the
voltage drop. The small high feed back cap from COMP to user must set bit 2 to the value of 1 in register D2h. The
FB should be as close to the controller as possible. Keep the register map describes all the register in the context of main
FB traces short to minimize their capacitance to ground. rail only, however once bit 2 in register D2h is set these
register are all communicating with the North Bridge rail i.e.
Digital Interface (SMBUS) Vout command register 21h changes will be execute voltage
Control of the NCP4205 is carried out using the SMBus. changes on the North Bridge rail only until this bit is cleared.
Vout, Loadline and offset can be programmed either over the The NCP4205 is connected to this bus as a slave device,
SVI2 interface or the SMBus interface. By default the under the control of a master controller. Data is sent over the
NCP4205 accepts voltage, loadline and offset commands serial bus in sequences of nine clock pulses: eight bits of data
only from the SVI2 interface, to configure the part to accept followed by an acknowledge bit from the slave device.
commands from the SMBus the user must set bit 0 in register Transitions on the data line must occur during the low period
D2h. The voltage and current register values are updated of the clock signal and remain stable during the high period,
after every 43 ms approximately. Six registers are updated because a low−to−high transition when the clock is high
in a round robin manner with one conversion takes 8 ms. might be interpreted as a stop signal. The number of data
Therefore, data can be read over SMBus after every 44 ms bytes that can be transmitted over the serial bus in a single
based on the round robin time of the ADC of NCP4205.

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 NCP4205

read or write operation is limited only by what the master The first byte of a read or write operation always contains
and slave devices can handle. an address that is stored in the address pointer register. If data
·When all data bytes have been read or written, stop is to be written to the device, the write operation contains a
conditions are established. In write mode, the master pulls second data byte that is written to the register selected by the
the data line high during the tenth clock pulse to assert a stop address pointer register. This write byte operation is shown
condition. In read mode, the master device overrides the in . The device address is sent over the bus, and then R/W is
acknowledge bit by pulling the data line high during the low set to 0. This is followed by two data bytes. The first data
period before the ninth clock pulse; this is known as No byte is the address of the internal data register to be written
Acknowledge. The master takes the data line low during the to, which is stored in the address pointer register. The second
low period before the tenth clock pulse, and then high during data byte is the data to be written to the internal data register.
the tenth clock pulse to assert a stop condition. The read byte operation is shown in Figure 24. First the
Any number of bytes of data can be transferred over the command code needs to be written to the NCP4205 so that
serial bus in one operation, but it is not possible to mix read the required data is sent back. This is done by performing a
and write in one operation because the type of operation is write to the NCP4205 as before, but only the data byte
determined at the beginning and cannot subsequently be containing the register address is sent, because no data is
changed without starting a new operation. written to the register. A repeated start is then issued and a
In the NCP4205, write operations contain one, two or read operation is then performed consisting of the serial bus
three bytes, and read operations contain one or two bytes. address; R/W bit set to 1, followed by the data byte read from
The command code or register address determines the the data register.
number of bytes to be read or written, See the register map It is not possible to read or write a data byte from a data
for more information. register without first writing to the address pointer register,
To write data to one of the device data registers or read even if the address pointer register is already at the correct
data from it, the address pointer register must be set so that value. In addition to supporting the send byte, the NCP4205
the correct data register is addressed (i.e. command code), also supports the read byte, write byte, read word and write
and then data can be written to that register or read from it. word protocols.

1 9 1 9
SCL

SDA
1 1 0 0 0 ADDRESS R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY STOP BY
MASTER NCP4205 NCP4205 MASTER
FRAME 1 FRAME 2
SERIAL BUS ADDRESS BYTE COMMAND CODE
Figure 22. Write Command Code Byte

1 9 1 9
SCL

SDA
1 1 0 0 0 ADDRESS R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY
MASTER NCP4205 NCP4205
FRAME 1 FRAME 2
SERIAL BUS ADDRESS BYTE COMMAND CODE

1 9
SCL (CONTINUED)

SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY STOP BY
NCP4205 MASTER
FRAME 3
DATA BYTE
Figure 23. Write a data Byte

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Figure 24. Read a Data Byte

The following abbreviations are used in the diagrams:

S − START
P − STOP
R − READ
W − WRITE
A − ACKNOWLEDGE
A − NO ACKNOWLEDGE
The NCP4205 uses the following write protocols.

Send Byte
In this operation, the master device sends a single command byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the transaction ends.
For the NCP4205, the send byte protocol is used to clear Faults. This operation is shown in Figure 13.

1 2 3 4 5 6

SLAVE COMMAND
S W A A P
ADDRESS CODE

Figure 25. Send Byte

If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start
condition immediately after the final ACK and carry out a single byte read without asserting an intermediate stop condition.

Write Byte
In this operation, the master device sends a command byte and one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA and the transaction ends.
The byte write operation is shown in Figure 14.

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1 2 3 4 5 6 7 8

SLAVE COMMAND
S W A A DATA A P
ADDRESS CODE

Figure 26. Write Byte

Write Word
In this operation, the master device sends a command byte and two data bytes to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends the first data byte.
7. The slave asserts ACK on SDA.
8. The master sends the second data byte.
9. The slave asserts ACK on SDA.
10. The master asserts a stop condition on SDA and the transaction ends.

1 2 3 4 5 6 7 8 9 10
SLAVE COMMAND DATA DATA
S W A A A A P
ADDRESS CODE (LSB) (MSB)

Figure 27. Write Word

Block Write
In this operation, the master device sends a command byte and a byte count followed by the stated number of data bytes to
the slave device as follows:
1. The master device asserts a START condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code
5. The slave asserts ACK on SDA
6. The master sends the byte count N
7. The slave asserts ACK on SDA
8. The master sends the first data byte
9. The slave asserts ACK on SDA
10. The master sends the second data byte.
11. The slave asserts ACK on SDA
12. The master sends the remainder of the data byes
13. The slave asserts an ACK on SDA after each data byte.
14. After the last data byte the master asserts a STOP condition on SDA

1 2 3 4 5 6 7 8 9
SLAVE COMMAND BYTE COUNT DATA
S W A A A A
ADDRESS CODE =N BYTE 1

10 11 ... 12 13 14
DATA
BYTE 2
A ... DATA
BYTE N
A P

Figure 28. Block Write

Read Byte
In this operation, the master device receives a single byte from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA.

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4. The master sends a command code.

5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on SDA
7. The master sends the 7 bit slave address followed by the read bit (high)
8. The slave asserts ACK on SDA
9. The slave sends the Data Byte
10. The master asserts NO ACK on SDA.
11. The master asserts a stop condition on SDA and the transaction ends.

1 2 3 4 5 6 7 8 9 10 11
SLAVE COMMAND SLAVE
S W A A S R A DATA A P
ADDRESS CODE ADDRESS

Figure 29. Read Byte

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Read Word
In this operation, the master device receives two data bytes from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on SDA
7. The master sends the 7 bit slave address followed by the read bit (high)
8. The slave asserts ACK on SDA
9. The slave sends the first Data Byte (low Data Byte)
10. The master asserts ACK on SDA.
11. The slave sends the second Data Byte (high Data Byte)
12. The masters asserts a No ACK on SDA
13. The master asserts a stop condition on SDA and the transaction ends

1 2 3 4 5 6 7 8 9 10
SLAVE COMMAND SLAVE DATA
S W A A S R A A
ADDRESS CODE ADDRESS (LSB)

11 12 13
DATA
A P
(MSB)

Figure 30. Read Word

Block Read
In this operation, the master device sends a command byte; the slave sends a byte count followed by the stated number of
data bytes to the master device as follows:
1. The master device asserts a START condition on SDA.
2. The master sends the 7−bit slave address followed by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a REPEATED START condition on SDA
5. The master sends the 7−bit slave address followed by the read bit (high).
6. The slave asserts ACK on SDA
7. The slave sends the byte count N
8. The master asserts ACK on SDA
9. The slave sends the first data byte
10. The master asserts ACK on SDA
11. The slave sends the remainder of the data byes, the master asserts an ACK on SDA after each data byte.
12. After the last data byte the master asserts a No ACK on SDA.
13. The master asserts a STOP condition on SDA

1 2 3 4 5 6 7
SLAVE SLAVE BYTE COUNT
S W A S R A
ADDRESS ADDRESS =N

8 9 10 11 12 13
DATA DATA
A
BYTE 1
A ... BYTE N
A P

Figure 31. Block Read

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 NCP4205

The NCP4205 includes a timeout feature. If there is To prevent rogue programs or viruses from accessing
no Bus activity for 35 ms, the NCP4205 assumes that the critical NCP4205 register settings, the lock bit can be set.
bus is locked and releases the bus. This prevents the device Setting Bit 0 of the Lock/Reset sets the lock bit and locks
from locking or holding the SMBus expecting data. Some critical registers. In this mode, certain registers can no
SMBus controllers cannot handle the SMBus timeout longer be written to until the NCP4205 is powered down and
feature, so it can be disabled. powered up again. For more information on which registers
are locked see the register map.

Table 20. REGISTER MAP

CMD Code R/W Default Description #Bytes Comment

0x01 R/W 0x80 Operation 1 00xx xxxx – Immediate Off

01xx xxxx – Soft Off
1000 xxxx – On (slew rate set by soft start) – Default
1001 10xx – Margin Low (Act on Fault)
1010 10xx – Margin High (Act on Fault)

0x02 R/W 0x17 ON_OFF_Config 1 Configures how the controller is turned on and off

Bit Default Comment

7:6 00 Reserved for Future Use

5 1 Reserved

4 1 This bit is read only. Switching starts when

commanded by the Control Pin and the
Operation Command, as set in Bits 3:0

3 0 0 : Unit ignores OPERATION commands over

the Interface
1: Unit responds to OPERATION command,
power up may also depend upon Control
input, as described in Bit 2

2 1 0: Unit ignores Main Rail EN pin

1: Unit responds Main Rail EN pin, power up
may also depend upon the Operation
Register, as described for Bit 3

1 1 Control Pin polarity

0 = Active Low
1 = Active High

0 1 This bit is read only. 1 means that when the

controller is disabled it will either immediately
turn off or soft off (as set in the Operation
Command)

0x03 W NA Clear_Faults 0 Writing any value to this command code will clear all Status Bits immediately.

0x10 R/W 0x00 Write_Protect 1 The Write_protect command is used to control writing to the device. There is also a lock bit
in the Manufacturer Specification Registers that once set will disable writes to all
commands until the power to the NCP4205 is cycled.

0x19 R 0xB0 Capability 1 This command allows the host to get some information on the SMBus device

Bit Default Comment

7 1 PEC (Packet Error Checking is supported)

6:5 01 Max supported bus speed is 400 kHz

4 0 Reverved

3:0 000 Reserved for future use

0x20 R 0x22 Vout_Mode 1 The NCP4205 supports SVI2 VID mode for programming the output voltage

0x21 R/W 0x00 VOUT_Command 2 Sets the output voltage using the SVI2 VID table decoding

0x24 R/W 0x00 reserved

0x25 R/W 0x00E9 VOUT_ MARGIN_ HIGH 2 Sets the output voltage when operation command is set to Margin High. Programmed in
VID Mode.

0x26 R/W 0x0033 VOUT_ MARGIN_ LOW 2 Sets the output voltage when operation command is set to Margin Low. Programmed in
VID Mode.

0x38 R/W 0x0001 IOUT_CAL_ GAIN 2 Sets the ratio of voltage sensed to current output. Scale is Linear and is expressed in
1/Ohms

0x39 R/W 0x0000 Iout Offset

0x4A R/W Iout _Fault limit This sets the output current fault limit. Once exceeded Bit 7 of the Status IOUT Command
gets set and the FAULT output gets asserted (if not masked)

0x55 R/W 0x0010 VIN_OV_ FAULT LIMIT 2 This sets the input over voltage fault limit. Once exceeded the VIN Overvoltage Fault Bit,
Bit 7, gets set in the Status Input Register and the FAULT output is asserted. This limit is
set using Linear Mode, in V.

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Table 20. REGISTER MAP

CMD Code R/W Default Description #Bytes Comment

0x68 R/W 0x012C POUT_OP_ FAULT LIMIT 2 This sets the output power over power fault limit. Once exceeded Bit 1 of the Status IOUT
Command gets set and the FAULT output gets asserted (if not masked)

0x78 R 0x00 STATUS BYTE 1 Bit Name Description

7 BUSY A fault was declared because the NCP4205

was busy and unable to respond

6 OFF This bit is set whenever the NCP4205 is not

switching

5 VOUT_OV This bit gets set whenever the NCP4205

goes into OVP mode.

4 IOUT_OC This bit gets set whenever the NCP4205

latches off due to an over current event.

3 Reserved Reserved

2 Reserved Reserved

1 Reserved Reserved

0 None of the Above A fault has occurred which is not one of the
above

0x79 R 0x0000 STATUS WORD 2 Byte Bit Name Description

Low 7 Res Reserved for future use

Low 6 OFF This bit is set whenever the NCP4205 is not

switching

Low 5 VOUT_OV This bit gets set whenever the NCP4205

goes into OVP mode

Low 4 IOUT_OC This bit gets set whenever the NCP4205

latches off due to an over current event

Low 3 Reserved Reserved

Low 2 Reserved Reserved

Low 1 Reserved Reserved

Low 0 None of the Above A fault has occurred which is not one of the
above

Byte Bit Name Description

High 7 VOUT This bit gets set whenever the measured

output voltage goes outside its power good
limits or an OVP event has taken place, i.e.
any bit in Status VOUT is set

High 6 Iout/Pout This bit gets set whenever the measured

output current or power exceeds its warning
limit or goes into OCP. i.e. any bit in Status
IOUT is set

High 5 Input This bit gets set whenever the measured

input voltage falls outside its Fault limit

High 4 MFR A manufacturer specific warning or fault has

occurred

High 3 VDD_PWRGD The VDD_PWRGD signal is deasserted.

Same as PowerGood in General Status

High 2 Reserved Reserved

High 1 OTHER A Status bit in Status Other is asserted

High 0 Res Reserved for future use

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Table 20. REGISTER MAP

CMD Code R/W Default Description #Bytes Comment

0x7A R 0x00 STATUS VOUT 1 Bit Name Description

7 VOUT_OVERVOL This bit gets set whenever an OVP Event

TAGE FAULT takes place

6 VOUT_OVERVOL Not Supported

TAGE WARNING

5 VOUT_ UNDER Not supported

VOLTAGE
WARNING

4 Reserved Reserved

3 VOUT_MAX Not supported, Can’t program an output

Warning greater than max VID as there are no bits to
program it

2 Reserved Reserved

1 Reserved Reserved

0 Reserved Reserved

0x7B R 0x00 STATUS IOUT 1 Bit Name Description

7 IOUT Overcurrent This bit gets set if the NCP4205 latches off
Fault due to an OCP Event

6 Reserved Reserved for future use

5 IOUT Overcurrent Not supported

Warning

4 Reserved Reserved for future use

3 Reserved Reserved for future use

2 Reserved Reserved for future use

1 POUT Over Power This bit gets set if the measured POUT
Fault exceeds the FAULT Limit

0 Reserved Reserved

0x7C R 0x00 STATUS INPUT 1 Bit Name Description

7 VIN Overvoltage This bit gets set when the input voltage goes
FAULT above its programmed FAULT limit

6 Reserved Reserved for future use.

5 Reserved Reserved for future use.

4 Reserved Reserved for future use.

3 Reserved Reserved for future use.

2 Reserved Reserved for future use.

1 Reserved Reserved for future use.

0 Reserved Reserved for future use.

0x88 R 0x00 Read_VIN 2 Readback of input voltage, measured using VRMP Input. Readback is in linear mode

0x8B R 0x00 Read_VOUT 2 Readback output voltage. Voltage is read back in VID Mode

0x8C R 0x00 Read_IOUT 2 Readback output current. Current is read back in Linear Mode (Amps)

0x96 R 0x00 Read_POUT 2 Readback Output Power, read back in Linear Mode in W’s.

0x99 R 0x1A MFR_ID 2 0x1A

0x9A R 0x4205 MFR_ MODEL 2 0x4205

0x9B R 0x04 MFR_ REVISION 1 0x04

0xD0 R/W 0x00 Lock/Reset 1 Bit 0 = Lock Bit

Bit 1 = Reset Bit

0xD1 R/W 0x01 Manufacturer Config 1 Bit 0 = ADC

Bit 1 = Reserved
Bit 2 = Reserved
Bit 3 = SMB_TO_EN

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Table 20. REGISTER MAP

CMD Code R/W Default Description #Bytes Comment

0xD2 R/W 0x00 VR Config 1 1 Bit 0= 0, All SVI2 parameters programmed through SVI2; Default = 0
1, All SVI2 parameters programmed through Digital interface
Bit 1 = Reserved
Bit 2 = Voltage rail;
Voltage rail = 0 then main rail is programmable,
Voltage rail = 1 then North Bridge rail is programmable over SMBus.
Default = 0
Bit 3 = Reserved
Bit 4 = Reserved
Bit 5 = Reserved
Bit 6 = CLIM_EN, 0 = CLIM Latch off enabled = default, 1 = CLIM
Latch off disabled
Bit 7 = Reserved

0xD3 R/W 0x03 VR Config 2 1 Bit 0 = PSI0

Bit 1 = PSI1 (see description of operation on page 17)
Bit 2 = Not supported
Bit 3 = Reserved
Bit 4 = Reserved
Bit 5 = Not supported
Bit 6 = Reserved

0xD4 R VOUT_Linear 2 Readback of output voltage in Linear Mode. Exponent fixed at −9

0xD5 R/W 0x02 Vout Trim 1 Programmable Offset Voltage.

Data format is 2’s complement
00 = 0
01−25 mV
10 = initial programmed offset (default)
11 = +25 mV
11

0xD6 R/W 0x00 Initial offset

0xE3 R/W 0x02 Current Limit 1 Sets the value of the current limit relative to the current limit set by the ILIM pin.

0xE4 R/W 0x03 Loadline 1 This register sets the internal loadline attenuation. The max loadline is controlled externally
by setting the gain of the CSA. The max loadline can be adjusted between 0% and 100%
of the external loadline.
000-Remove all loadline drop from output
001-LL slope-40%
010-LL slope-20%
011-LL slope (38.7% default)
100- LL slope+20%
101- LL slope+40%
110 LL slope+60%
111 LL slope+80%

0xE5 R/W 0x03 Initial loadline

0xE6 R/W 0x00 Special purpose offset

0xE7 R 0x00 Current VID 2 This register reports back the current VID Code being output incl. Offset being output

0xF3 R 0x00 Vboot 1 Read back Vboot value− VID code format

0xF7 R/W 0x0A OSC Freq. 1 This register adjusts the oscillator frequency from 240 kHz to 1 MHz

0xFB R/W 0x00 General Status Bit 0 – Ready

Bit 1 – VDD_PWRGD
Bit 2 − VDDNB_PWRGD
Bit 3 – RESERVED
Bit 4 – RESERVED
Bit 5 − Clim limit exceeded but not long enough for Latch off

0xFC R 0x00 Reserved Reserved

0xFD R 0x00 Phase Status Bit 0 = Phase 1

Bit 1 = Phase 2

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 NCP4205

PACKAGE DIMENSIONS

QFN44 6x6, 0.4P

CASE 485CH
ISSUE A

SOLDERING FOOTPRINT*
5.60

(Unit: mm)
5.60

0.40 0.21
0.80

NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 NCP4205

ORDERING INFORMATION
Device Package Shipping†
NCP4205MNTXG QFN44 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

AMD is a registered trademark of Advanced Micro Devices, Inc.

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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