Table of Contents Chapter 1: Binary Number Systems. 1 Chapter 2: Basic Gates and Boolean Algebra . : K-Maps Chapter 4: Combinational logic wmmennnnennnnnennnnennnnnennnnennnnnennnnnens 18 13 Chapter Chapter $: Introduction 10 flip-flOPS.r.esiwusnrnssninnnnennnnennaneaneinnnanensnnnen 34 Chapter 6: Finite State Machines — Synchronous Sequential design 4B Chapter 7: Setup time and Hold time. Chapter 8: Counters and Shift Registers. Chapter 9: Fauit Analysis and Hazard Chapter 10: Digital Integrated Circuits Chapter 11: Memories, FIFO and Programmable device .wennnennnennnenennne 107 Chapter 12: Verilog HDL wnnsnnnnnnnnnennnnnnnennnnennnnnennnnnnnnnnennnens 116Chapter 1 a jumber Systems Questions: QI) Define: (a) bit (b) nibble (c) byte (d) word 2) What is weighted code? Give example. Q3) Give an example for Non-weighted code? (Q4) What is the key feature of Excess-3 code? Q5) In how many different ways can number 5 be represented using 2-4-2-1 code? Q6) What are all the BCD numbers that can be uniquely represented in 2 code? 2-1 weighted Q7) How many unused combinations are there in the representation of BCD numbers using 7-4-2-1 weighted scheme? What are they? aye is the condition for a weighted code to be selfcomplementary? Q9) Convert the binary number 011101010001 to octal and hexadecimal? Ql0) Formulate a simple procedure for converting base-8 numbers to base-9? QU1) Convert (2111012: 10 base-97 Q12) digits in a r-radix number system. What is its (t-1)’s complement and r’s complement? Q13) What is the 9°s complement of the BCD number 752? Q14) Convert the Gray code number 11001 to binary code? QIS) Give the procedure for converting a binary number to Gray code? Q16) Represent 45 in the number systems (a) binary (b) BCD (c) Excess-3 (d) Gray code QI7) Give the range of the numbers that can be represented using n bits in 2's complement method? QI8) What is the minimum number of bits required to represent the numbers in the range of -5 to 23 using 2's complement method? Srikanth Alaparthi 14o odd Joes (1), vole Q- X srumaladt vogordons 4 —_— 20) In a particular design which uses 5 bits for integral part and 7 bits for fractional part, the result of some operation is 7B8 hex. Find the corresponding decimal equivalent? Q21) Convert 0.95 to its binary equivalent? 22) ABie— 3Ei6= ? Q23) Solve for x: (70)s+ (12 ame Q24) Solve for X in (135):2= (X)s + (78)? 25) Explain the detailed procedure for BCD addition? Q26) Perform BCD addition: (1001) + (0110)? Answers: Al) (a) Bit: Binary digit (Either logic-1 or logic-0) (b) Nibble: 4-bits together is called a nibble (c) Byte: 8 bits or 2 nibbles (d) Word: 16 bits or 2 bytes A2) The weighted code will have a fixed weight for each position. For example, in normal binary system, the decimal equivalent can be obtained by multiplying the position value with position weight and adding them together. A3) Unlike weighted code, non-weighted codes will not any weights. For example, Excess-3 code and Gray code. So the numbers that are represented using non-weighted code can not be directly converted to decimal equivalents. Ad) Self-complementing: The 9°s complement of an excess 3 number can be obtained simply by replacing its 1's with 0’s and 0°s with Is. AS) 2-4-2-1 represents the weights corresponding to bit positions. So the two possible ways are: 1011, 0101 A6) 0, 1, 8 and 9 (Only these 4 numbers will have unique representations). A7) As BCD numbers range from 0 to 9, there are 5 unused combinations in 7- They are: 1011, 1100, 1101, 1110 and 1111. Srikanth AlaparthiAS) A weighted code is self-complimentary if the sum of the weights equals to 9 E.g.: 2-4-2-1 code. Sum of the weights = 2+4+2+1=9. A9) (a) Binary: 011 101 010 001 Octal: 3 5 2 1 (b) Binary: 0111 0101 0001 Hex: 7 5 1 (Similar concept was explained in Al4 & A15) A10) Consider (Xy1 Xp2 .X3X2X) Xo) an bit base 3 number. The corresponding decimal equivalent is given by, rt Ng + Naa nn + 3X54 FRY IN t No =o Bx Xt +95 (3 X3+X3)+9°(3 Xp + Xa) So take every to digits of base-3 number from LSB side, find their decimal equivalent, it will be the corresponding base-9 digit. (Similar to the procedure of converting a binary number to octal or hex) Al) Base-3: (2 11 10 12 222. Base-9:2 43587 48 Al2)(P-1)-N, (-N) 13) 999 — 752 = 247 A14) Conversion from gray to binary: Retain the MSB as it as. XOR the current input bit with the previous output bit to get the new output bit. In this case, given gray code number is 11001 INPUT (Gray) 4 1 0 0 OUTPUT(Binary) 1 0 0 So, the required binary number is 10001. AIS) Binary to Gray code conversion: Retain MSB. XOR Current bit of Binary input With the previous bit of Binary input to get new bit of Gray code Output. A16) (a) 101101 (b) To get BCD: Represent each digit separately in binary 0100 0101 (©) Excess-3: Add 3 to each digit and then represent them separately in binary 0111 1000 (d) Gray code: First convert to Binary and use the procedure shown in QUS: 1101 AIT) (2°71) 0 +2" 1) Srikanth Alaparthi 3=> 2% ta 24 281 Als) (2"""—1)> n= 6bits A19) 2’s compliment of the binary number E.g: Consider 10010, Its 2’s compliment is given by 01110 A20) 78B in hes /1111.011 1000 (5 integral bits and 7 fractional bits) 15.4375 A21)0.95x2 0.90 x2 0.80 x2 0.60 x2 0.20 x2 0.40 x 2 0.80x 2 So, 0.95 0, 11 1100 1100 1100 1100.... A22) ABys~ 3Ey6= (171) ~ (62) = (109) = 6Dis A23) 2x? +x+1= 56+ 50= 106 => x (2x+1)= 105 =7x 13> x=7 A24) (78)9 = 63+ 8=(71)10 (135)12 = 144 + 36 + 5 = (181)i0 (71)to= (181)10= (110)10= (156)e So, X= 156 A25) BCD addition is similar to any binary addition. But if the result is above 9, to get valid BCD result, we need to add 6 to the result. A2%6) «1001 0110 1111@9) Adding 6,01 10 10101 So, the result is 0001 0101 = (1 5) Srikanth Alaparthi 4Chapter 2: Basic Gates and Boolean Algebra Questions: QI) Which gates are called universal gates? Why? 2) How many minterms or maxterms will be there for n-inputs? Q3) Give the minterm and maxterms corresponding to 6 and 15 numbers (4-inputs)? (aa) In how many ways can a NAND gate be converted into an inverter? Show all the possibilities? QS) How many number of 2 input AND gates are required to generate N I/P AND gate? @osiate De-Morgan’s Laws? (a) If it is given that A & B will not be | at the same time, what will be the equivalent logical gate for an XOR gate? (b) Ifany of the inputs of an XOR gate are inverted, XOR gate will work as —-? ‘State the Shannon’s expansion theorem for representing a Boolean function by its To-factors? @)wire the cofactors Fa and Fa: for F(A,B,C,D) = ABD + BCD’ + A’B’C’ ? Q10) How many unique Boolean functions can exist for ‘n’ number of inputs? Q11) Mention the logical gates for which the 3 input implementation can not be obtained fiom two 2 input gates? How do you implement them? Q12) What is OUT in the circuit shown below? x . —~ _—“ OUT Q13) Give implementation of XOR using minimum number of NAND gates? Srikanth AlaparthiAn assembly line has 3 fail safe sensors and one emergency shutdown switeh. The line should keep moving unless any of the following conditions arise: (i) If the emergency switch is pressed (ii) If the senor! and sensor2 are activated at the same time. (iii) If sensor 2 and sensor3 are activated at the same time. (iv) If all the sensors are activated at the same time Suppose a combinational circuit for above case is to be implemented only with AND Gates, How many minimum number of 2 input NAND gates are required? GQ@WDasory function is the one which gives 1 if the input has more 1s than 0s. Show The truth table and give the AOI for 3-input majority function? Gagx number of XNOR gates are connected as shown below. How does this cireuit [Nwork? Explain? Q17) Show the implementation of XNOR gate using minimum number of NOR Gates? QI8) Explain parity generation and its significance? Q19) Which logical gates can be used as parity generators? Q20) What is the parity of (i) 10111001 (ii) 11001010 Q21) Give a circuit for 4-bit even parity checker? And explain the same how can it be re- used for parity generation? Q22) Design a combinational circuit using XOR gates that converts a 4-bit gray code number to a 4-bit binary number? 03) Draw the enable signal (CLK_EN) such that the OUT will get only the 2 and 3 pulses of CLK? The figure shows the circuit and CLK signal? Srikanth Alaparthi 6CLK ;*% CLK_EN 24) Which logical gate can be used to find out whether the two single bit inputs are equal or not? (05) What is the difference between NAND gate and negative AND gate? 26) How to obtain the dual of a Boolean equation? Q27) Match the following: a) Comparator (i) NAND b) Halfadder (ii) NOR ¢) Anyone input is 1, outputisO (iii) XOR 4) Anyone input is 0, output is1 (iv) XNOR Answers: Al) NAND and NOR gates are called universal gates. Because any other logical gate like AND, OR, NOT, XOR, XNOR ete. of any other Boolean function can be implemented oly with NAND or NOR gates. A2) For n inputs, possible minterms/maxterms = 2°n, For example, for 2 inputs the possible 4 minterms are A°B’, A’B, AB’, AB and maxterms are A+B, A’+B, A+B’, AGB" A3) (a) 6 (by 15 (0110)> Minterm = A’BCD”, maxterm = A+B’+C’+D (1111): Minterm = ABCD, maxterm = A’+B’+C’+D’ A4) A NAND gate can be converted into an inverter by using any of the following two methods: AS) Nel. For example to implement a 4 input AND gate we need three 2-input AND gates. Srikanth Alaparthi 1A6) (A*B+C+D...)° (ABCD... A7) (a) OR Gate, We can conclude this from truth table. Also from Boolean algebra as shown here As A=B=I, can not occur, AB = 0 always. A XOR B = AB’ + A’B= A (AB)’ + B(AB)’ = A (0)’ + B(0)" = A+B (b) XNOR Gate. AXORB =AB’+A’B Using this, A’ XOR B = AXOR B’ = A’B’ + AB= A XNORB A8) According to Shannon's expansion theorem any Boolean function F(A,B.C,D... can be represented as F= A Fa + A’ Fa: , where the cofactors Fs and Fy: are given as, Fq=F(LB,CD....) and Fa: = F(0.B.CD....) A9)Fa= BD + BCD’ and Fy = BCD’ +B’C” Al0)2°2*n For n inputs, the possible number of minterms are, k = 2n. Any boolean function is combination of minterms. So all possible Boolean functions are *Cy +*Cy + "Cy +4Cy +e... C= (141) All) NAND , NOR and XNOR : All these 3 gates need three 2-input gates to get 3-input gates. The 3-input NAND implementation using 2-input NAND gates is shown below. NOR and XNOR also can be implemented in the same way. (ABy' 7 Bay __ cc ———_ recy’ A12) First XOR gate output = X XOR X’ Second XOR output = 1 XOR Third XOR gate output = OUT = X’ XOR X= OUT = 1 irrespective of X Al3) AXOR B= A’B+ AB’ = A(AB)’ + B(ABY Srikanth Alaparthi 8A \. ao L—, L_t—4, (AB)" b— rl A . ~“AXORB I B / Al4)6 A = Switch B=Sensorl C=Sensor2 D=Sensor3 Pressed or sensor activate: hutdown=1 Tf you use K-Map and simplify, you will get F = A + BC + CD. The implementation of the same is shown below — = yy [= | PT) -}'! . ‘You can always use the truth table and then use Boolean simplification to get the result. AIS) Truth table for 3-input majority function is shown below: A_ |B [ce [¥ ojo [o fo ojo [i fo o fi [o fo oa fh 1 jo Jo [o 1 fo ff ft 1] fo fa 1 a Y=AB+BC+AC The AND-OR Implementation (AOD) of Y is shown below: Srikanth Alaparthi 9A16) This is circuit will work in two different ways based on N-value. (a) N is odd (b) N is even (a) If N is odd, there will be even number of XNOR gates in the circuit. Take an example of N=3, So there are 2 XNOR Gates. The two bubbles will get cancelled and this works as XOR. Same works for any odd N. So if N is odd it works as XOR Gate. (b) IFN is even, the circuit works as XNOR Gate. ( Apply the same logic). One extra bubble will be there to make XOR to XNOR. You may verify the same for N: A17) Very much similar to A13. ik ) pe = AXNOR B AI8)_ Parity generation adds an extra bit to the data which indicates the parity of input data. Parity generation is of two types: Even-parity and odd-parity generation. Even parity generator gives | if the input has odd number of 1’s so that overall number of 1°s will be even. Similarly odd parity generator gives | if the input has even number of 1°s. In data transmission systems the transmission channel itself is a source of data error. Hence the need to determine the validity of transmitted and received data. The validity of data is essential in applications where data is transmitted over long distances. Invalid data is a corruption risk. Parity generation helps in checking the validity of the data. Parity generation and validation is a scheme to provide single bit error detection capabilities. A19) XOR gate can be used as even parity generator and XNOR can be used as odd parity generator. A20) (i) ODD as the number of ones = 5, odd number (ii) EVEN, number of 1s, seven Srikanth Alaparthi 10A21) The following circuit shows a parity checker for 4 inputs. A. B and C is the actual data, Whereas P is even parity bit generated at the transmitter. P = A xor B xor C. So A, B, C and P together will have even patity always. If all the bit sequences are received properly, O should be zero always. O=1 indicates that some error has occurred during transmission. The same circuit can be used for parity generation by putting P = 0. If P=! circuit works as 3-input even parity generator. A22) The detailed procedure with an example for converting gray code to binary is shown in chapter 1. The same concept is shown with the XOR gates here A23) The input clock, the OUT that is needed and the corresponding CLK_EN are shown in the following diagra CLK | 1 2 3 4 5 ouT CLK_EN A24) XNOR gate. If we observe the truth tables, XNOR gate gives 1 if both the inputs are same. Similarly XOR gives 1 if both the signals are different. Srikanth Alaparthi rt25) (a) NAND gate A ot F1=(AB)'=A'+B? (b) Negative AND gate: AL ~~ a F2 = A’.B' =(A +B)’ (Equivalent of NOR Gate) + F2 A26) Dual; Replacing AND (NAND) with OR(NOR) and OR (NOR) with AND(NAND) in a given boolean equation gives the dual. A27) a) iv b) iii ¢) ii di Srikanth Alaparthi 12hapter 3: K-Maps Questions: QI) Define: SOP from and POS form? 2) When is a SOP/POS form is called standard or canonical? «Witte POS from fora S-input NOR wate” sit canonical? Q4) Which form is suitable for designing logic circuits using (a) Only NAND gates (b) Only NOR gates Q5) In which order are the bits arranged while drawing K-Maps? )Why do we write 00 01 11 10 in that order while Drawing K-maps? jow many cells will a n-input variable have in K-Map? Q9) What do you mean by don’t care condition? Q10) ¥ =A'C + ACB and you are given that A=C=I will never occur. Simplify Y? QU) ¥ = £(0,2,3,4,9,10,12,13) (6.8.14) Simplify using KMap. Mention Prime Implicants & Essential Prime Implicants? Q12) Y=F(A.B.CD) = ¥ (0.1,4,5,7,9,12). Express the same using IT ? QI3) IfFA,B,C,D,E) = B’E, how many terms will be there in the standard or canonical SOP representation of F? Q14) Ina 6 variable K-map, how many literals will the grouping of 4 adjacent cells give in the term? Q15) Generalization of Q13: The grouping of k adjacent cells, in a N variable K-Map will lead to a term of -—- literals? Q16) Ifthe number of variables are more(>5) , which method is suitable for Boolean simplification? aya the simplification of a Boolean function, F = ¥ (0,1,2,6.7,8,9.10,14,15) using Q- fthod the following table is obtained: Srikanth Alaparthi 1Bofif[2[e[7][s]9]| 10 [mis BC x [x x [x oo x [x x [x Be [xX| xX x |x BD |X x x x (a) Identify the essential prime Implicants? (b) Find out the simplified expression for F in SOP form? QI8) Use K-Map to simplify F = ¥ (0,1,2,6,7,8,9,10,14,15) in SOP ftom? Cross check the essential prime Implicants that are obtained in QU7. Q19) Simplify the Boolean function Y = ¥ ( 0,2,3,5,7,10,11,15) in POS form using K- Map? ere the AND-OR implementation of a circuit, using minimum gates, that gives "H when the input is BCD equivalent of 5,7 or 9 and LOW otherwise. Answers: Al) SOP: Sum Of Products : OR of all ANDs Eg: F (A,B,C) = A + BC POS: Product Of sums: AND of all ORs Eg: F(A.B.C) = (A’+B") (A’+C’) A2) A SOP is called standard if each term is a minterm. Similarly a POS is called standard if each term is a maxterm. A3) Y = AXNORB XNORC A -|-lolol_|-Jololes —-|o}-|o|—-le/-lela lo |-lo|-lolol4 |e Y= (ABC + A’BC’ + AB’C’ + ABC)’ So Y is POS form is (A+B+C*) (A+B"+C) (A’+B+C) (A°+B+C") As each term in the POS form is maxterm, this is canonical. A4) (a) SOP form (b) POS form AS) Hamming order (Gray code) Srikanth Alaparthi 14A6) In K-Map, the Boolean simplification is done by grouping the adjacent cells that have 1. To get the simplified expression, the adjacent cells must have 1 bit change. So gray code is used. A7)2’n. E.g: 3 variables, § cells. Similarly. variables 16 cells, AS) Ceiling (log: n) A9) The don’t care condition set accommodates input patterns that never occur or outputs, that will not be observed A10) ¥ = A'C + AC'B' and the output will be don’t care for A = C = 1. So the K-map will be as follows: SAB Thus the simplified expression for Y is AB? +C All) The K-Map is AB a7) o1 a lw) oo) yb. OL vl |x un CYAN [x 10 i L ion —~ AN The prime implicants are : D’, B’D’, AC’, A’B’C The essential prime implicants are : D’, AC’, A’B'C The simplified expression is : Y =D’ + AC’+ A’B’C A12) Y=T1(2,3,6,8,10,11,13,14,15) A13) 8 terms, F=B’E(A +A’) (C+C’) (D¥D’) Al4) 6 — logy 4 Srikanth Alaparthi 1515) In3 variable map, grouping all 8 cells will give zero literals in the term as itis logical | always. Similarly, in 4 variable map the same grouping will give 1 literals, in a variable map itis 2 and so on. So the literals in the term = N - lopk 16) Q-M Method A17) Checkout for the columns which has only one entry (X), that term must be included in the simplified expression. So, that term will be essential. (a) So the essential prime implicants are: BC and B'C” (b) The simplified expression F = BC + B'C’ + CD’ =BC+B'C’ +B’D" A18) The K-Map is shown below: \eD_ AB\) 00 01) 11, 10 oa) ] ob N —4 o1 The EPI= BC and B’C’ F=BC+B'C +CD’=BC+B'C’+B A19) To simplify the Boolean function in POS form we need to map for 0s and them take the compliment of that function to get ¥ in POS form. cD ABS 00{ 01) 1110 00 Ao o1 nN yo} n {24° Ke 10 y A+C) (BD) (B+C+D") AC’ + BD’ + B'C’Dy Srikanth Alaparthi 16A20) As the input is a BCD number, the output will be don’t care for the input combinations, 10,11,12,13,14 and 15. So the K-Map will be as shown below: cD ABX 00 01 11 10 00 ol ul * x 10 \ A Srikanth Alaparthi 7Chapter 4: Combinational logs Questions: Q1) (a) Show the AOT implementation of a 2:1 Mux? (b) Convert this to 2-input NAND implementation? Q2) Design the following gates using minimum number of 2:1 Muxes? (a) NOT (b)AND (©) OR (4) XOR Q3) Construct a 16:1 Mux with two 8:1 Mux and one 2:1 Mux. Q4) Find out the simplified expression for Y in terms of A, B and C? 4:1 Mux. A B Q5) Design a circuit for 3-input majority function using a 4:1 Mux? Q6) (a) Expand the Boolean function f(x,y,z) =x"2" + xy + xz in terms of x? (b) Implement fusing a 2:1 Mux and extemal gates? Q7) There is a single telephone which needs to transmit the data from 8 different users to the receiving end. Give a design which can accomplish this task? &rou are given a 2:4 decoder, a 2 input OR gate and a 3 input OR gate. Using these ponents design a system which takes A & B as inputs and generates the following four outputs: AB, (AB)', AB, (AB). Q9) Give the truth table for (a) half-adder and (b) half-subtractor? Q10) Design a circuit for half-subtractor using basic gates? QI1) Design "OR" gate using HA's? QI2) Design a full adder using half-adders and minimum number of external gates? Srikanth Alaparthi 18Q13) Implement a full adder using two 4:1 Muxes? Q14) A full adder can be implemented using basic gates in many ways. Show the efficient implementation among them, which needs minimal hardware? QU5) Implement a circuit for adding two 4-bit numbers using (a) Ripple carry adder (b) Carry Look Ahead (CLA) adder Q16) Compare the two implementations of Q1S. QI8) Explain how a full adder can be used as majority function? 19) Tee NB a I DS 220) There is a sixteen bit adder with ripple carry. Which of the following gives minimum delay for the output? (Fastest output) FO = Fi, FF + FF, FF+FI (@)) ‘What is overflow? Under what conditions will it occur? (2) sing a 4-bit binary adder, design a circuit which multiplies the input by 3? @pain a subtractor unit using a 4-bit comparator, 4-bit binary adder and some Serefnal gates, which performs A-B if A>B and else B-A. A and B are two 4-bit binary numbers 24) Design an adder/subtractor unit using 4-bit binary adder and some external gates, yo which gives out A+B if C=0 and A-B if C=1. Also provide an indicator for checking the overflow? Q25) Use the above designed circuit as block box and give a scheme for finding the absolute value of a 4-bit number? Q26) Design a circuit that generates 9°s compliment of a BCD digit using binary adder? @aive the circuit that adds two BCD numbers and gives out a BCD number? (8) How will you count the number of 1's that are present in a given 3-bit input using adder? Srikanth Alaparthi 19IN In the above circuit, the inverters have delay of T1 and T2 respectively. IN is a clock signal with 50% duty cycle and period T. It is given that T1+T2 is less than T/2 (a) What is the functionality of the circnit shown above? (b) Derive the duty cycle of output waveform? (c) What is the condition to get $0% duty cycle at the output also? 30) Give the truth table for 4:2 priority encoder in which the LSB(D0) has the highest priority and MSB(D3) has the lowest priority. Q31) You have three delay elements D1, D2, D3 that delay a clock by 25%,50% and 75% respectively. Design a frequency doubling (fout = 2 * fin) circuit that uses these delay elements along with any combinational logic. Q32) Give a combinational circuit which checks out whether two 4-bit input signals are same or not? Q33) Using a 4:16 decoder and minimum number of external gates implement the following Boolean functions: (a) FAB.CD) = ¥ (5,7,9,14) (6) GAB.CD) = ¥ (0,1,2,3,4.6,7,8.9,10,11,14,15) Answers: Al) (a) For a 2:1 mux, whose inputs are 10,11 and select line S, the out put is given by the following boolean expression: Out =s'I0+ST1 The AND-OR Implementation (AOD) is shown below: 10 ne Srikanth Alaparthi 20(b) The NAND gate implementation is: 10 an? IL A2) (a) NOT Gate using a 2:1 Mux: (6) AND gate —_| 0 — 0 1 wg ol AANDB o—n, B Ws A A (©) OR gate (d) XOR gate B 10 B 10 0 ° — AORB — AXORB 1 I , B gs A A To get B’, we need an extra 2:1 Mux, as inverter. Similarly NAND, NOR, XNOR gates can also be implemented. All these implementations need 2 2:1 Muxes (similarly to XOR gate). A3) 16:1, mux will have 4(S3 to SO) select lines and 16 (115 to 10) data lines. $3 will be 0 for 10 to 17 and will be 1 for I8 to IIS. So $3 is used as a select line for the 2:1 Mux. The complete design is shown below: Srikanth Alaparthi 2110 10 to To o;—_ a 0 $2 S1S0 — 10 o-— 82 SI So —iu ouT Is 0. to to 0 83 115 i 2 SISO $2 $1 80 Ad) Y=AVB'C+A’BC’ + ABC’ = ABC = A XORB XOR C AS) 0 c 4:1 Mux Y c 1 A B The majority function gives 1 if the input has more number of 1s than zeros. The truth table is shown in Chapter 3. If A=B=0, the output will be zero irrespective of C. If A=B=1, output is | irrespective of C. But if A=1,B=0 or A=0,B=1, as we can not decide the majority without knowing C. So 10 = 0, II=12 = C and 13 =1. The implementation is shown above. If we simplify the expression it gives, Y= AB+BC+ AC A6) Shannon’s expansion theorem is highly useful in implementing a Boolean function, using Multiplexer. (a) To get f(x,y.z) = x°z’ + xy + xz in terms of x, first use Shannon’s expansion theorem to get the following co-factors. The cofactors are: & = flyz) =y+z Srikanth Alaparthi 22fe= f(0,y.2)=2" So, f(X,y,2) =x 7x" fy (b) Now we can use x as select line and implement f(x,y,z) using 2:1 mux 10 fixy.z) Ny y x A7) We need a 8:1 Mux at the input side and 1:8 Demux at the receiver side. We may need an 8 bit counter which mins at the same clock speed on both the sides to select one of the user. A8) A 2:4 decoder will have 4 O/Ps which are the minterms of the 2 inputs : AB, AB’. AVB, A’B’. Ont of the four outputs that are needed, AB and (A+B)’ = A’B’ are directly available. Whereas A~B can be obtained using the extra 2 input OR gate (which is given). So only O/P that is needed is (AB). (ABY = A’ +B’ = A’(B+B’) + BAA’) = AB + AB’ = AB? So use 3-input OR gate to obtain (AB)’. The whole design is shown below Decoder A 1S; Dy AB ENB A9) (a) Truth table for Half-adder: A |B | Cout| Sum o fo o fo ofa o [1 1 [0 o [i iii 1 1 Srikanth Alaparthi 23(b) Truth table for Half-Subtractor: A |B | Bout| Dir o [0 0 |o oa 1 1 1 fo o [1 1 it oo 10) From the above truth table (A9(b)), we can derive the following equations for barrow and difference: Borow = Bout=A’B Difference = Diff= A XORB The same equations can be shown using basic gates. (SOR, NOT, AND) All) The HA equations are, Cout = AB and Sum = A XOR B= AB’ +A'B. ‘Sum XOR Cout = Sum’ Cont + Cout” Sum (AB+AB’) AB + (A’+B’) (A’B+AB") AB+A’B+AB'=A+B So to get OR gate we need two HA. The Sum and Cout of fist HA are given as inputs to second HA. The Sum of second HA gives the A OR B. Al2) Sum = A XOR B XOR C and Carry = AB + BC + AC Full adder from 2 HA and one OR gate: A carey \- aa 7 caRRY B sum s “our Cin aM ‘suM_our A13) Sum= A XOR B XOR C and Carry = AB + BC + AC Srikanth Alaparthi 24c © 4:1 Mux Sum e c l | A B 0 ic 4:1 Mux Cout c 1 I | A B A14) The suitable equations are: Sum =(A XOR B) XOR C Cout= AB+(A XOR B)C The implementation is as follows: 5 ot ) >] Gi FL Cin A15) Two possible implementations of an adder are (a) Ripple carry adder and (b) Carry Look Ahead adder. (a) The ripple carry adder for adding two 4 bit numbers, A and B is shown below: Srikanth Alaparthi 25AB BB “si le ‘$3-S0 indicates the final result and Cout is the final carry. Cout 3 (b) Camy Look Ahead (CLA) From the figure that is shown (Al4), we can derive the following intermediate equations: P,= A; XOR B, and Gi= A; AND B, Now, Sum =P; XOR C; and C1 = G+ PC; 2) Using this equation for carry, we can generate the following algorithm for carry look Gy+ PiC1= Gr+ Px(Go+ PoCp) and so on. By using these recursive equations, we can look a head and decide the cartier, unlike in case of ripple carry adder. So the three steps involved in CLA adder are: Step]: Generation of Pi and Gi from Ai and Bi using Eq(1) Step2: Generation of carrys using Eq(3) Step3: Finally getting the Sum from Pi and Ci using Eq(2) ‘A16) In ripple carry adder, the carry propagates from first adder to last. As it has to pass through all the adders, the delay in getting the final output is considerably high. Where as, it is hard-ware efficient. The scheme for CLA is explained in the previous question. The major advantage of CLA is faster output. But it needs more hardware. A17) To perform the delay calculations, use the circuits that are shown in above answers. (a) For full adder the best implementation is shown in Al4. XOR gate delay = 10ns and AND/OR gate delay = Sns The delay for each adder = 10 + 10 + $ = 2Sns. For adding 4-bits, we need 4 such adders, so overall delay = 100ns (b) For CLA, as explained in A15, we need 3 main steps: Srikanth Alaparthi 26Step]: Generation of Pi, Gi: The XOR gate delay = 10ns Step2: Generation of carry: And-Or stage = Sus + Sus = 10ns Step3: Sum generation: One more XOR operation = 10ns So the overall delay = 30ns A18) The carry out of a full adder is equivalent to Majority function. Majority function, Y = Cout = AB + BC + AC A19) The truth table for full subtractor is shown below: Bout | Diff 0 —|-|-|-|oleleloly —|-lolol—|-Jolole —|o|-|o|—le)-loln Diff= A XOR B XOR C and Bout = BC + A'(B XOR C) To implement full subtractor from full adder we need to XOR one of the inputs with 1 and then give to full adder as shown in the figure. Diff FA Bout L____] A20) FO + Fl generates 4 carries, FF+FF and FF=F1 generates 8 carries. Whichever generates less number of carries, that one will give the fastest output. So FO+FI gives fastest output. A2l) Casel: Unsigned Numbers: In N-bits, We can represent numbers from 0 to (2°N) - 1. Suppose if we are adding 2 N bit unsigned numbers and if the result is greater than (2°N) - 1 , overflow will occur. To detect this, check whether the MSB addition (Nth bit) + Carry generated from (N-1) bit addition is generating any carry or not. If there is carry out, there is overflow. Case2: Signed Numbers: In N-bits, we can represent numbers from -(2“(N-1)) to (2*(N-1)) - 1. Suppose if we are adding 2 N bit signed numbers and if the result is not in the above range, overflow will occur. To detect overflow in this case: Srikanth Alaparthi 27+ The sum of two positive numbers is negative + The sum of two negative numbers is positive; + Subtracting a positive number from a negative one yields a positive result; or + Subtracting a negative number from a positive one yields a negative result. A22)Y¥=3A=2A+A. The 4-bit binary adder which is shown in A1S (a) can be used as a block box here. As 2 can be obtained by simple right shift operation, one binary adder is sufficient for the complete design. AB A2 AL AO [1° B3 B2B1 BO A3 A2Al Ad 4-bit binary adder co -— 3A - A23) Note that A-B = A + (-B), That is, to subtract B from A, just find the 2’s of B and add that to A. IA > B, the comparator gives 1 at A>B and zero at rest of the outputs. That 1 is used as one of the inputs to the XOR gate, to find the 2°s compliment of B. Similarly, in case of A, =-A otherwise We can use the above designed adder/subtractor unit to accomplish this task. The MSB of ‘A, which will be 1 if A is negative, can be used as C. A3 AZ Al Ao A3 o 0 0 0 uf [ | [ ; ["B3 B2 BI RO AD 4-bit Binary adder co AB Srikanth Alaparthi 29A26) A3 AZ Al AO too ot B3 B2 BI BO A3 A2 Al AO 4-bit Binary adder co |} Cout 83 S2 $1 $0 9-4 (9'5 compliment) 9°s compliment of a BCD number d is given by 9-d. That is just find the 2’s compliment of d and add that to 9. Cout is needed. Just the $3-SO of the binary adder, shown in the above figure, gives the required result. A27) The BCD addition is explained in Chapter. If the result is above 9, it is needed to add 6 to obtain the result in BCD number system. So we need two 4-bit binary adders: One is just to add the two BCD numbers, The second one is for adding 6 or 0 to the result. Extra combination logic is needed to identify the overflow. The condition for detecting the overflow can be derived as, K=Cout + $3 $2+$3S1 K = 1 indicates the overflow and addition of 6 is needed. The complete design is shown below: Srikanth Alaparthi 30BCD No2 BCD Nol [|] jj) {1 3 B2 Bl BO A3 A2 Al AO gh. 4-bit Binary adder co}-— cin $3 $2 SI SO B3 B2 Bl BO A3 A2 Al AO 4-bit Binary adder CO Cout $3 $2 Sl SO Carry out Sum of the 2 BCD numbers A28) The binary number that is formed from the Carry out as MSB and Sum as LSB, gives the number of 1s of input. The same thing is illustrated in the following table. The sixth column shows Cout-Sum together where as the last column shows the actually number of Is in the input. Note that both are exactly same. > bs ‘Cout 0 ‘Cout-Sum 0010) od) oid) 10(2) od) 10(2) 10(2) 118) -l---[+-[[° 2 ~lelo|-o|-|-Jo|¥ E -[-|-le/-lele A29) (a) The circuit works as frequency doubler. That is, it gives double the frequency at the output. But the duty cycle depends upon the delay of the gates. Srikanth Alaparthi al(b) - L] ii T1472 If you observe the output, it will be on for (T1+T2) duration, And the total period is T/2. (As output frequency = 2 * input frequency) So duty cycle = (11+! T+ (€) To get 50% duty cycle, T1 + T2 should be equal to T/4. So you can use two inverters each with a delay of T/3. A30) Encoder functionality is opposite of a decoder. The output of an encoder corresponds to the binary code of the input. There is a chance that, in the input stream, more than one I may present. In that case, to avoid clash, we need to provide the priority to any one of the bits. Here the truth table for priority encoder which gives, highest priority to its LSB, is shown: Input Output D3_p2_DI_—~iO x y oo o 0 x x xx x it 0 0 xX xX 1 0 0 1 x1 oO 1 0 10 oo 1 1 A31) The simple design using XOR gate is shown below, (Similar to A29) DI fin A32) For finding out whether two signals are equal or not, the best logical gate is XOR. The design is shown below. OUT =1 implies that the two binary numbers are not equal. Srikanth AlaparthiA33) The decoder gives all the possible minterms at the output. We need to just OR all the corresponding minterms to get 2 particular Boolean functions. If a Boolean function hhas more minterms which are 1, then take all the minterms which are zero and use NOR gate. Here in case (a) we can directly use OR gate. But case (b), NOR gate is to be used to get the optimal solution. @ * 4:16 deccoder — B 5 OF c +> 7 D ss } > 14 ) . a 4:16 deccoder B 5 G D 2 - 13) Srikanth Alaparthi 33Chapter 5: Introduction to flip-flops Questions: Q1) Mention two basic applications of flip-flops? Q2) What is the difference between a LATCH and a Flip flop? Q3) What is transparent latch? @ Implement $-R Latch with control input using 2-input NAND gates? Which input combinations are not allowed in (a) NAND based (b) NOR based $-R ‘Sitch? Explain, Q6) How to convert §-R Latch to transpareat latch? Q7) Design @ D-lateh using 2:1 Mux. @)pssien a master-slave D-Flip flop using D-Latch? ) What is ace-sround condition? Explain it incase of J-K Latch and solution to avoid Qe have a circular wheel with half painted black and the other half painted white. fefe are 2 censors mounted 45 degree apart at the surface of this wheel( not touching the wheel) wiich give a "1" for black and "0" for white passing under them. Design @ circuit, using DFF to detect which way the wheel is moving. Can not assume any fixed position for start. QiT)Give the characteristic table and characteristic equation for I-K Flip-flop? (@13) Construct a 4-K flip flop using a DFF, 2:1 Mox and an-inverter? Q13) Implement T-flip flop from D-flip flop? Q14) Show how to convert JK flip flop into (a) T-flip flop (b) D-flip flop? 5) What is excitation table? Gown the excitation table for T-flip flop? Q17) Draw the circuit for a D flip flop with Synchronous Reset? Srikanth Alaparthi 34Q18) Which flip-flop can be used as delay switch? Q19) Which flip-flop can be used as toggle switch? Ising DFFs and minimum no. of 21 Mux, implement the following XYZ flip-flop. XY Z Qt 0 0 0 1 o o 1 0 o 1 0 0 o 1 1 1 1 0 0 ay 1 0 1 ay 1 1 0 Quy 1oro4 a) Q21) A AB flip flop has 4 operations: clear to 0, no change, compliment and set to 1, when inputs A and B are 00, 01, 10 and 11 respectively. Derive the characteristic equation? 22) Give the excitation table for the AB flip flop described in Q20? 23) Show how the AB flip-flop can be converted to a D flip-flop? 4 ne = G3pnw the output waveforms Q and Q” for a NOR based S-R Latch for the $ and R forms shown in the following figure if each NOR gate has a delay of 10ns s R “Tons” Design a TFF using only 2:1 Muxes? N (Change-No change) flip flop, there won't be any change in output as long. AST is 0, irrespective of C. If N=1, then if C = 0 output will change to zero else if C = output will be the compliment of previous output. (a) Write the characteristic table ? (b) Design this using J-K flip-flop? Srikanth AlaparthiAnswers: Al) The major applications of flip-flops are: > Data storage » Data transfer > Counting and > Frequency division A2) The differences between a LATCH and a FLIP-FLOP are: ® Latch is a level sensitive device where as flip-flop is edge sensitive > Latch is sensitive to glitches on enable pin and flip-flop is immune to glitches > Latches take less gates(also less power) than flip-flops > Latches are faster than flip-flops. A3) D-Latch is called transparent Latch. As it transfers the data as it is to the output on enable. A4) S-R Latch with clock using 2-input NAND gates is shown below: 5) (a) S=R=0 (b) S=I A6) Transparent latch from S-R Latch: > + $“@Q Rar Q CLK Srikanth Alaparthi 36A7) D-Latch using ‘Mux: CLK AS) 2 Delatches and an inverter are needed to get the master-slave configuration. The major advantage of master-slave configuration is avoiding the race-around condition as the input changes only at the edges. DIN CLK A9) The race around condition means: the output oscillating between Os & Is This problem will occur in Latches especially if the clock is high for long time. In case of FK Latch, gives Q(t+L) = Q(t)’. Consider the case when clock is high for long time and F Then the output oscillates between 0 & 1 continuously as long as the clock is high. To avoid this, use Master-Slave configuration which latches the input only at clock edges. So in that case, irrespective of the duration of clock high, output will be just compliment of previous output. There won't be any oscillation as such. A10) The sensor will give 1 for Black and 0 for white. First we will draw the outputs of the sensors assuming some position of the wheel. Assume that the initial position of the Wheel is as shown in the figure with respect to the sensors. The output waveforms of SI and $2 will be as follows. Both clock wise and counter clock wise wave forms are shown. here, It is clear from the waveforms that there is an initial delay of 22 4 degrees benween the two waveforms (assuming the to sensors are at the same distance from the partition), Initially $2 = 0 and S1 =1 because of their initial positions(this is just our assumption). Once the wheel started moving in anti-clock wise direction, $1 will go to 0 from | after 22% degrees. And then gets complemented once in 180 degrees. In this case, 2 will go to 0 to 1 afier (180 -22 *% ) degrees and then complements once in 180 degrees. Srikanth Alaparthi a7Similarly we can analyze for clock-wise case also. The waveforms for both the cases are shown below. (a) For Clock-wise case the waveforms ar 22% ST 180-22 4, Clock-wise rotation (b) For anti-clock wise, the waveforms are: sl 22% en ee 1-22 Ve - P ‘ sa022! Anti-Clock-wise rotation These two wave forms are connected to DFF as shown in the following figure. That is $1 to the clock and S2 to the D input. our If you observe the above waveforms, for clock-wise direction, whenever there is a rising edge of S1, S2 is always 0. For anti-clock wise direction, at the rising edge of SI, S2 is 1 always. That is OUT =1 in the above circuit indicates the clock-wise rotation and OUT = 0 indicates anti-clockwise rotation. Srikanth Alaparthi 38AI1) The characteristic table for J-K flip flop is: I K Qe ojo Qn) oO 1 oO 1 oO 1 1 1 Qi To get the characteristic equation, we can use K-Map with 3 inputs, J.K and Q(t) and obtain, AHL = TQ +E Qt) A12) The complete design is shown here. The catch here is to use Q as select line. You can observe the cofactors of Q(t1) with respect to KK and Q(t). Using J or K as the select line with 2:1 mux will not do, A13) T-flip flop using DFF: Al4) (a) TEF: Kar Q Srikanth Alaparthi 39(b) DFF: 5 J=@ K ar Q A15) During the design process we usually know the transition from present state to the next state and wish to find the flip-flop input conditions that will cause the required transition. For this reason we will need a table that lists the required inputs for a given change of state. Such a list is called the excitation table A16) The excitation table for T flip flop is shown below. Q@ [aa [Tt 0 0 0 oO 1 1 1 0 i 1 1 0 A17) Synchronous reset will clear output only at clock edge unlike asynchronous reset. At clock edge, if syn_rst = 0, output will be 0 otherwise output will be D. So we just need an AND gate before the DFF as shown in the figure. Syn_r A18) As DFF transmits the data as it is to the output, it can be used to provide one clock delay. A19) In TFF, if T switch. ; output just toggles between 1 and 0. So TFF can be used as toggle A20) From the given characteristic table, itis clear that if X=0, Q(t+1) = Y XNOR Z. If X =1 and if (Y XNOR Z), Q(+1) = Q(p, else Q(". So we need two 2:1 mux to generate Y XNOR Z. One to select Q(t) and Q(t)’ and one more to select between X=0 case and X=1 case. Total we need 4 2:1 mux. The design is shown here except the generation of Z”, Srikanth Alaparthi 40out CLK out A21) The characteristic table is shown below: A B Quy 0 0 0 0 1 Qo 1 o Quy 1 1 1 The characteristic equation can be derived as, Qlt+1) =A Qty’ +B Qt) A22) The excitation table for AB flip flop is, Qa TA B 0 0 0 a 0 1 1 x 1 0 x 0 1 1 x 1 A23) To get D from flip-flop from AB flop, just connect A We can prove this from the characteristic equation , QU) =D Qn’ +D QW =D()=D A24) For NOR based S-R Latch, there is no change in output for S=R=0, 0 for S=1, and 1 for S=0 and R=1. The waveforms are drawn using this. (Delay of NOR gate = 10ns). Assume that initially Q= 0 and so Q’ = 1 Srikanth Alaparthi 4lA26) (a) The characteristic table for C-N flip flop is, c N Q(t) 0 0 ro) oO 1 o 1 0 aw 1 1 Cyol The characteristic equation can be derived as, Q(t+1) = (CN) Qi’ +N’ Q(0) (b) Comparing the characteristic equation of C-N flip flop with that of J-K flip flop (Q(t+1) = J Q(t)’ + K’ Q(t), we will get, The F-input=CN and K-input =N Srikanth Alaparthi 42Chapter 6: State Machines chronous Sequential design Questions: Ql) Give the State Machine for Serial 2s complementer. Draw the complete design for the same using DFF? @ CN os y~) Woo’ 1 } }___+__—of {010 } 4 —< ae (a) Write the output sequence for the input sequence: 0010101 10110110111 (b) What is the functionality of above FSM? (c) Which flip-flop can be used to implement above FSM with out any external logical gates? Q3) Give the state transition diagram for J-K flip flop? Q4) A sequential circuit with 2 D flip-flops, A and B and an external input x, is specified by the following next-state equations: A(1) A+xB B(HI)=xXA'+x'B (a) List the state table showing present state and next states? (b) Draw the corresponding state diagram? (c) Explain the functionality of the circuit? Q5) The sequential circuit oscillates in any of the following cases as long as the extemal input X = 0 based on the initial state Case (a) :00 > 019 00 9 01 ....0r Case (b): 10 119 109 11 And if X =I, if itis currently in Case(a), the circuit switches to Case(b) and vice versa (a) Draw the state diagram? (b) Implement the circuit using two J-K flip flops and external gates? 6) What is Moore model & Mealy model? Explain. Q7) Give the State Machine for detecting the sequence “1010” from a serially coming data, Q8) Repeat Q7 for Non-overlapping case. Srikanth Alaparthi 43Q9) Draw the state diagram to output a'"1" for one cycle if the sequence "0110" shows up and the leading Os cannot be used in more than one sequence. Q10) Describe a finite state machine that will detect three consecutive coin-tosses (of one coin) that result in heads. QIL) Reduce the following state table: Next State fT Present State | _x=0 x= x= xl a a b 0 0 b e c 0 1 © a d 0 1 d e £ 0 1 e a £ 0 0 ric Al a 0 1 eA a b 0 0 Q12) Starting from state a, write the next state and output values for the input sequence: 01010101001 for both Original and reduced state table. Eg: UP 0101011001 OP 0001011100 Eg: /P 0101001101010 OP 0001100001111 Eg IP :0010101101000 OP :0001111001100 Eg: LP 01001101100 OP 00000111110 Q17) What is one-hot method? List the advantages and disadvantages? QI8) Show the state assignment using Johnson’s method for a FSM of 6 states? Q19) How many flip flops are needed to design a FSM having N states if the state assignment is done by using (a) Binary (b) Gray (c) One hot (d) Johnson Srikanth Alaparthi a420) cf cLK =D [> The block diagram shown above has one input “IN” which is coming serially @ clock, “CLK”. It has 4 outputs A, B,C & D . A will be 1 if IN has even number of I's & even number of 0's. Similarly B will be 1 for even 1°s odd 0°s, C for odd 1's even 0's and D for both odd. Give the FSM required to design above block. Q21) For the above problem, which method is more suitable for state assignment? For instance, if the input stream we output a" 101 is 5). If we then get a "0", the aggregate total is 10, so we output another "1" (and so on). Input Sequence. Value Output 1 1 1 0 o 10 2 0 1 101 3 1 0 1010 10 1 1 10101 2 0 Q23) Draw the FSM for checking whether the two inputs P and Q have same value for the last three continuous samples? Eg: A 00110010110 B 00000011010 OP 01010111010 Srikanth Alaparthi 45The system is initially in state Sa. If * represents zero or more occurrence of a logic level and ~ represents one or more occurrence of a logic level which of the following best describes the sequence of states the system could have gone through if it is finally in state Sc. a) O* > 1+ DO+ b) oF > IF Se ©) O FOF D1 d) 0+ > 1+ DOF Answers: Al) State Machine for Serial 2's complemente Logic: Starting from LSB, retain all the bits till first one has occurred including the first one and then complement all the following bits. State Definition. State a: No one has occurred State b : After first one has occurred State Diagram. Con Nt a } Ae 7 Design using DEF: Ps [INPUT [Ns | OUTPUT o@ [0 o(@)_[o oa) [1 1b) [1 1) [0 ib) [1 1) [1 1b) [0 Srikanth Alaparthi 46A?) (a) INPUT Sequence O10110110110111 OUTPUT Sequence :001000100100100101 (b) Note that the OUTPUT is 1 if the input (that has arrived till now) contains odd number of I’s, So the FSM shows the functionality of serial odd parity indicator. (c) The state table is as follows: PS [INPUT [NS_ [OUTPUT 0 0 ojo 0 1 1 1 1 0 1 1 1 1 o fo The state table shows that NS = OUTPUT = PS XOR INPUT This is same as the characteristic equation of T- Flip flop. a3) 00 or 10 \ ¥—~) \2~\ 100811 (a0) bit) —*~ es ——Wor 14 Srikanth Alaparthi a7Aa) A(t) =xA+xB B(t+l) =xA’+Xx"B (a) State Table: Present State] Next State AB A(t) BO) 0 0 0 [0 0 0 0 1 fo 1 0 1 o [o 1 0 1 1 1 1 0 oi 0 1 0 1 [0 0 1 1 oft 1 i 1 1 0 (b) State Diagram. = 1 (0 +1 > WTS o/ oO” (¢) Functionatity: This circuit works as enable based gray code counter. transition takes place in gray code counter and if X=0, there won't be any change in the present state AS) One of the possible FSMs is shown below: a Srikanth Alaparthi 48State table and flip flop inputs. Present State [INPUT | Next State Flip Flop inputs A B x A B Jy Ky pK 0 0 0 0 1 0 x I ne 0 0 1 1 0 1 x 0 x 0 1 0 0 0 0 x x 1 0 1 1 1 1 1 x x 0 1 0 0 I 1 x 0 1 x 1 0 1 0 0 a 1 0 x 1 1 0 1 0 x 0 x 1 1 1 1 0 1 of 1 x 0 Design using JeK Flip fl The simplification using K-Map gives, Ja=X,Ka=Xx, Jg=x',Ka=x° x cLK A6) A state machine consists of set of states, initial state, input symbols and transition function that maps input symbols and current state to next state. Mealy machine: machines having outputs associated with transition of input and the current state. So Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle. Moore machine: machines having outputs associated with only states, that is the outputs are the properties of states themselves. The output will vary only after the states are Srikanth Alaparthi 49varied. So the changes in the output will be only during clock transitions and the outputs are held until you go to some other state Advantages and Disadvantages: In Mealy as the output variable is a function of both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output is dependent on only states and not the input signal level. Ay) State Machine for detecting “1010”. Logic: Check for the bit pattern 1010. The end “10” has to be reused for next pattern, State Definition. State a: No 1 detected state State b : One | detected state State ¢ : 10 detected state Stated: 101 detected state State Diagram: A8) State Machine for detectins Logic: Check for the bit pattern 1010. The end “10” can’t be reused. So after detection of one patter, just go to initial state. (Here it is State a), State Definition State a: No 1 detected state State b : One | detected state State ¢ : 10 detected state State d : 101 detected state State Diagram: Srikanth Alaparthi 50A9) State Machine for detecting “0110”: Logic: Check for the bit pattern 0110. The end “0” can’t be reused. So after detection of one pattern, just go to initial state. (Here it is State a). That is non overlapping case. State Definition State a: No 0 detected state State b: At least one 0 detected state State ¢ : 01 detected state State d: O11 detected state State Diagr Al0) State Machine for detecting “111 Logic: If we represent Head with logic | and tail with logic 0, Checking for 3 consecutive heads is nothing but pattern matching for “111” (overlapping) State Definition: State a: No 1 detected state State b : One 1 detected state State c: More than Two 1's detected state State Diagram 10 All) To remove a state, we need to have another state with the same next state values and output values. If we observe the given state table, state g has all entries same as those of state a. So state g can be replaced with a everywhere. Once g is replaced with a, all the entries of f are same as those of c. Thus, replacing f with c, makes state d same as state b. So with all these changes the reduced state table is shown below: Srikanth Alaparthi slOutput Present State 1 x=0 x=1 a 0 0 b 0 1 e 0 1 e 0 0 Al2) (a) For Original: The input sequence: 01010101001 Next state aabefg beaaab Output sequence 000000 00000 (b) For Reduced: The input sequence: 01010101001 ‘Next state aabeca beaaab Output sequence 000000 00000 Al3) State Machine for detecting more than one 1 in last 3 samples: Logic: Check for the patterns 011, 101, 110 or 111. These 4 patterns have more than one 1 State Definition: State a: No | detected state, continuous 0s State b: Oue 1 detected state, “01” or “1” detected state State ¢ : Atleast two Is detected state, “011” or “111” detected state 10” or “001” detected state State d State Diagram: Ald) State Machine for detecting “101” in last 4 samples. Logic: Possible patterns are: 0101,1101,1010,1011 (overlapping) State Definition. State a : Continuous 0s Srikanth Alaparthi 52State b : Atleast one 1, that is “01” or “111...” State ¢ : 010 detected state State d : 0101 of 1101 detected state State Diagram: 15) State Machine for detecting alternative 1’s and 0's in last 3 samples: Logic: Check for the patterns 101 of 010 in last 3 samples. State Definition. State a: No | detected state, continuous 0s State b : One | detected state, “01” or “1” detected state State ¢ : “10” detected state State d: continuous 1's detected state State Diagram: Al6) State Machine for eliminating short length pulses Logic: The | after two successive 0°s will be made 0. Similarly the zero after two successive 1’s will be made 1. If you are continuous 1s state, minimum 2 0’s zeros are needed to switch to continuous 0s state and vice versa. State Definition: State a: Continuous Os State b : One | in between 0s Srikanth Alaparthi 53State ¢ : Continuous 1s State d : Oue 0 in between Is State Diagram: Aly) One-Hot encoding of FSM uses one flip-flop per state. Only one flip-flop is allowed to have ‘logic 1' at anytime. For example, for a five state FSM, the states are "00001", "00010", "00100", "01000", "10000", All other states are illegal. One-Hot encoding trades combinational logic for flip-flops. One hot reduces the next state and output logic complexity. Its good for ‘flip-flop’ rich implementation technologies. Because the combinational logic is reduced, the length of the critical path can be reduced resulting in a faster FSM. Speed increase is more significant for larger finite state machines. The disadvantage is we end up in using more number of flops. A18) Johnson's method: 000,001,011,111,110,100 A19) (a) Log:N (b) LogN (N @N2 A20) State Machine for identifving whther the 1's and 0's are even or odd: Logic: The only 4 possibilities are even-even, even-odd, odd-even, odd-odd. So initial state will be even-even as no 1 or no 0. Now if 1 comes it will be even 0s odd 1 Similarly if 0 comes it will be odd 0's even I's. So the state transition will take place according! State Definition. State a : Even 0°s Even I’s State b : Even 0s Odd 1’s State c : Odd 0’s Even 1's State d : Odd 0’s Odd 1's Outputs: In state a, outputs are: A Srikanth Alaparthi 34In state ¢, outputs are: A In state d, outputs are: A State Diagram: A21) One hot method. a: 1000, b: 0100, c : 0010, d : 0001 These values are nothing but the four outputs that are needed. So it reduces the output logic complexity. A22) State Machine to detect whether the serial binary number is divisible by 5 or not: Logic: From the given example we can notice that the data is coming from MSB side. And the possible reminders are 0,1,2.3.4. So we need to have five states each for value and output is made 1 if we reach state ‘a’, reminder 0 state State Definition: State a : Reminder 0 State b : Reminder 1 State c : Reminder 2 State d : Reminder 3 State e : Reminder 4 State Diagram: 55 Srikanth Alaparthi23) State Machine to check whether the two inputs have same value for last 3 samples Logic: As there are two inputs, at each state we will have four possible transitions based on the two input combinations. IfP=Q=1 or P=Q=0 go to next state, otherwise go back to initial state. State Definition: State a: P is not equal 0 Q State b : P=Q for last 1 sample State ¢ : P=Q for Atleast last 2 samples State Diagram Out of the two bits that are shown on the arrows, first 1 is for input A and second one is for input B. 01/0.0F 1010 91/0 or 1010 00/1 or 14/4 ae a \ <> a (0010 oti” Joomortat 01/0 or 10/0 A24) State Machine with two inputs- Number of 1's together multiples of 4: Logic: As there are two inputs, at each state we will have four possible transitions based on the two input combinations. Just count the number of 1’s in X and Y together and check for the reminder if that number is divided by 4. The possible reminders are 0.1.2.3. The output will be 1 if the reminder is 0. State Definition: State a: Reminder 0 State b : Reminder 1 State ¢ : Reminder 2 State d : Reminder 3 State Diagram: Out of the two bits that are shown on the arrows, first 1 is for input A and second one is for input B. Srikanth Alaparthi 56A25) State Machine with two inputs Logic: As there are two inputs, at each state we will have four possible transitions based on the two input combinations. The output will be one for the first time, if A has same value in the last two clock ticks. After that, output can be made 1 either by condition A or condition B. § for initial transitions B will be don’t care. But once output is 1, that if you are in state d or e, as long as B is 1, the transition will be between d and e only and the output is also 1 State Definition: State a : Initial state State b: A is 0 once (B can be either I or 0) State c : A is 1 once (B can be either 1 or 0) State d : A has same value for last two samples and it is equal to logic 0 State e : A has same value for last two samples and it is equal to logic 1 State Diagram Out of the two bits that are shown on the arrows, first 1 is for input A and second one is for input B. X indicates don’t care, that is the input can be 1 or 0. A26)a Srikanth Alaparthi 37Chapter 7: Setup time and Hold time Questions: QU) Define (a) setup time (b) hold time (c) clock to Q delay. * «Which of the following Dip flops can work at maximum frequency? 1 FF2_| FF3 ‘Setup time(ns) Hold time(ns) F Clock to Q delay(ns) |__ 5 3 2 Hlelo Q3) Derive the maximum frequency of operation for the following circuit in terms of Teg, Tsu and Th of the flip flop? >—© D Q ., DFF Q CLK Qa) For the above configuration with dly = 0, which of the flip flops that are shown in 2. can be used if the available clock period is (a) Sns (b) Sns (c) 15s Q5) Design a circuit for clock frequency divided by 2 using DFF. Given the following information, find the maximum clock frequency that the cireuit can handle? ‘T_setup = 6s , T_hold = 2ns and T_propagation = 10ns Q6) Is there any hold violation in the above circuit? When will the hold violation occur in a given circuit and how can it be solved in circuit level? Describe in detail. a Srikanth Alaparthi 58(a) Will the above circuit work without any violation? (b) Calculate the new value of “dy” to avoid the violation, if any? (c) Will the delay of CLK_BUF affect the maximum frequency of operation? Q8) What is clock skew? Explain. Q9) Can hold time be negative? Explain, Q10) Among the flip flops that are shown in Q2, which combination can give maximum frequency of operation for the following circuit? — +p @ dD Qu IN our > > CLK. QI1) The following digital circuit shows two flops with a logic delay (dly1) in between and two clock buffer delays (dly2, dly3). Derive the conditions in terms of (dly1.dly2,dly3) to fix setup and hold timing violations at the input of second FF? Teq — Clock to Q delay, Tsu -- Setup time and Th — hold time. [ >-—__b e@ dD @ Teq2 Tsu2 Th a2 do you modify the circuit to avoid them? (b) For the Circuit, what is the Maximum Frequency of Operation? Srikanth Alaparthi 59tm NS Wi If both the flip flops have same clock to Q delay of 2.5us, setup time of 2ns and a hold time of Ins, what is the maximum frequency of operation for the circuit shown in the above figure? Qua) . alow — = Teq + Tsu + dly. The same thing is illustrated in the following waveform, «| LILI LI | INPUT ' Teq+dly Tsu T Ad) dly For FF1, Tsu + Teq For FF2, Tsu + Teq For FF3, Tsu + Teq As dly = 0, Tsu + Teq <=T (a) T=5ns, None of the flip flops has Tsu + Teq <= T, so no one can be used. (b) T= 8ns, FFI can be used © ins, Anyone can be used fin fout Srikanth Alaparthi oefin i fout ATU ae cr Q cq + Tsu, T>= 6+ 10. So T >= Léns. 1/16ns = 62.SMHz Using the same equation , T >: ‘The maximum clock frequency A6) There are no hold violations in the above circuit. If the hold time is greater than the propagation delay then there will be hold violation for the above circuit. In that case, buffers (even number of inverters) will be used in the feedback path in order to delay the signal in reaching back to the input. Ay) (a) Thold <= Teq + dly. But here, 2ns > 1.5 + 0.5 = 1.7ns So there is a hold violation in the above circuit. (b) dly >= Thold - Teq = 2 ~ 1.5 = 0.5ns (c) The delay of the clock buffer will not effect the maximum frequency of operation of the circuit. A8) Clock-skew: Clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times, This is typically due to two causes: 1. The first is a material flaw, which causes a signal to travel faster or slower than expected. 2. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times. Skew is only meaningful between adjacent pairs of registers, not between any pair of registers in a clock domain. A9) Yes, Hold time of a flip flop can be negative. Most of the modem flip flops will have either 0 or negative hold time. Assume Thold = -2ns, there should not be any transitions in the input before 2ns of the clock event. 10) For the given circuit, T >= Teql + Tsu2, To get maximum frequency T should be less. So we should select the first flop with less clock to Q delay and second flip flop with less setup time. So FF1 and FF3 give the ‘maximum frequency and it is equal to 1/7ns = 142.8MHz Srikanth Alaparthi 63All CLK CLK1 sd CLK2 1 INPUT AT FIRST FF I mpurarseconn ee | OPM 1} Laly+teq igyt pbb st TFT inches The above waveforms show the CLK, CLK1 and CLK2. The input waveform at FF1 is assumed and the input of FF2 is shown accordingly with all the given delays and clock- t0-Q delays. From the waveforms it is clear that, to avoid setup time violation, T >= (Tsu2 + Teql + dlyl delta) where delta ~ dly2-dly3 (assuming +ve skew) From this equation we can get maximum freq of operation. To avoid hold time violation, Th2 <= Teql + dlyl ~ delta These two equations can be used as generalized equations to solve setup time/hold time problems. This works only for synch circuits. If one clock works at pos edge and other is negative edge we need to derive one more set of equations. That also we will at later section, Al2) (a) There is a hold time violation in the circuit, because of the feedback. Teq2 +AND gate delay is less than thold2. To avoid this , we need to use even number of inverters(buffers). Here we need to use 2 inverters each with a delay of Ins. Then the hold time value exactly meets. (b) In this diagram, dly3 dly2 = 2ns so,delta = 2ns tsu2 = 3ns, teql Putting all these values in Eq(1) , T>=Teql + dlyl + Tsu2 - delta Srikanth Alaparthi 64Max freq of operation is 125MHz Al3) Teql = Teq: ‘Tsu = Tsu? = 2ns Tholdl = Thold: delta = clock skew = 3 - 0.5 = 2.Sns Equation for hold-violation is, Thold <= dly + Teql - delta (Eq(2)) L<=dly+2 So dly >= Ins To obtain maximum freq, fixing it to lowest possible value, so dly = Ins Using this value and Eqauation (1) of setup time, we can obtain max freg. T>=Teql + dly +Tsu2 - delta T>=25+1 5 So T>=3ns Max freq of operation = 1/3ns = 333.33 MHz Ald) Setup time: (1/2) + delta >= Teql + dly1 + Tsu2 Hold time: Th2 <= delta + Teql + dy! where delta = dly3 - dly2, assuming positive skew and T is clock period. Note: The procedure is same as that of QI1.Just draw the waveforms with proper delays, you will get above equations. A15) For FFI and FF2, TI >= (Tsu2 +Teql + dlyl — skew!) For FF2 and FF3, T2 >= (Tsu3 + Teq2 + dly2 ~ skew2) T>=MAX (TLT2) Al6) Metastable state Metastable state. Reason for occurrence: This will happen if the output node capacitance is not allowed to charge/discharge fully to the required logical levels. In case of flip flops, if the input changes in the restricted region, that is if there is a setup time or hold time violations, metastability will occur. A un-known state in between the two known logical states is called as Srikanth Alaparthi 6Way to avold: To avoid this, a series of FFs is used (normally 2 or 3) which will remove the intermediate states. The extra flip flop is called the synchronizer. A17) Given: Tsu = 2us, Th = -3ns and Teq = Sus. If hold time is negative and if its absolute value is less than Tsu, only thesetup violation equation without any modification will work. But if absolute value of hold time is more than setup time, we need to replace the setup time in the equation with hold time. The modified equation is shown below: Teql + dlyl + Max( Tsu2, | Th2 | ) S+dlyl+3 8+dlyl To get maximum frequency of operation, the minimum possible diy! = Ins So, T >= 9ns Fax = 1/9ns = 111MHz Srikanth Alaparthi 66Chapter Questions: QI) Design a 3-bit shift register control input, C = 0 and shifts left if C @ Q0 Q1 Q2 Q3 D SHIFT REGISTER A four bit shift register, which shifts data right QO > Q1 > Q2 > Q3, is shown in the above figure. The initial value for QO, Q1, Q2, Q3 is 1000. (a) Write the 4 bit values for QO, Ql, Q2 and Q3 after each clock pulse until the pattern, 1000 reappears. (b) To what values should the shift register be initialized so that the pattern 1000 occurs after 2 clock pulses? Q3) What is the difference between a ripple counter and a synchronous counter? Q4) To count from 0 to N-1, how many flip-flops are needed? QS) Design a 4-bit binary counter using TFFs? Q6) Give the FSM for a 3-bit gray code counter? 7} Eg IN : 001110110000 OUT: 0111111000 Q8) Obtain OUT1 & OUT2 from INPUT shown below? (Hint: You need a synchronizer to align INPUT with clock) Srikanth Alaparthi orclk INPUT ouTI ouT2 Q9) Give the circuit to extend the falling edge of the input by 2 clock pulses. The waveforms are shown in the following figure. Clk INPUT OUT Q10) Design a frequency divide-by-2 circuit using DFF and extemal gates which gives (a) 50% duty cyele (b) 25% duty cycle? out Design a sequential circuit which cuts the every second pulse from the input (clock) as shown above. dur ele of 1/3" Can we do it using ling counter 100 Srikanth Alaparthi 6s‘an we do it using LES lngccurer 0 QI5) DQ ) D-fp F abe |. OUT > or Q ar QU CLK In the above circuit what is the relation between input “CLK” and the output? seoutheeet eens Q17) Design a BCD counter which counts from 0 to 9999, using BCD decade counter as, black box? Q18) What is ring counter? Implement a ring counter using shift register? QU9) Ring counter implementation using 2-bit counter and 2:4 decoder is shown in the following diagram. Draw the output time signals, Q0,Q1,Q2 and Q3 with respect to the clock. Q0.Q1.92.Q3 aad 2X4 decoder __, | 2+bit counter CLK ;: Srikanth Alaparthi o)Q21) The following FSM shows the zero circulating ring counter. Predict the values of the missing states? (22) What are the unused states in a 3-bit Johnson counter? 223) What is the length of counting sequence for a Johnson counter with N flip-flops? 04) How many unused states will be there in a Johnson's counter with N flip-flops? Q25) What is the output frequency of a 4-bit binary counter for an input clock of 160 MHz? Q26) If each flip flop has a clock-to-Q delay of 10ns, how much time will it take for output to change to its next state in case of (a) 4-bit Ripple Counter (b) 4-bit Synchronous counter? Q28) Design a counter using DFF that counts in the sequence: 0.4,2,7,0.4,2,7,0,4...... 29) What is the functionality of the following cizcuit: Q Val Srikanth Alaparthi 70ois Mana eel gates and £i counter, design a crcl which gies“ ifthe Q31) Design a sequential circuit that produces a logic 1 at the output when the input has, been 1 for eight or more consecutive clock pulses using a counter(shown below) and minimum number of basic gates. 3. Q2.Q1.Q0 —+ CLK (Binary counter) CLEAR Q32) What are the frequencies Fl, F2, F3 and F4 after each stage if an input clock of 10MHz is applied? 10 bit ring (Mod-20 ripple “bit parallel ‘4-bit Johnson Fin counter_| F1"|_counter_| F2"|_counter_| ¥3 1OMHz 4 33) How to swap the contents of two 8-bit registers without using a third register. Answers: Al) The shift register is shown below. IfC =0, the circuit shifts from IN > Qx > Qs > Qe and IEC = 1, the circuit shifts from IN > Qc > Qa > Qa IN —1 ou —h Da} & > c ax @ Q, —f Q& 1h HPO Qs Lo on Q Qu ie tw I | = es ax @ cLK Srikanth Alaparthi 1A2) Dress = QO xor Q2 xor Q3 (a) Qo QL Q Q3 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 0 (b) Q0= 0, Q1=0, Q2=1,Q3=1 A3) Ripple counter is asynchronous. This means all flip flop outputs will not change at the same time. The output of one flop works as clock to the next flip flop. The state changes consequently “ripple through” the flip flops, requiring a time proportional to the length of the counter. ‘Where as synchronous counters will have same clock for all the flip flops. All ip flops will change the state at the same time. Design of synchronous counters is easy but needs more hardware Although the asynchronous counter is easier to implement, it is more "dangerous" than the synchronous counter. In a complex system, there are many state changes on each clock edge, and some IC's (integrated circuits) respond faster than others. If an extemal event is allowed to affect a system whenever it occurs, a small percentage of the time it will occur near a clock transition, after some IC's have responded, but before others have. This intermingling of transitions often causes erroneous operations. What is worse, these problems are difficult to test for and difficult to foresee because of the random time difference between the events. Ad) logsN AS) In the problem it is not clearly mentioned whether QW Qa a Q@ 2 CLK 8 Srikanth AlaparthiA6) The FSM for 3-bit gray counter is shown below. You can notice the single bit change fiom one state to another state. (100000 > Oo 1104 —¢010 A7)_ Shift register based: We need current sample, previous sample and previous to previous sample. So a 2-bit shift register is needed. The logic is similar to Majority function (Refer Chapter 4). The following figure shows the design with two DFFs and a 4:1 Mux. ingeo tune ‘our INPUT. cu AS) Shift register based: The synchronizer (the first flip flop) aligns the INPUT with clock. The second flip flop delays the input by one clock. Draw the waveforms of output of first and second flip flops and then try to get the relationship between those waveforms and OUT1, OUT2. It gives the complete solution as shown below. Srikanth Alaparthi 73Synchronizer UT ouT2 INPUT A9) Shift register based: Assumed atleast 3 clock gaps between next falling edge. Shift register of width 2 is needed. Al0) (a) 50% duty cycle: Waveforms: fin fout Srikanth Alaparthi 4le=o_l_. fot 4an-— " an Q () 25% duty cvele: The above circuit gives 50% duty cycle. To get 25%, we need to use an extra AND gate, which takes fin and fout as the inputs. Waveforms: in out Design: All) Same as A10(b) Srikanth Alaparthi 75Al2) Waveforms: fin fout Design: In the above problem, if you observe the waveforms, they are synchronous. So we can use FSM to design the circuit. If you observe the waveform clearly, output is 100,100,100 and so on. Assume 3 states: a,b & c, Initial state is a and output is 1 in this state. The state transition a->b->c->a. Output is 1 only for state a. The state table is shown below: PS NS OP abil boc 0 c a 0 With State assignment: 00-a,01-b and 10-c, we can obtain the following next state equations: A(t+l) =B, B(t+L ANOR B, OUT= A NOR B Es =a an Q con Q fi A —_—_——— Ww A13) (a) Replacing the NOR gate in the above circuit with NAND gate gives a duty cycle of 2/3. That is 66.67%. (b) To get $0% duty cycle, by observing the waveforms, we can notice that, an extra flop that works at the negative edge of the clock is needed. ORing of the input and output waveforms of this flip flop gives the required waveform. The complete solution is shown below: Srikanth Alaparthi 76(@ Waveforms. fin | Finv3, duty cycle = 0.33 | OVP of negative edge FF Fin, duty | cycle = 50% (ii) Design: fin fout Design. Srikanth Alaparthi 7Nore: The clue to get the solution is: There is a transition at the falling edge of clock. So the clock to the second flop is inverted one. The waveforms shown in the above figure, fout has a duty cycle of 1/3 To get 2/3 duty cycle, replace NOR gate with NAND gate in the above design. 15) From the given circuit we can derive the following next state equations, A(t+l) =A’ and B(ttl) = A XOR B= AB + A’B’ Taking initial values of A=B=0 and drawing the waveforms with respect to the clock using above equations, we can observe that OUT = fireq_Clock / 4 with duty eyele = 50 A16) The block box can be an up-down counter, where the “count_up_enable” is connected to the sensor at the entrance and “count_down_enable” to the sensor at the exit. ‘That is if there is no one in the room, the counter’s output will be zero. Whenever this happens make the bulb “OFF”. For 200 people, we need 8 bit counter. So The O/P of entrance sensor will be used as enable for UP count and the other sensor at exit will be used for DOWN count, whenever the counter's O/P is 0, we can make the BULB OFF, Otherwise ON. A17) Each BCD counter counts from 0-9. 93.02.91 00 att 0 a ati @ 93.92. O1 G0 BCD Counter anil Counter) BCD. Coun BCD Counter 10? digit 10° digit 10° dis 10" digit) CNT EN Srikanth Alaparthi 78A18) Ring counter: A ring counter is a circular shift register with only one flip-flop being set at any particular time, all others are cleared. This single bit is shifted from one flip flop to the next to produce the sequence of timing signals. QO Q1.Q2.Q3 Shift register ‘The above circuit shows the ring counter. The initial value of the shift register has to be 1000. Al9) LPL as L Qo Qi @ @ A20) 3-bit counter and 3:8 decoder A21) In “0” passing ring counter, at any time only one flip flop will be set to 0 others will be 1. The given state values are 23 and 29. The binary representations are 10111 and 11101 respectively. So the states are : O1111, 10111,11011,11101,11110. The decimal values are : 15,23,27.29.30. a=15,b=27 and c=30 A22) The states of 3-bit Johnson counter are: 000,100,110,111,011,001. So the unused states are 010 and 101 A23)2N A24) For N-flops, the total possible states ‘The number of states of a Johnson counter So, the number of unused states = 2°N—2N Srikanth Alaparthi 79A25) The output of last flip flop of 4-bit counter is equal to the input clock/16. So output frequency = 160MHz/16 = 10MHz A26) (a) 10+ 10+ 10+ 10=40ns (b) 10ns A27) Minimum time period of the clock = 11 x 40 + 60 = 440+60 = 500 ns So maximum clock frequency = 1/500 = 2 MHz A28) The present state and next state values are shown in the table and the complete design is shown in the following diagram. Present state Next state =lo|-lof> H|-lelolm c 0 0 oO 1 Seer lol-|-loles olHlolola Using this the following next state equations can be derived. A(HD =A" Bit+l) XORB C(t+1)=BXORC 1 ‘ a = oo = A29) Let us name the 3 flip flops as A,B and C Qo =a’ QI= AXORB Q2= (AB)XORC Starting with the next states can be obtained as: 000 > 001 > 010 > 011 > 100 > 1019 1109 111 So the circuit works as 3-bit binary counter. Srikanth Alaparthi 80A30) The output should be asserted 1 if the number of clocks is multiple of 4, that is 0, 4. 8 and 12. The K-Map simplification gives, OUT = Q1°Q0" = (QI + Q0)" Bi @ Qe Q ——* 4-bit binary counter cLK A3l) CLK (Binary counter) CLK =I IN Limitation of the design: As the design used only one counter, the maximum count is 15. 32) N-bit ring counter gives 1/N times the input frequency at the output. Johnson’s output is 1/2N times the input. Where as the counters output will be 1/(2N). MHz / 10 KHz / 8 = 390.625Hz A33) The complete design using shift registers is shown in the following figure. The main clock is gated with the clock enable so that A and B will be shifted just 8 clocks. After 8 clocks A and B will have their contents swapped. Srikanth Alaparthi 81= (Shiftregister) +} (Shift register) A B cLK2 8-bit register S-bit register U CLK CLK_EN a fr) fl fll isle lel LP CLK_EN CLK) cLK2 |! 2| [3|_ Jal [sl Jel [7] Js Srikanth Alaparthi 82apter 9: Fault Analysis and Hazards Questions: QL) What are stuck-at problems? Explain the reason for their occurrence? Q2) How many number of stuck at problems are possible for a 2 input AND Gate? Which, of those faults are not testable? Q3) Define : (a) Test Pattern/Test set (b) ATPG. (4) Explain the procedure for detecting a specific fault in a given circuit? QS) To detect the Stuck at Zero problem at marked point ‘P” in the following diagram, which of the input combinations can be used? oP Q6) Give the test pattems that are needed to verify all the stuck at problems of a (a) 2-Input NAND Gate (b) 3-input NAND Gate Q7) How many minimum number of test vectors are needed to verify all the stuck at problems of a N-input logical gate? Q8) Give the complete test set for the following circuit: & —_____ a (i Q9) What is the output F, in the following circuit, if there is (a) A stuck-at-0 problem at node A (b) A stuck-at-1 problem at the output of OR gate Srikanth Alaparthi 83Q10) What do you mean by “Path Sensitized Tests” in testing of logic circuits? Q11) Which input pattern can be applied to make the path from input C to the output F (via NOR gate —OR gate — AND gate), sensitized, in the following diagram? Q12) (a) List all the single faults that can be detected in the following circuit, using the test set “0100”? (b) Show the tests that can detect stuck-at-0 and stuck-at-1 faults at node w3? Q13) (a) Give the AOT of a 2:1 Mux? (b) Show all the paths that are possible from inputs to the output? (c) Give the complete test set for the same using the Path sensitized test? Q14) (a) Give the circuit for a 4-bit parity generator? (b) Derive the minimal test set that can detect all stuck-at-faults? QU5) What is D-notation? QU6) What are the two hazards that can be there in a combinational circuit? QI7) Match the following: (a) Static-one hazard (i) (b) Static-zero hazard (ii) (©) Dynamic hazard (ii), J I Q18) Give the characteristics of Static-zero Hazard? Srikanth Alaparthi 84Q19) Show the equivalent circuit for Static-one Hazard? ec ERR inl le shang sti fads he Hoole anton =A} Q21) How to avoid static hazards in a given circuit(single variable change hazards)? Q22) Y= AB + A’C + BC where A.B and C are input Boolean variables. The output Y, a) Glitches and can be reduced b) Will not glitch and can be reduced c) Glitches and cannot be reduced d) Will not glitch and cannot be reduced. Q24) Design 4-input XOR gate using 2 input NOR gates in all possible ways? Discuss the advantages and disadvantages of each? 25) Implement the Boolean function Y = AB + CD with the following design constraints: i) A and B arrive at t= Ons ii) C arrives at t= Ins iii) D arrives at t= 2ns iv) Alll logic gates, mux, adders have constant delay of Ins. v) Output should be available at 3ns. Answers: Al) A fault in a manufactured circuit causing a node to be stuck at a logical value of 1 (stuck-at-1) of a logic value of 0 (stuck-at-0), independent of the input to the circuit. If any rail during the layout gets connected to either VDD or GND petmanently, it will lead to these stuck at problems. A2) Total possible faults are 6. (3 nodes, 2faults for each node) By single fault model, the test patterns that are needed are: 01,10 and 11 The stuck-at-0 problems at any of the inputs and stucl-at-0 problem at the output can not be distinguishable. A3) (a) Test pattern/set : The set of all input combinations that is needed to find out all the stuck-at faults of a digital circuit. Eg: Test set for 2-input AND gate: { 01, 10.11} (b) ATPG: ATPG, or Automatic test pattern generation is an electronic design automation tool that generates the complete test set to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. Srikanth Alaparthi 8‘A4) Assume that there is only fault in the given circuit. This is called single fault model. ‘Now apply the input combination such that the correct and faulty circuits would give different outputs, ATPG Fault free circuit AS) We need to select the pattern such that none of the inputs at AB,C& D should give 0 at any of the inputs of NAND gate. So the possible pattern is: A= B =C =D=1 So we need to apply 1111 at the input, if it is correct circuit we will get, 0 at the output and if there is stuck-at-0 problem at P, we will get 1 at the ouput. A6) Single Fault method is used here. (a) 2-input NAND gate: Node For Stuck-at-0_ | For Stuck-at-1 A in o1 B 1 10 F 00 or 10 or 10, i So complete test set = { 10,01, 11} (b) 3-input NAND gate: st) c PF Node For Stuck-at-0 For Stuck-at-1 A iit oll B it 101 Cc di 10 F ‘Aileast one input HI isO So complete test set = { 011,101,110,111} Srikanth Alaparthi 86AT)N+1 A8) Single fault model is used, A = F Node For Stuck-at-0_| For Stuck-at-1 A 100) 000) B on 001 Cc on 010) F 1x (000 oF 010 oF OOT So complete test set = { 000, 001, 010, 011, 100} A9) (a) F (b) F (c-py B csp A10) If the number of nodes is more in a given circuit, itis very difficult to derive the test pattern by using single fault model (That is analyzing at each node). The other method called “Path sensitized” can be used to make the test pattern generation more efficient. In this method, all the paths from input to the output will be identified and the input will be applied such that the output will be dependant only on one particular path. And this path is called sensitized. All + To make F dependant of the high lighted path, the output of XOR gate has to be 1 This can be achieved from A=0,B=1or A= 1,B= + To make the output of OR gate to make dependant only on one input, the other input has to be 0. This can be achieved either B = 0 or C + But C can not fixed to 0. So B has to be 0. That implies A = 1 + To make NOR gate output only C dependant, D has to be 0. Srikanth Alaparthi 87So to make the given path sensitized, the input pattern that is needed is, A=1,B=0,C=1lor0andD=0 Al2) (a) 0100 at the input, makes the path A-w1-F sensitized. So it can be used to detect the following single stuck-at problems: Stuck-at-I at A or Stuck-at-0 at wl or Stuck-at-O at F” (b) Path sensitized method is used here. To make F dependant only on w3, wl = 0. So A+ Now for identifying the Stuck-at-0 fault at w3, we need to apply input pattern such that we will get 1 at w3.(C=D=1). So the required pattern is 1111 For identifying the Stuck-at-1 fault, either C or D has to be 0. So any of the following patterns can be used : 1100,1101 or 1110 A13) (a) AOT of a 2:1 Mux: Y=Sh+Sh se Y (b) All possible paths from inputs to ¥: Path :)-w;-Y, Path2 : S—w,-Y, Path3: $— w2—Wws-Y, Path4: Ip—w3-Y (c) Test vectors needed for each path: Path Test vector needed Pathi : I; —wi-Y Olx, 11x Path? : S—wi-Y 11x, 100 Path3: S—w)-w3-¥ O11, x01 Path4: Ip — w3 ~Y x01, x00 X— indicates don’t care So the complete test set is { 100, 011,11, x01, x00 } Al4) (a) The 4-bit even parity generator is shown in the following diagram: Srikanth Alaparthi 88(b) Path sensitized test: Path Test vector needed Pathl :D-Y 0001, 0000 Path2 : C—w2-¥ 0010, 0000 Path3: B— wi - wi-¥ 0100, 0000 Pathd: A—w:—w)—Y 1000, 0000 So the complete test set is {0000, 0001, 0010, 01000, 1000} A15) In test of logic circuits, normally the logic levels are represented with D. This is called D-Notation. If Logic-0 is represented with D, logic 1 will be D” and vice versa. A16) A Static Hazard is defined when a single variable change at the input causes a momentary change in another variable (the output]. A Dynamic Hazard occurs when a change in the input causes multiple changes in the output [ie. from 1 to 0 and back to 1]. In either case of a Static or Dynamic hazard the product produced is an unanticipated glitch [the hazard). The resulting glitches in the circuit may or may not induce additional problems, other then increased issues due to switching noise. There are two types of Static hazards: the high output transitions to a low and back high [a low going glitch]. Or the low output transitions to a high [1] and back low [0] [a high going glitch]. There are also two types of Dynamic hazards: the 0 output transitions to a 1 back to 0 and then 1 again. Or the 1 output transitions to a 0 back to 1 and then 0 again. A17) (a) i (i (6) iti 18) Static-zero Hazard’s characteristics: Two parallel paths for x, one inverted and reconverge at an AND gate. F=A.A’ Any circuit with a static-O hazard must reduce to the equivalent circuit of the following figure: A ss A19) Static-one Hazard’s characteristics: Two parallel paths for x, one inverted and reconverge at an OR gate. F=A+A’ Any circuit with a static-1 hazard must reduce to the equivalent circuit of the following figure: Srikanth Alaparthi 89A20) G=AB+A°C~B" IfB = C= 0, G= A+A’ (Static-0 hazard in A) IA 0, D= 1, G=B+B’ (Static-0 hazard in B) Ifa 1,G=C+C’ (Static-0 hazard in C) A21) To avoid the static hazards, one of the possible ways is delay matching. Suppose in the circuits shown above (A18 & A19), we can provide buffer whose delay is equal to that of NOT gate. But it becomes very difficult to match the delays exactly. If Static Hazards are removed from the design, Dynamic Hazards will not occur. A Karaugh map [K-map] is the easiest way to eliminate a Static Hazard or glitches. A K- map for each combinatorial logic function which has an output should be used. Redundant prime implicants should be added to the K-Map (circuit), which will guarantee that all single-bit input changes are covered. Multi-level functions will be reduced to "two-level" functions, and analyzed by the K-map approach. The procedure for designing a static-hazard-free network is a straightforward application. The key is to place the function in such a form that the transient output function guarantees that every set of adjacent 1's in the K-map are covered by a term, and that no terms contain both a variable and its complement. The former condition eliminates L-hazards and the latter eliminates 0-hazards. 22) (b) The boolean expression, Y = AB + A’C + BC can be further reduced to Y = A’C = AB. But the second expression will have hazards. So the redundant term BC is added. ‘You can observe the K-Map of the same AEC oo ol ul 10 AB A23) F(A,B,C,D) = ¥ (0.4,11,13,15) + d(2,3,5,10) From the K-Map shown below, the simplified expression for F is, F=ABD+A'C'D’+B°C But to make it Hazard free, we need to add the redundant term, ACD to this. F= ABD + A’C’D’ + ACD (Note that B’C is removed from the equation) Srikanth Alaparthi 90AB\_00_ ol 1110 | 00 | xX) oy xi i ek 10 x i \ ACD (Redundant term) A24) The two possible implementations are shown below: f) (b) If we compare both the implementations, in implementation (a), the delays from the inputs to the output, F are uniform. So there is no possibility of glitches. Where as in the implementation (b), the delays are not balanced properly. (a) is hazard free and the better implementation when compared to (b). A25) Y=AB+CD AB CAB. D,T Ons, Ins 2ns 3ns Ins Ins A \ B 10 — Y S| c —_) 2 nm) Ins Srikanth Alaparthi 1Questions: QI) What do you mean by CMOS technology? Explain with a block diagram. Q2) What are the advantages and disadvantages of CMOS logic? Q3) Why CMOS tech is widely used? a) Ease of manufacturing b) Low power dissipation c) Speed of the CMOS tech d) Low cost Q4) Show the circuit for CMOS inverter and explain the basic operation? QS) Draw the VIC of a CMOS inverter? (Q6) Arrange the following in the decreasing order of voltage levels: YousVoi.VinViL- Q7) Define: (a) Fan-out (b) Noise-margin Q8) Find the noise margin: Vou = 4V. Vir = 3V, Vor = 1'V and Vz. = 1.5V Aa PE drtpatic— Find out fan_out and propegetiendeday of a logical gate for which the following ‘Specifications are given: Veo = 5V, Iocu = mA, Ioct = 2mA, Ion = 1mA, Io. = 20mA, T= 0.05mA and In = 2mA Q10) With increase in frequency of operation the fanout, a) increases a ) decreases —> Put why ¢) doesn’t change 6 @) none of these Q11) Draw the CMOS implementation of NAND and NOR gates. Q12) The following circuit shows the CMOS implementation of a Boolean function Complete the dual PMOS network and also write the boolean function? Srikanth Alaparthi 92pull-down network Orn many minimum number of MOS transistors are required to implement the lean function, Y (A,B,C) = AB + A’C = BC using CMOS implementation assuming the inputs and their complements are available? Q14) Draw the CMOS implementation for the following circuit: @» Design a 4-input NAND gate using only 2-input NAND gates? (b) What are the minimum number of transistors that are needed to draw the gate level equivalent of the same? Gpeo many minimum number of MOS transistors are required to implement a Full Adder using CMOS technology? G@aa A&B be two inputs of the NAND gate. Say signal A arrives at the NAND gate f than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output? Srikanth Alaparthi 93Q18) Consider CMOS NAND gate. For an input sequence AB = 01> 11 > 10 > 00, the output logic level is: a)5V > 4V > OV > OV b) OV > OV > 4V> unknown ©)5V > SV >0V>4V d) None of the above QI9) Draw the stick diagram of CMOS inverter? 20) Draw the stick diagram of NOR gate. Optimize it. Q21) What do you mean by pass transistor logic? 22) Show the implementation of AND gate using pass transistor logic? 23) (a) What is the functionality of the following circuit? (b) Show the Boolean equation? (c) What is name of logic that is used in implementing the circuit? (@) Mention the advantages and disadvantages of this method. Also suggest improvements, if any, to overcome the disadvantages? 04) Show the circuit of Transmission gate and explain the functionality? 25) Why don’t we use just one NMOS or PMOS in a transmission gate? Q26) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output) Q27) Draw a Transmission Gate-based D-Latch. Q28) The output and input of a static CMOS inverter are connected as shown in the above figure. What is the output voltage? Srikanth Alaparthi 94uP 29) What are the applications of open-collector gate? 30) Using open-collector NAND gate, implement Y = (AB + CD)’ ? Q31) Four open collector gates are connected as shown in following circuit. What is the functionality? Q32) Describe (a) Three-state buffer gate (b) Three-state inverter gate Q33) Two Three-state buffers are shown below. The output of a 4 bit binary counter is, connected to the 4 inputs A, B, C and D such that the MSB is connected to D and LSB to A. For how many counter states, the circuit is sure to produce proper output( 0 of 1)? ° — L B c D Y Q34) What is Latch Up? How do you avoid Latch Up? Srikanth Alaparthi 95Answers: Al) CMOS(Complementary MOS) circuits consist of both types of MOS devices interconnected to form logic functions as shown in the following block diagram. The PUN(Pull up network) will chay the output node in case of Logic-1 and the PDN(Pull down network) will discharge by connecting the output node to ground, in this way the out put is connected either to VDD or GND continuously. PUN and PDN are dual logic networks. CMOS take advantage of the fact that both n-channel and p-channel devices be fabricated on the same substrate. Voo i WN PMOS only InN F(In4 In2,...InN) Int In2 | PDN ian NMOS only A2) The CMOS logie has two important advantages: Advantages No direct path in steady state between power and ground, so no static power dissipation(except for small power dissipation due to leakage currents) Full logic levels (The VTC exhibits a full output voltage swing between 0 and VDD. and that VIC is usually very sharp) High noise margins (Good noise immunity) Extremely high input resistance; nearly zero steady-state input current Low output impedance. Always a path to Vdd or Gnd from output node, in steady state; CMOS provides a greater packing densit Srikanth Alaparthi 96Disadvantages: + CMOS processing is more complex + Latch up problem + Slower compared to TTL + Higher cost A3)(b) A4) CMOS inverter: h Vv IN our 1 Basic operation: When input goes from 0 to 1, the PMOS will be off and the NMOS will be on, This makes the OUT to get connected with GND and goes to 0. Similarly when input is 0, the NMOS will be OFF and PMOS turns ON making the output logic to VDD. We will get full logic levels at the output. AS) Voltage Transfer Characteristics (VIC) of a CMOS inverter: A VOH ™) AG) Vor > Ver> Vit > Vor (Refer to VIC shown in AS) Srikanth Alaparthi 97Aq) (a) Fan_out: The fan-out of a gate specifies the number of standard loads that can be connected to the output of the gate without degrading its normal operation. The fan-out is calculated from the amount of current available in the output of a gate and the amount of current needed in each input of a gate. Fan_out = Min (IowIes, lor/In) (b) Noise margin: Noise margin is the maximum noise voltage that can be added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. Noise margin = Min ( Vor-Ves. Vi-Vor) A8) Given: Vou = 4V, Vin = 3V, Vor Vou-Vnn= 4-3=1 Va.- Vou =1.5-1 ‘Noise Margin = 0.5 = 1Vand Vi = 1.5V A9) (a) Fan_out Tou = LmA, To, = 20mA, Inx= 0.05mA and I = 2mA TowIn= 1 0 Tor/In = 20/2 = 10 So, Fan_out= 10 (b) Power dissipation Veo = SV, lec = IMA, Iccr = 2mA L.(avg)= (loess + Teer 2 = 1.5m. Power dissipation = Vcc * Te(avg) = 1S=7.5 mW A10) (b) 11) (a) 2-input NAND gate: a—4 b—s | OUT =(AB, Srikanth Alaparthi 98(b) 2-input NOR gate: —4 o4 our = any L AIL Re Al?) Deriving the Pull-up network hierarichally identifying sub nets as shown in the following figure: SNL E SN4 \ “A SN2 D SN3 fel The complete circuit and the output boolean function is shown below: Srikanth Alaparthi 99Al4) Srikanth Alaparthi “4 x4 eS *-q OUT=D+A+(B+C) AS B ee c [ Js D > F=((A*B). (C+D) 100“4 re 8 _J f° [x = ((A+B)*(C+D)) A15) (a) 4-input NAND gate from 2-input NAND gates: A ~ — — — B / J —, Pp c SN a D~__ L/ (b) Number of NMOS = Number of PMOS transistors = 4 (So total, 8) 16) S=A XORB XOR C and Cout = AB + BC ~ AC S can be rewritten as, S = ABC + (A+B+C) Cour” For Cout, NMOS = PMOS = 6 (Total 12) For S, NMOS = PMOS = 8 ( Total 16) So for one bit full adder implementation, minimum number of transistors that are required = 28 AB+(A+B)C Srikanth Alaparthi 101A17) The late coming signals are to be placed closer to the output node ie A should go to the NMOS that is closer to the output. Reason is, by the time A comes, B would have turned on the bottom transistor and discharged the intermediate node between the 2 series NMOS. So by the time A comes. it can discharge the output node very quickly. Als) (d) A19) Stick diagram for CMOS inverter IN ouT GND A20) Stick diagram for NOR gate out A21) Pass transistor logic: + A pass transistor is a MOSFET in which an input is applied not only to the gate but also to the drain * Unlike static CMOS, there is no need for any static power supplies Srikanth Alaparthi 102+ More advantageous in terms of number of transistors if the inputs and their complements are available + Disadvantage is : Degarded logic level as NMOS passes weak logic-1 A22) The AND gate using pass transistor logic is shown below: A GND = rs AB A23) (a) 2:1 Mux (b) OUT=Sh+S' lh (c) Pass transistor logic (d) Degraded logic 1. To avoid we need to use both NMOS and PMOS together (That is transmission gate) A24) Tranmission gate consists of one n-channel and one p-channel MOS transistor connected in parallel. The same thing is shown in the following diagram. When N is at VDD and P is at ground, both transistors conduct and there is a closed path between IN and OUT. N IN OUT = P 25) Using only an NMOS will result in an poor 1. Assume the gate voltage on NMOS is SV. IE we connect Drain to SV, and the source is initially at 0, NMOS will tum on as long as Vgs >Vth, this means, once the source reaches 4.3V (Assuming Vth=0.7), the NMOS, Srikanth Alaparthi 103will tum off and there will be no more increase in source voltage. Similarly the opposite happens with PMOS, it doesn't give us a clean 0, but it can give a full SV. So we use a combination of both NMOS and PMOS so that our signal doesn’t get degraded by Vth on either side of VDD and GND. A26) XOR Using TG: If we observe the truth table of XOR, if A is 1, output is B’ and if A is 0 output is B. Using this, we can implement the following circuit. A a AXORB A To get XNOR, just connect B directly to bottom TG and B’ to the upper TG. A27) Latch using TG: CLK Srikanth Alaparthi 104A28) The NMOS transmits the same voltage from drain to source. as long as its value is less than 4V. So in the given diagram the output and input of the inverter are same. If we observe theVTC of an inverter, Vout=Vin at Vth = VDD/2 = 2.5V.So if there is no noise floor, the output will settle to 2.5V (This is theoretical analysis). However practically the circuit will oscillate. A29) The 3 major applications of open-collector gate are: + Driving lamp or relay + Performing wired logic * Construction of common bus system 30) A31) It forms a common bus system. We can transmit one of the inputs A,B,C to the output Y by making the other inputs 0. Suppose if A=B=0, Y is C. 32) (a) Three-state buffer: c. —$|s— A ‘ Y IfC=1,¥=A and if C= 0, Y is high impedance (b) Three-state inverter: Srikanth Alaparthi 108A33) IfA=1, Y=B orlfC=1 Y=D otherwise ¥ is high impedance. So all combinations with A = 1,C =0 or A=0,C =1 or A=1,C=1 Except the four combinations : 0000,0010,1000 and 1010, The rest all combinations can give either logic-1 or logic-0 at the output. A34) Latch up: In fabricating CMOS ICs, parasitic bipolar transistors are formed as by- products of CMOS processing. These parasitic pnp and npn bipolar transistors form a SCR(Silicon controlled Rectifier) with positive feedback and virtually short circuit the power rail to ground, The generation of such a low-impedance path in CMOS chips between the power rail and the ground rail is defined as Latch-up. Guidelines to avoid Latchu * Layout n- and p-channel transistors such that all NMOS transistors are placed neat close to Vss and all PMOS transistors are placed close t0 Vpp rails. Also maintain sufficient spacings between NMOS and PMOS transistors. * Use p> guard rings connected to ground around NMOS transistors and n> guard rings connected to Vp around PMOS transistors + Use minimum area p-wells Note: Here very basic solution is given. The concept of SCR and guard rings is not given here. It is advisable to read about Latchup. Srikanth Alaparthi 106Chapter 11: Memories, FIFO and Programmable devices Questions: Q1) What is Volatile memory? Give an example. Q2) Differentiate between RAM and ROM? Q3) How many address and data lines will be there for a memory of size, IK X 8? Q4) How many number of 16X8 size memories are needed to obtain a memory of size 256X162 QS) Design a memory of size SKXS using a 3:8 decoder and the minimum number of ROMs of size IKX8 shown in the following diagram. (¢s > chip select, active high). Also show the complete address map. din |-s%" —+} rom A0-A9 EI) iKxs ee al Q6) Using DFF design a binary cell, which can perform read/write operations based on enable, r/w ? Also provide memory enable, mem_en? Q7) Give the basic circuit for DRAM? Q8) Draw the circuit for SRAM? Q9) Define memory access time? QU0) Which is faster: SRAM or DRAM? QI1) What are the advantages and disadvantages of DRAM when compared to SRAM? Q12) Explain read-refresh operation in case of DRAM? Q13) Using the binary cell as block box, two-dimensional decoding structure of a memory block is shown below: Srikanth Alaparthi 107Ar Ao 14 S: So 2:4 decoder Do Di Dz D,| 7 Dg} f_s}s,. 2 2D, <_4ls,3 3 De Ds (a) What is the size of the memory? (b) What is address of the basic cell at location: Row3, Column3? (c) Which cell will get selected for the address: C (in hex) ? Q14) What is dual data ROM? QUS) Expand the following: (a) PLD (b) PLA (c) PAL (d) FPGA QU6) What is the difference between PLA and PAL? Q17) Match the following: (a)PROM (i) Programmable AND Array and programmable OR array (b) PAL (ii) Fixed AND array and programmable OR array (©) PLA (ii) Programmable AND Acray and fixed OR array Q18) Implement the following boolean functions using PLA: F1=A’BC + ABC +B’C’ F2=A’BC + ABC F3=B'C” 19) What is FIFO? Explain the significance? 20) Show the basic block diagram of FIFO and explain the basic signals or connections ofa FIFO? Q21) Itis required to connect a Master, which generates data @ 200 Mega Samples/sec to a Slave which can receive the data @ 10 Mega Samples/Sec. If the data lasts in 10Micro Sec, what is the optimal size of FIFO to be used to avoid loose of data? Srikanth Alaparthi 10822) In a particular system, the sender sends data at the rate of 80 words / 100 clocks and the receiver can consume at the rate of § words / 10 clocks. Calculate the depth of FIFO so that no data is dropped under following assumptions: > There is no feedback or handshake mechanism. ® Occurrence of data in that time period is guaranteed but exact place in those clock cycles is indeterminate. 23) How deep does the FIFO need to be to prevent under flowing or overflowing? Given Rules: i) Ais input data and B is output data ii) frequency(clk_A) = frequency(clk_B)/ 4 iii) period(en_B) = period(clk_A)* 100 iv) duty_cycle(en_B) = 25% al wr FF on wal kok 6 Q24) What is the difference between Synchronous and Asynchronous FIFOs? Answer Al) Any type of memory that requires power in order to store information is called volatile memory. RAM is volatile whereas ROM is non-volatile. That means ROM can, store data without power also. A2) Differences between RAM and ROM: 1, ROM: Read Only Memory. RAM : Random Access Memory 2. ROM has no write operation. RAM has both read and write operations 3. ROMS are non-volatile and RAMS are volatile, 310 A3) IK =2'°, Number of address lines = 10 Number of data lines = 8 Ad) 256/16 = 16, 16X8 memories are sufficient to get a memory of size 256 X 8. But to get 256 X 16, we need twice of that. So, the required number of 16 X'$ memories = 16 * 2 AS) We need 8, IKX8 memories. For SKX8 memory has 13 address ( A12-A0) lines. For each 1KX8 memory, there will 10 address lines. So we can connect the A0-A9 address lines directly to these 10 address lines. And the remaining, that is from A10,A11,A12 can be used as select lines for the decoder and the decoders outputs will be connected to “es” of the ROMs, The complete design is shown below. Srikanth Alaparthi 109Ee eee Do a now a» [> Test ene Ai ——¥ So p-| __*,frow] a Ay Ds} ow b, That [Sane aS t—_ 2 WOM LS dot Ds tke De 6 row kx FHP Dy 3 Tow >} Teas [=D now Lf 0M] 5s The corresponding address map is shown in the following table: ‘Address range in hex ROM that will be selected (0000 — 03FF ROML (0400 — O7FF ROM (0800 — OBFF ROMS OCFF — OFFF ROM4 1000 — 13FF ROMS 1400 — 17FF ROMG 1800 — 1BFF ROM7 1CFF — 1FFF ROMS A6) Mem En rhw Operation 0 x Output = 0 1 0 Write 1 1 Read Using the truth table shown in above table, the following equations can be derived: Din = IN AND Mem_En AND (r/w_ )° and OUT =QAND Mem En AND (1/v ) Srikanth Alaparthi 110Mem_En wo A7) One-transistor Dynamic RAM cell is as follows: word line The cireuit shows the access transistor, NMOS transistor and the storage capacitance (typically 30-50 F). Logic-1 at word line makes the MOS transistor conductive. Then the bit line capacitance (nearly 30 times more than Cs) comes in parallel with the Cs. This allows the charge sharing between the two capacitors. (A filled capacitor equals to a logical one while an "empty" capacitor equals to a logical zero.) A8) A single SRAM memory cell is shown in the below diagram. As can be noted, six total transistors are required for our design. Two NMOS and two PMOS transistors are used to construct a simple latch to store the data, plus two more pass NMOS transistors are controlled by Word Line to pass Bit Line and Bit Line Bar into the cell. Write and Read operations are performed by executing a sequence of actions that are controlled by the outside circuit. Write Operation: A Write operation is performed by first charging the Bit Line and Bit Line Bar with values that are desired to be stored in the memory cell. Setting the Word Line high performs the actual write operation, and the new data is latched into the circuit. Read Operation: A Read operation is initiated by pre-charging both Bit Line and Bit Line Bar to logic 1. Word Line is set high to close NMOS pass transistors to put the contents stored in the cell on the Bit Line and Bit Line Bar. Srikanth Alaparthi M1