ICN6202 Specification V0.

ICN6202 Specification
MIPI® DSI BRIDGE TO FLATLINKTM LVDS

Revision 0.8

NOTICE NOTICENOTICENOTICENOTICE

This design and all of its related documentation constitutes valuable and confidential
property of Chipone Technology (Beijing) Co., Ltd. It is licensed for use as expressly
stated in the written license Agreement between Chipone Technology (Beijing) Co.,
Ltd and its customers. Any other use or redistribution of this design and all related
documentation is expressly prohibited.

This design and all related documentation have been released by Chipone Technology
(Beijing) Co., Ltd to its customers under a Non Disclosure Agreement (NDA).
Disclosure of this design outside of this agreement is expressly prohibited.

NOTICE NOTICENOTICENOTICENOTICE

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 ICN6202 Specification V0.8

Revision History

Rev Date Author Description

0.1 2013-04-03 Simon_Liu Initial version

0.2 2013-04-12 Simon_Liu 1. add DC and AC characteristic, section 7
2. add MIPI Rx functions, section 6.1
0.3 2013-05-20 Simon_Liu 1. add section 6.4 & 6.5
0.4 2013-06-20 Simon_Liu 1. add diagram QFN40 and pin description.
0.5 2013-07-09 Simon_Liu Only use QFN48 package
0.6 2013-07-09 Simon_Liu Add QFN40 again

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 ICN6202 Specification V0.8

Table of Contents
1 Introduction ................................................................................................................ - 5 -
1.1 Feature List ............................................................................................................................................ - 5 -

2 Functional Block Diagram ........................................................................................ - 6 -

3 System Application Diagram .................................................................................... - 7 -
4 Pin Diagram ................................................................................................................ - 8 -
5 Pin Description ........................................................................................................... - 9 -
6 Function Description ................................................................................................ - 11 -
6.1 MIPI Receiver...................................................................................................................................... - 11 -
6.1.1 DSI Lane Merging ................................................................................................................................. - 11 -
6.1.2 DSI Pixel Stream Packets ...................................................................................................................... - 11 -
6.1.3 DSI Video Transmission sequence ........................................................................................................ - 13 -
6.2 LVDS Transmitter .............................................................................................................................. - 14 -
6.3 Bist mode .............................................................................................................................................. - 15 -
6.4 DSI access local registers .................................................................................................................... - 15 -
6.4.1 Write local registers .............................................................................................................................. - 15 -
6.4.2 Read local registers ............................................................................................................................... - 16 -
6.5 I2C access local registers .................................................................................................................... - 16 -

7 DC and AC Electrical Characteristics ................................................................... - 17 -

7.1 ABSOLUTE MAXIMUM RATING .................................................................................................. - 17 -
7.2 RECOMMENDED OPERATING CONDITIONS .......................................................................... - 17 -
7.3 Electrical Characteristics.................................................................................................................... - 18 -
7.3.1 MIPI DSI INTERFACE ........................................................................................................................ - 18 -
7.3.2 LVDS output ......................................................................................................................................... - 19 -
7.4 SWITCHING CHARACTERISTICS ............................................................................................... - 20 -

8 Package information ................................................................................................ - 22 -

8.1 QFN40 package ................................................................................................................................... - 22 -

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Table of figures
Figure 2-1 ICN6202 function block diagram ..................................................................................................... - 6 -
Figure 3-1 ICN6202 system application diagram ............................................................................................... - 7 -
Figure 4-1 ICN6202 QFN40 pin diagram (Top View) ....................................................................................... - 8 -
Figure 6-1 DSI multi-lanes HS Transmission Example ................................................................................... - 11 -
Figure 6-2 DSI RGB666 Color format, Loosely Long Packet ......................................................................... - 12 -
Figure 6-3 DSI RGB666 Color format, Tightly Long Packet .......................................................................... - 12 -
Figure 6-4 DSI RGB888 Color format, Long Packet ....................................................................................... - 12 -
Figure 6-5 Non-Burst Mode with Sync Pulses ................................................................................................. - 13 -
Figure 6-6 Non-Burst Mode with Sync Events ................................................................................................ - 13 -
Figure 6-7 Burst mode ...................................................................................................................................... - 14 -
Figure 6-8 LVDS, 18-bit single port, VESA or JEITA format ......................................................................... - 14 -
Figure 6-9 LVDS, 24-bit single port, VESA format......................................................................................... - 14 -
Figure 6-10 24-bit single port, JEIDA format .................................................................................................. - 15 -
Figure 6-11 Bist mode pattern sequence .......................................................................................................... - 15 -
Figure 7-1 DSI HS UI timing definition ........................................................................................................... - 18 -
Figure 7-2 DSI HS/LP signaling and Contention Voltage................................................................................ - 19 -
Figure 7-3 LVDS output signaling ................................................................................................................... - 19 -
Figure 7-4 LVDS output data and clock timing ............................................................................................... - 21 -
Figure 7-5 Power on and RESET and ULPS timing ........................................................................................ - 21 -
Figure 8-1 QFN40 pin dimension ..................................................................................................................... - 22 -

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 ICN6202 Specification V0.8

1 Introduction
ICN6201 is a bridge chip which receives MIPI® DSI inputs and sends LVDS outputs.
ICN6202

MIPI® DSI supports up to 4 lanes and each lane operates at 1Gbps maximum; the totally maximum input
bandwidth is 4Gbps; and the MIPI defined ULPS(ultra-low-power state) is also supported. ICN6202 decodes
MIPI® DSI 18bepp RGB666 and 24bpp RGB888 packets.

The LVDS output 18 or 24 bits pixel with 25MHz to 154MHz, by VESA or JEIDA format.

ICN6202 support video resolution up to FHD (1920x1080) and WUXGA(1920x1200).

ICN6202 adopts QFN40 .

1.1 Feature List

 Supports MIPI® D-PHY Version 1.00.00 and MIPI® DSI Version 1.02.00.

 Single Channel DSI Receiver with One, Two, Three and Four lanes configurable, each lanes operates up to
1Gbps.

 Receives 18bpp RGB666 and 24bpp RGB888 packets defined by DSI.

 Supports MIPI Low State, Ultra-Low Power State, Shut Down mode.

 Single Channel LVDS with output clock range of 25MHz to 154MHz.

 LVDS can be generated from MIPI HS clock or external reference clock.

 Support LVDS clock with center spreading up to 2%, modulation 30KHz ~ 60KHz.

 LVDS output with VESA or JEIDA format.

 LVDS output pin order can be swapped flexible.

 supply voltage: 1.8V.

 provide I2C slave interface.

 package: QFN40-pins with e-pad.

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2 Functional Block Diagram

Following figure shows a functional block diagram of the ICN6202.

A_Y0P/N
LANE0
DA0P/N LP_TX
LP_RX A_Y1P/N
HS_RX

DA1P/N LANE1 LANE VIDEO LVDS LVDS TX A_Y2P/N

same as lane0 MERGE RECOVER PACKAGE PHY

A_Y3P/N
DA2P/N LANE2
same as lane0

A_CLKP/N
DA3P/N LANE3
same as lane0

DACP/N LANE_CLK
LP_RX
I2C SCL/SDA
HS_RX PLL
CONFIG

REFCLK

Figure 2-1 ICN6202` function block diagram

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3 System Application Diagram

In the diagram below shows the ICN6202’s system application.

mipi_lane0 lvds_lane0 Source

mipi_lane1 lvds_lane1 driver
Application mipi_lane2 ＩＣＮ６２０２ lvds_lane2
TCON PANEL
Processor mipi_lane3 lvds_lane3 Gate
mipi_clk lvds_clk
driver

Figure 3-1 ICN6202 system application diagram

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4 Pin Diagram

VDD18_PLL
REFCLK2
A_CLKP
A_CLKN
A_Y1P
A_Y1N
A_Y2P
A_Y2N

A_Y3P
A_Y3N
30 29 28 27 26 25 24 23 22 21
A_Y0N 31 20 DA3N
A_Y0P 32 19 DA3P
VSS_LVDS 33 18 DA2N
VDD18_LVDS 34 17 DA2P
VCORE 35 16 DACN
CHIPONE
VDD18 36 15 DACP
ICN6202 QFN40
GND 37 14 DA1N
TEST_EN 38 13 DA1P
BIST_EN 39 12 DA0N
GPIO_0 40 11 DA0P
1 2 3 4 5 6 7 8 9 10
GPIO_1
ADDR_SEL
GND
IRQ
SCL
SDA
ATEST
EN
VDD18_RX
VSS_RX

Figure 4-1 ICN6202 QFN40 pin diagram (Top View)

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5 Pin Description
Name QFN-40 I/O Description

MIPI interface

DA0P/DA0N 14/15 11/12 Input MIPI® D-PHY, data LANE0.

DA1P/DA1N 16/17 13/14 Input MIPI® D-PHY, data LANE1.

DA2P/DA2N 20/21 17/18 Input MIPI® D-PHY, data LANE2.

DA3P/DA3N 22/23 19/20 Input MIPI® D-PHY, data LANE3.

DACP/DACN 18/19 15/16 Input MIPI® D-PHY, clock LANE.

LVDS interface

A_Y0P/A_Y0N 36/35 32/31 Output LVDS data lane0

A_Y1P/A_Y1N 34/33 30/29 Output LVDS data lane1

A_Y2P/A_Y2N 32/31 28/27 Output LVDS data lane2

A_Y3P/A_Y3N 28/27 24/23 Output LVDS data lane3

A_CLKP/A_CLKN 30/29 26/25 Output LVDS clock lane

MISC

EN 8 8 input When EN is low, this chip is reset.

ADDR_SEL 1 2 input Local I2c address select.

REFCLK1 11 -- input Optional reference clock for LVDS output clock.

REFCLK2 26 22 input Optional reference clock for LVDS output clock.

SCL 5 5 input Local I2C bus

SDA 6 6 inout Local I2C bus

IRQ 4 4 output Interrupt signal

TEST_EN 44 38 input For ATE test, when work, connect to GND.

BIST_EN 45 39 input For ATE test, when work, connect to GND.

GPIO_0 47 40 inout Reserved.

GPIO_1 48 1 inout Reserved.

Power/Ground

GND 3, 10, 3, 10, Ground

25, 39, 33,37

43, 46

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VDD18 9, 24, 9, 21, 1.8V input
40, 42 34, 36

VCORE 41 35 Output from voltage regulator for digital core.

Other

NC 2, 12, -- Not used pins, left unconnected

13, 37,
38

NOTE:

1. The use of four ceramic capacitors(2 x 1uF and 2 x 0.01uF) with pin VCORE provides good performance.
At least, one 1uF and one 0.01uF capacitor is necessary. Also, the trace between the decoupling capacitor
and pin should minimized.

2. Any one of REFCLK1 and REFCLK2 can be used as the reference clock for LVDS output. If one or two
is not used, the unused pin should connect to GND. For QFN40 package, only REFCLK2 is available.

3. TEST_EN & BIST_EN should be connected to GND when normal working.

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6 Function Description

6.1 MIPI Receiver

6.1.1 DSI Lane Merging

ICN6202 support four DSI data lanes, and may be configured to one, two or three DSI data lanes. Unused DSI
input lanes should be left unconnected or driven to LP11 state.

Following figure illustrates the lane merging function for 4-lane, 3-lane, 2-lane and 1-lane separately.

Figure 6-1 DSI multi-lanes HS Transmission Example

6.1.2 DSI Pixel Stream Packets

ICN6202 receives and interpret 18bpp(RGB666) , 24bpp(RGB888) DSI packets and translates to video stream.

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Figure 6-2 DSI RGB666 Color format, Loosely Long Packet

Figure 6-3 DSI RGB666 Color format, Tightly Long Packet

For the RGB666 tightly packet, the total line width(displayed plus non-displayed pixels) should be a multiple of
four pixels(nine bytes).

Figure 6-4 DSI RGB888 Color format, Long Packet

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6.1.3 DSI Video Transmission sequence

ICN6202 supports Non-Burst Mode with Sync Pulses, Non-Burst Mode with Sync Events and Burst mode.

 Non-Burst Mode with Sync Pulses: enables the peripheral to accurately reconstruct original video timing,
including sync pulse widths.

 Non-Burst Mode with Sync Events: similar to above, but accurate reconstruction of sync pulse widths is not
required, so a single Sync Event is substituted.

 Burst mode: RGB pixel packets are time-compressed, leaving more time during a scan line for LP
mode(saving power).

For all three sequences, the first line of a video frame shall start with a VSS packet, and all other lines start with
VSE or HSS. The position of the synchronization packets in time is of utmost importance since this has a direct
impact on the visual performance of the display panel; that is, the LVDS output video timing(HS-Horizontal
sync and VS-Vertical sync) are generated based on the synchronization.

Figure 6-5 Non-Burst Mode with Sync Pulses

Figure 6-6 Non-Burst Mode with Sync Events

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 ICN6202 Specification V0.8

Figure 6-7 Burst mode

6.2 LVDS Transmitter

ICN6202 supports both Jeida/VESA 6/8bits data format. Each format is as below diagram.

Figure 6-8 LVDS, 18-bit single port, VESA or JEITA format

Figure 6-9 LVDS, 24-bit single port, VESA format

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 ICN6202 Specification V0.8

Figure 6-10 24-bit single port, JEIDA format

6.3 Bist mode

ICN6202 goes into bist mode when configure register is enabled, five built-in images as below are displayed
sequentially; and the interval time can be set (default is about 2ms).

Pattern1: White Pattern2: Black

Pattern5: Blue Pattern4: Green Pattern3: Red

Figure 6-11 Bist mode pattern sequence

6.4 DSI access local registers

6.4.1 Write local registers

There are two methods to write local registers.

These two method must be used under ESCAPE mode.

 Use Generic Short WRITE with 2 parameters( DI = 0x23)

The format is as below:

DI(0x23) + offset[7:0] + data + ECC.

Please note that the offset is only 8bits.

Also, this method can write only one data in each packet.

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 ICN6202 Specification V0.8
 Use Generic Long Write( DI = 0x29)

The format is as below:

DI(0x29) + WC[7:0] + WC[15:8] + ECC + offset[7:0] + data(1) + data(2) + …… + data(n) + CHKSUM[7:0] +

CHKSUM[15:8].

where: n = WC[15:0] – 1..

In this case, the data length can be 65535 maximum.

6.4.2 Read local registers

Use Generic READ with 2 parameters(0x24), this method can be used under HS mode or ESCAPE MODE.

The format is as below:

DI(0x24) + offset[7:0] + length[7:0] + ECC.

Please note that the offset is only 8bits.

The read length can be 255 maximum.

6.5 I2C access local registers

ICN6202` support standard I2C protocol with speed up to 400K.

The chip device address is determined by the pin “ADDR” as below table:

BIT7(MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0(W/R)

0 1 0 1 1 0 ADDR 0/1

When ADDR = 1, device address is 0x5A(Write) and 0x5B(Read);

When ADDR = 0, device address is 0x58(Write) and 0x59(Read).

following example is operation procedure with ADDR = 0.

 Write one byte to certain offset

ST  0x58  ACK  OFFSET  ACK  DATA  ACK  STOP.

 Write more bytes to successive address.

ST  0x58  ACK  OFFSET  ACK  DATA0  ACK  DATA1  ……  DATAn  ACK 

STOP.

 Read data from certain offset.

ST  0x58  ACK  OFFSET  ACK  RESTART  0X59  ACK  DATA0  ACK  DATA1
 ……  DATAn  NACK  STOP.

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7 DC and AC Electrical Characteristics

7.1 ABSOLUTE MAXIMUM RATING

MIN MAX UNIT

Supply Voltage Range VCC -0.3 2.175 V

Input Voltage Range CMOS Input -0.5 2.175 V

DSI input -0.4 1.4 V

Storage Temperature Ts -65 105 ℃

Electrostatic discharge Human Body Model ±2 KV

Charged-device model ±500 V

Note: Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.

7.2 RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

VCC VCC power supply 1.65 1.8 1.95 V

VPSN Supply noise on any VCC pin f(noise) >

0.05 V
1MHz

TA Operating free-air temperature -40 85 ℃

TCASE Case temperature 92.2 ℃

VDSI_PIN DSI input pin voltage range -50 1350 mV

f(I2C) Local I2C input frequency 400 KHz

fHS_CLK DSI HS clock input frequency 40 500 MHz

tsetup DSI HS data to clock setup time(Figure 7-1) 0.15 UI

thold DSI HS data to clock hold time(Figure 7-1) 0.15 UI

ZL LVDS output differential impedance 90 132 Ω

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 ICN6202 Specification V0.8

Figure 7-1 DSI HS UI timing definition

7.3 Electrical Characteristics

7.3.1 MIPI DSI INTERFACE

Refer to Figure 7-2.

parameter Description MIN TYP MAX UNIT

VIL Low Power logic 1 input voltage 880 mV

VIH Low Power logic 0 input voltage 550 mV

|VID| HS differential input voltage: |Vdp – Vdn| 70 200 270 mV

|VIDT| HS differential input voltage threshold 50 mV

VIL-ULPS Low Power receiver logic 0 voltage, ULP

300 mV
state

VCMRX(DC) Common-mode voltage HS receive mode 70 330 mV

△VCMRX(HF) HS common-mode interference 100 mV

VIHHS HS single-ended input high voltage 460 mV

VILHS HS single-ended input low voltage -40 mV

VTERM-EN Single-ended threshold for HS termination

450 mV
enable

ZID Differential input impedance 80 100 124 Ω

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Figure 7-2 DSI HS/LP signaling and Contention Voltage

7.3.2 LVDS output

Refer to Figure 7-3.

parameter Description MIN TYP MAX UNIT

|VOD| Steady-state differential output voltage 140 500 mV

△|VOD| Change in steady-state differential output 35 mV

voltage between opposite bnary state

VOC(SS) .Steady state common-mode output voltage 0.8 0.9 1.0 V

1.15 1.25 1.35 V

VOC(PP) Peak-to-Peak common-mode output voltage 35 mV

RLVDS_DIS Pull-down resistance for disabled LVDS 1 KΩ

outputs

Figure 7-3 LVDS output signaling

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7.4 SWITCHING CHARACTERISTICS

Parameter Description MIN TYP MAX UNIT

DSI

tGS DSI LP input pulse rejection 300 ps

LVDS (refer to Figure 7-4)

tC Output clock period 6.49 40 ns

tW High-Level output clock pulse duration 4/7 tC ns

t0 Delay time, CLK↑ to 1st serial bit position -0.15 +0.15 ns

t1 Delay time, CLK↑ to 2nd serial bit position 1/7 tC – 0.15 1/7 tC + 0.15 ns

t2 Delay time, CLK↑ to 3rd serial bit position 2/7 tC – 0.15 2/7 tC + 0.15 ns

t3 Delay time, CLK↑ to 4th serial bit position 3/7 tC – 0.15 3/7 tC + 0.15 ns

t4 Delay time, CLK↑ to 5th serial bit position 4/7 tC – 0.15 4/7 tC + 0.15 ns

t5 Delay time, CLK↑ to 6th serial bit position 5/7 tC – 0.15 5/7 tC + 0.15 ns

t6 Delay time, CLK↑ to 7th serial bit position 6/7 tC – 0.15 6/7 tC + 0.15 ns

tr Differential output rise-time 180 500 ps

tf Differential output fall-time 180 500 ps

REFCLK

FREFCLK REFCLK Frequency 25 154 MHz

tr, tf REFCLK rise and fall time 0.1 1 ns

tpj REFCLK peak-to-peak phase jitter 50 ps

Duty REFCLK duty cycle 40% 50% 60%

EN, ULPS, RESET (refer to Figure 7-5)

ten Enable time from EN or ULPS 1 ms

tdis Disable time to standby 0.1 ms

treset Reset time 10 ms

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Figure 7-4 LVDS output data and clock timing

Figure 7-5 Power on and RESET and ULPS timing

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8 Package information

8.1 QFN40 package

Figure 8-1 QFN40 pin dimension

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