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Verification of KCL and KVL

This document describes an experiment to verify Kirchoff's Current Law (KCL) and Kirchoff's Voltage Law (KVL) in DC circuits. The experiment involves setting up simple circuits using a regulated power supply, resistors, ammeters and voltmeters. Measurements are taken at different voltages and recorded in tables. KCL is verified if the total current entering a junction equals the total current leaving. KVL is verified if the sum of the potential differences in a closed loop equals zero. The results show the theoretical and measured current and voltage values match, demonstrating KCL and KVL are verified experimentally.

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0% found this document useful (0 votes)
398 views3 pages

Verification of KCL and KVL

This document describes an experiment to verify Kirchoff's Current Law (KCL) and Kirchoff's Voltage Law (KVL) in DC circuits. The experiment involves setting up simple circuits using a regulated power supply, resistors, ammeters and voltmeters. Measurements are taken at different voltages and recorded in tables. KCL is verified if the total current entering a junction equals the total current leaving. KVL is verified if the sum of the potential differences in a closed loop equals zero. The results show the theoretical and measured current and voltage values match, demonstrating KCL and KVL are verified experimentally.

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© © All Rights Reserved
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Experiment No.

-1 Date:

VERIFICATION OF KVL AND KCL


FOR DC CIRCUITS

Aim:

To verify Kirchoff’s Current Law (KCL) and Kirchoff’s Voltage Law (KVL).

Apparatus required:

Sl.No. Name of the apparatus Type Range Quantity


1. Regulated power supply unit DC (0-30)V, 2A 1Nos.
2. Ammeter MC (0-2)A 3Nos.
3. Voltmeter MC (0-30)V 3Nos.
4. Rheostat Wire Wound 50Ω/2A, 1No.each
100Ω/2A,
150Ω/2A
5. Connecting wires/ Patch cards - - As many
required

Theory:

KCL: Kirchoff’s current law states that in any electrical circuit, the amount of current
entering the junction is equal to the sum of the currents moving out of it.

KVL: Kirchoff’s voltage law states that, the sum of the potential drops across the various
elements in a closed loop of any electrical circuit is zero.

Circuit Diagram:

VERIFICATION OF KCL
VERIFICATION OF KVL

Tabular Column:

KCL:

Sl. RPS I1 (A) I2 (A) I3 (A) I1= I2+ I3(A)


No Voltag Calculated Measured Calculated Measure Calculated Measure Calculated Measured
. e (V) d d
1 10
2 15
3 20
4 25
5 30

Verification: I1= I2 + I3, if satisfied, KCL is verified.

KVL:

Sl. RPS V1 (V) V2(V) V3(V) V= V1 + V2 + V3 (V)


No Voltag
. e (V) Calculated Measured Calculated Measure Calculated Measure Calculated Measured
d d
1 10
2 15
3 20
4 25
5 30

Verification: V= V1 + V2 + V3, if satisfied, KVL is verified.

Sample Calculations:
Procedure (Common to Verification both KVL and KCL):

● Make the connections as given in the circuit diagram of KCL verification.

● Initially keep the voltage control knob in the minimum position and current knob in
the maximum position.

● Switch ON the power supply. Increase the voltage in uniform steps such as to cover
wide range as possible in the meters.

● Note down meter readings in the tabular column.

● Repeat the same for different voltages by varying power supply.

● Repeat the same procedure by considering KVL verification circuit.

● Keep voltage control knob to minimum and switch off the power supply and remove
the connections.

● Verify the practical readings with theoretical values.

Result:

The theoretical and practical values of current are nearly same. Thus KCL is verified.

The theoretical and practical values of voltage are nearly same. Thus KVL is verified.

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