2

Circuit Building Blocks

2.1 !ntroduction

In this chapter we shall examine a variety of useful transistor circuits and

circuit configurations. First we consider means of boosting the gain of a
circuit by employing pairs of transistors coupled together. This type of
arrangement is called a Darlington or "super-alpha" pair.

2.2 Darlington and complementary Darlington connections

The basic idea is to take two transistors and to connect them in a special
way to produce a three-terminal composite device of much larger current
gain. If npn and pnp transistors can be used, there are four possible circuit
arrangements with this property (Figure 2.1). Of the circuits shown, (a) and
(b) are called "Darlington pairs", and (c) and (d) are called "complementary
Darlingtons" as they use complementary transistors. It is easy to see which
terminal must be the emitter of the composite transistor in each case - it
must be the one passing the most current, since 1" :16 * 1". Careful inspection
of the circuits also reveals that the composite transistor is in all four cases
of similar type (npn or pnp) to the first of its two transistors: thus (a) and
(d) are npn, while (b) and (c) are pnp. A simple calculation shows that for
a Darlington pair of type (a) or (b):

§ : frr+ §z(frr+ 1): §r§r+ 0r+ frr* fr t§z (2.r)

31
32 Electronics, Noise and Signal Recovery

(c) (d)

Fig. 2.1 Darlington and complementary Darlington circuits. Here (a) and (b) are
Darlington pairs, and (c) and (d) are complementary Darlingtons. Note that in all
cases the single equivalent transistor is of the same type (npn or pnp) as the
first
transistor of the pair.

while for a complementary Darlington:

§ : 0 r(§ r+ 1) : 0 r§r* fr t N 0 t§ z (2.2)

circuit (c) is highly useful on some integrated circuits, where it is

straightforward to fabricate low-gain pnp transistor but difficult to fabricate
a
a high-gain one directly. However, in many applications such as hi-fi, a
matched pair of high-gain npn and pnp transistors is required. For this
purpose circuits (a) and (c) are often used together.

2.3 White em¡tter follower

Next we consider the white emitter follower (Figure 2.2). This circuit is
useful when feeding a low-impedance load and a fast response is needed for
positive andnegative-going waveforms. The lower transistor operates between
the output connection and the ground, and is capable of pulling the output
voltage down rapidly. The upper transistor operates between the output
connection and the upper voltage rail, and is capable of pulling the output
voltage up rapidly. This second transistor acts as an emitter follower circuit,
while the lower transistor acts as a normal common emitter amplifier.
However, a complication arises since the lower transistor inverts the input
signal: to overcome this problem, the lower transistor is fed from the collector
of the upper transistor. Various capacitors and resistors are also required in
order to ensure that both transistors operate under appropriate conditions.
To avoid some of these complications, an alternative version of the circuit
was devised, using a complementary pair of transistors (Figure 2.3). Notice
Circuit Building Blocks 33

Fig.2.2 White emitter follower.

that in reality this is an emitter follower constructed using a slightly modified

complementary Darlington. Unfortunately, the significantly lower com-
plexity of the circuit also reflects the fact that it only reacts rapidly when
pulling the output voltage up, unlike the original White emitter follower.
The complementary emitter follower aims to overcome this shortcoming and
is described next.

Fig. 2.3 Modified White emitter follower. This circuit is a White emitter follower
modified so as to cut down the number of coupling capacitors and bias resistors.
However, closer scrutiny shows that it can also be regarded as an emitter follower
constructed using a slightly modiflred complementary Darlington.
34 Electronics, Noise and Signal Recovery

2.4 Complementary em¡tter follower

In many applications such as audio amplification, "push-pull" power output

stages are needed, and for this purpose the White emitter follower is
inadequate since it is not symmetric: note, for example, that the upper and
lower output connections have different intrinsic output impedances and
speeds of operation. In particular what is needed is a symmetric circuit which
produces no so-called "crossover distortion" - i.e. one with a perfectly
symmetric linear voltage transfer function. The complementary emitter
follower circuit (Figure 2.4) is symmetric and therefore there should be no
even harmonic distortions in the output waveform. However, there is a range
of input voltages -2Vo" @1.2V) over which both transistors are non-
conducting. To understand this, note that when there is no a.c. input voltage,
the base and emitter voltages are all, by symmetry, equal to V""f2, and both
transistors are therefore cut off. The upper transistor only starts conducting
when the a.c. input voltage pulls its base up by an amount Zo" (=0.6V),
and the inverse situation applies for the lower transistor. In fact, this picture
does not take account of the fact that the switch-on of each transistor is a
gradual function of input voltage. Thus the true combined voltage transfer
function may be depicted as in Figure 2.5(a). To tackle this problem special
bias circuitry can be included (Figure 2.6), and this has the effect of sliding
the component voltage transfer curves in Figure 2.5 relative to each other,
until their sum gives a good approximation to linearity (see Figure 2.5(b)).
In the circuit of Figure 2.6,linearity has been improved further by including

Fig.2.4 Complementary emitter follower. This is an a.c. emitter follower circuit,

using a complementary pair of transistors joined symmetrically to give a "push-pull"
power output stage.
Circuit Building Blocks 35

Fig. 2.5 Elimination of crossover distortion. (a) The voltage transfer characteristic
for the circuit of Figure 2.4.The crossover distortion near the origin can largely be
eliminated by sliding the characteristics for the individual transistors relative to one
another, until their sum approximates closely to a straight line through the origin,
as in (b). This is achieved using the modified bias circuit of Figure 2.6.

cc

Fig.2.6 Modilied bias circuit for eliminating crossover distortion. Notice the small
resistors in series with the emitters of the two transistors. These give extra linearity
and thus help to eliminate crossover distortion.

a small "linearizing resistor" - typically in the range 1-3 O - in series with

each emitter.
Unfortunately, the general arrangement of Figure 2.6 is not satisfactory
since a resistive circuit can only cancel the 2Vo" offset accurately at a single
temperature. Two diodes can be used in place of the resistive network, but
it is more common to employ & "Vb" multiplier" circuit, which can be used
36 Electronics, Noise and Signal Recovery

Fig.2.7 More satisfactory bias circuit for the complementary emitter follower. In
this case the bias circuit uses a Zo" multiplier, as shown in more detail in Figure 2.8.

to cancel any multiple of vo". The vo. multiplier will be described in detail
below. Meanwhile, the complete circuit for a practical complementary emitter
follower is shown in Figure 2.7 . rn chapter 5 we shall see how a complete
audio amplifier can be built with this type of output circuit.

2.5 Vo" multiplier

This is a cunning circuit (Figure 2.8) with the property that the voltage z.
across it is a constant times the transistor Zo" on-voltage (-6.6V). The
circuit adjusts itself, by a negative feedback process, so that V"x Rrl(Rr+ Rz)

4l
Fig.2.8 Zo"multiplier.
Circuit Building Blocks 37

is just equal to Zo". Thus

n:(T)n" (2.3)

The reason for the name "I/0" multiplier" is now obvious. The circuit has
two notable features:
l. V.may readily be adjusted to any convenient value by means of a single
presettable potentiometer.
2. The temperature dependence of. Y. is identical to that of the Vo" of any
transistor. For these reasons the circuit is ideal for cancelling out the
Zo" voltages of other transistors, as in the circuit of Figure 2.7.

An important factor in the use of the above circuit is its dynamic resistance
p. This may be calculated by assuming that there is an a.c. voltage uo across
the circuit, deducing the current through R, and io, and then calculating i"
and the total a.c. current io. Thus we lind:

RrR, +hi"(Rl *Rr) Rr(V.lVo"- l)+ hr"(V,lvo")

(2.4\
'u-- h,.+ffi+1)R2 hnlRr+(B+1)

where we have eliminated R, using equation (2.3). For any given %, this
expression is clearly minimized by reducing R, as far as possible. However,
below a certain point, most of the current would be flowing through the
resistor chain, and on the contrary, we require the circuit to act as a chain
of diodes: thus most of the current must come from the collector. For this
to be so, R, must obey the condition:

Rr>>h,"1(p + 1) (2.s)

while at the same time we require:

hr.>> Rr, (2.6)

so that equation (2.3) is accurate and the factor in brackets is independent

of temperature.
Once R, has been decided, and V. has been specified, p is completely
determined by equation Q.$. Indeed, if we take R, to have the value
ch"l(§+ 1), where lr.rrrfr, we finally obtain:

p : l(V.l Vo" - t)c I $ + l) + (V,l Vb")fh,.c I @ + 1 XÉ + I)

x(Y.lVo")h"l(§+r) (2.7)
38 Electronics, Noise and Signal Recovery

Thus p has the value h"l$+l) for Yo:Vo", and increases approximately
linearly with increase of %. In fact, the a.c. voltage drop remains about the
same proportion of the d.c. voltage drop as Zo increases - a quite reasonable
result. It is of interest that equation (2.7) predicts values for p of 20,40,60
and 80Q at V":3,6,9 and 12V respectively for a BC107 at I.:25mA:
these values of p contrast with dynamic resistances 120, 27,25 and 35 o for
a typical series of Zener diodes with the same nominal voltages. Evidently,
the vo" multiplier is of value mainly for producing relatively small voltage
drops - especially when these are not integral multiples of 0.6 v. However,
to obtain a voltage drop of 1.2Y, for a circuit such as that of Figure 2.7,
R, and R, would typically both be - 70 Q, and p would be about 8 e.
Before leaving this section, note that the predictions of p are based on the
simplified model expressed by equations (2.5) and (2.6). However, the
important point is that the design can be optimized: furthermore, there is a
tradeoff in the design between dynamic resistance p (which should be low)
and temperature dependence (which should be close to that of a diode).
clearly, there is more subtlety in this simple circuit than there first appears
to be!

2.6 Diode-connected transistor

we next consider the diode-connected transistor shown in Figure 2.9.lnfact

this is a special case of the Vo" multiplier discussed above, with Rr:0 and
Rr:oo. Clearly, it has an output voltage equal to Vo", and in addition its
I-v characteristic must be a (P+ l)-amplified version of the emitter-base
diode characteristic. Applyingthe vo"multiplier formula for p (equation2.4)

Fig. 2.9 Diode-connected transistor.

Circuit Building Blocks 39

in the specific case, we obtain the exact result:

p:h,"1(B + l) (2.8)

which gives 4O for a BC107 at I":25mA.

2.7 Bootstrapped em¡tter follower

Itis the main purpose of an emitter follower circuit to act as a high-impedance

buffer between two other circuits. Unfortunately, many emitter followers are
unable to realize their potential in this respect, since the d.c. bias resistors
used to stabilize the operation of the emitter follower themselves conduct
substantial current, thereby constituting a significant load across the previous
circuit (see also Section 1.7).
This effect can be cut down substantially by a clever trick. The output
voltage variation is fed back to cancel the a.c. change in the bias voltage,
thereby nearly eliminating the input a.c. current passing through the bias
resistors. The complete circuit is shown in Figure 2.l0.lf the output voltage
is uo, the voltage across the series bias resistor R. is Dr-üo and the current
through it is:

i.:(ur-0")/R,:ut(l-av)/R. (2.9)

Hence the effective input impedance introduced by the bias resistor is:

Z in*: ü tl i":R./(l - au) (2.10)

Fig. 2.10 Bootstrapped emitter follower.

40 Electronics, Noise and Signal Recovery

Since a, for an emitter follower is close to unity, Zrn,"is many times larger
than R.. This means that a relatively small R., which will not reduce
significantly the d.c. bias current provided by the main bias resistors R, and
Rr, will be adequate to bring the emitter voltage input impedance back to
quite a high value. For example, in a case where R": 1 kO, Rl - Rz :20 kO,
R,:2kQ, and §:200, Zr^will be increased from -10kQ to -200kO by
this circuit arrangement.

2.8 Paralleled transistors

In certain applications, such as power amplifiers and power supplies, it may

be necessary to exceed the current or power specifications of a given type of
transistor. In that case it is attractive to attempt to put a number of such
transistors in parallel. However, this can be a recipe for disaster, since if one
transistor takes too much current and "blows", this will put more strain on
the other transistors, and the remainder of them will be induced to blow
(sometimes audibly, and at an accelerating rate!). However, this problem
can be overcome by placing a low-value resistor in series with each of the
emitters (Figure 2.ll). Then an increase in current through any transistor
will reduce the voltage across its emitter-base junction, and the current will
be brought back towards the design level - with the result that the total
current will be shared more evenly between the transistors. In fact, this is a
further example of the use of local negative feedback - a topic that will be
discussed in more detail in Chapter 5.

Fig. 2.11 Paralleled transistors. Here a small resistor (typically - 1O) is placed in
series with each emitter, thereby stabilizing the individual emitter currents. This is
actually an example of negative feedback (see Chapter 5).
Circuit Building Blocks 41

Fig. 2.12 Beanstalk amplifier.

2.9 Beanstalk amplifier

The aim of this circuit (Figure 2.12) is to amplify a.c. signals to

amplitudes that are higher than any individual transistor can cope with. The
idea is to spread the output voltage between a number of transistors, thereby
preventing them from being exposed to unacceptable potential differences
across their terminals. The lowest transistor and the resistor chain divide
the collector voltage swing evenly between the set of transistors. For the
circuit shown in Figure 2.12 containing three transistors, the maximum
voltage swing hence approaches 3(%")-u*. To understand the mode of
operation in more detail, imagine that the resistors are adjusted, in isolation,
to give the ideal voltages at the collectors: clearly, they would need to have
equal values to achieve this. Next, recall that each emitter-base junction will
produce a voltage drop of 0.6 V. Thus the resistor chain will have to be
adjusted to give a voltage at each base equal to the ideal collector voltage
for the next lower transistor, plus 0.6 V in each case.

2.1O Artificial reactance circuits

In many applications, artilicial reactances are required whose values can be

adjusted easily over a considerable range - as for example in frequency meters
42 Electronics, Noise and Signal Recovery

or remotely controlled radio tuners. One of the main problems with variable
capacitors is the small range over which they can be varied: this is because
stray capacitances limit the range of capacitances to factors (C^ JC^i,)
typically between 10 and 20 (note that even smaller factors in frequency
range result when these capacitors are used in tuned circuits, because of the
square root relation f :lpnJLq. In addition, variable inductors are
difficult to produce, and also large inductors and capacitors are bulky and
expensive. Hence there is considerable merit in having circuits which can
simulate inductors and capacitors, especially if these can be constructed
conveniently using resistors and low-value capacitors, together with active
circuit elements such as transistors.
The circuit of Figure 2.13 acts as an artificial inductor. To understand its
operation, consider the various currents and voltages:

i.: §it (2.11)

U
- Ub": Rin (2.12)

uu": (in -io)ljaC (2.13)

ü6" : hi"i6 (2.r4)

Eliminating i* and io gives:

ü:ub"+R(rb *jaCuo")
:ia(hi"+ R +j@CR/ri")

:i.(hi.+ R +jarCRh")10 (2.1s)

uli"x(R+ jafRhr")l§ (2.16)

Fig. 2.13 Artificial reactance circuit. The circuit shown in this figure acts as an
artificial inductor. Note that this is an idealized circuit and that d.c. bias circuitry is
not included in the diagram.
Circuit Building Blocks 43

where we have assumed that R>>/r,", which is normally valid for R greater
than a few kilohms. This equation implies that the transistor is acting as an
inductor of value CRhkl P in series with a resistance of value Rl P, as suggested
above. What is happening is that a small capacitive control voltage at the
base, coupled with the natural inverting characteristic of the transistor, is
making it act as an inductor.In a similar way, by interchanging the capacitor
and the resistor, the transistor can be made to act as a capacitor. A formal
proof of this is left as an exercise for the reader.

2.11 A square-law function generator

In this circuit (Figure 2.14) two matched FETs are joined together in a
symmetrical way and fed with signals of opposite phase. (Note that signals
of equal amplitude and opposite phase may be obtained with the l-transistor
phase-splitting circuit mentioned in Section 1.6, with R":R".) The FET is
known to have an approximately square-law transfer function:

/¿:1¿r.[1 +Vs"lve)2 (2.17)

where Z, is the "pinch-off" voltage.

In the given circuit, if the input voltages are applied with different phases
relative to a constant voltage 4,we have:

161 : /¿..[1 * Vs{lYr)z : 1¿..[1 + (V^+ Y)l Y;2 (2.18)

162 : 1¿,.[1 * Vr"2l Yo)2 : 1¿..[1 + (V^- V)l Ypf2 (2.te)

Fig.2.l4 FET squarelaw function generator. This square-law function generator

circuit does not include d.c. bias circuitry. In addition, it has to be fed from a
phase-splitter providing two waveforms of opposite phases at the two gate inputs.
44 Electronics. Noise and Signal Recovery

Hence the output voltage in the given circuit is:

Va:Y¿6- R(Iü+ Id2)

:V66-2R16"" t+21
vp
+4+
vr" T*)
:Vy-kVt2 (2.20)

where k and Vn arc constants. In practice, voltage level setting circuits can
eliminate V*, and then the circuit becomes a true square-law function
generator. Such circuits are useful for performing functions such as measuring
power or forming part of analogue multiplying circuits, based on the
"quarter-squares" principle, the latter being given by the following equation:

v"v, : il(v" + vr), - (v, - Y)2f (2.2t)

Clearly, two square-law function generator circuits are required to build such
a multiplier, and in addition an adder and two subtractors are required.

2.12 Summary

This chapter has described a number of useful circuit building blocks. These
have included various emitter follower configurations (the White emitter
follower, the complementary emitter follower, and the bootstrapped emitter
follower), the Darlington and complementary Darlingtbn conhgurations, and
the Vo" multiplier, most of which will prove useful later on when designing
audio frequency and d.c. amplifiers and operational amplifiers (see Chapters
5 and 8). Other circuits discussed were parallelled transistors and the
beanstalk amplilier - these being useful when circuits have to withstand
currents or voltages greater than the rated values of the transistors to be
employed - and artificial reactance circuits (useful, e.g., for generating
frequency-modulated signals) and the square-law function generator.
Although some of these circuits might seem trivial at first, they embody
important principles. In addition, a number of them illustrate the extra degree
of freedom available to the designer when complementary devices (e.g. npn
and pnp transistors) can be employed. This contrasts with the situation in
the early days of radio when thermionic valves had to be used, and electrons
were the only charge carriers that could be invoked.
Circuit Building Blocks 45

Finally, although most of the circuits described in this chapter employ

BJTs, in many cases equivalent versions of these circuits can be designed
using FETs. Space precludes a full discussion of the situation, but note that
the square-law function generator (Section 2.ll) can be implemented
accurately using FETs, whilst there is no obvious corresponding solution
using BJTs.

2.13 Bibliography

As in the case of Chapter 1, the volumes by Calvert and McCausland (1978),

Horowitz and Hill (1989) and Watson (1989), between them, provide
significantly more depth on the work of this chapter. In particular, the second
of these books provides a wealth of practical detail, while the third delves
further into the underlying theory.

2.14 Problems

1. Give a full derivation of equations (2.4) and (2.7) for the dynamic
impedance of a Vo. multiplier. Also, obtain an alternative version of
equation (2.7) in which R, is approximated as the geometric mean of h,"
and hr"l(B + 1) in order to satisfy equations (2.5) and (2.6). Does this
alternative equation predict significantly different values of p at voltages
Vo:3,6,9 and l2Y?
2. Use the theory of Section 1.7 to determine the basic voltage gain of an
emitter follower. Hence obtain a corrected value for the input impedance
of a bootstrapped emitter follower (see equation 2.10). How accurate are
the numerical predictions of Section2.T for the increase in input impedance
of an emitter follower produced by bootstrapping?
3. Following the methods of Section 2.10, find a formula for the effective
capacitance of an artificial capacitor circuit. What gain in capacitance is
achievable with this circuit, assuming reasonable resistor values? Show
that this gain in capacitance could be improved considerably with an
FET-based circuit.
4. It was assumed in Section 2.ll that identical FETs have to be used to
form a squareJaw function generator. Show that this is not so, and that
mis-matched FETs can be used if the input voltages are suitably adjusted.
46 Electronics, Noise and Signal Recovery

what modifications must be made to the circuit of Figure 1.10 to provide

a suitable phase-splitter to feed the FET circuit?
5. A 4-quadrant multiplier is one which takes inputs of either sign and
produces a product of the correct sign. similar definitions apply for
2-qtadrant and l-quadrant multipliers. If a quarter-squares multiplier is
built using the FET square-law circuit (see Section 2.ll), in how many
quadrants does it operate correctly?