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Tutorial 8 Answers

Cache memory is a small, high-speed memory that stores a copy of frequently used instructions and data from main memory in order to reduce access time. For a given computer configuration with 256KB primary memory, 4KB cache, and program requirements of 128KB instructions and 512KB data, the effective memory access time is calculated as 21.5 nanoseconds. The three common cache mapping techniques are direct mapping, associative mapping, and set associative mapping. For the sample computer configuration with a 32KB cache and 64MB main memory, the address splitting for each mapping technique is outlined.

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25 views

Tutorial 8 Answers

Cache memory is a small, high-speed memory that stores a copy of frequently used instructions and data from main memory in order to reduce access time. For a given computer configuration with 256KB primary memory, 4KB cache, and program requirements of 128KB instructions and 512KB data, the effective memory access time is calculated as 21.5 nanoseconds. The three common cache mapping techniques are direct mapping, associative mapping, and set associative mapping. For the sample computer configuration with a 32KB cache and 64MB main memory, the address splitting for each mapping technique is outlined.

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M Arif Siddiqui
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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ITDR2102: Computer Organization – Tutorial Answers

Tutorial 8
From Lecture 8 (Memory – Part2)

1. What purpose does cache serve?


Cache memory is a small amount of very high speed memory to hold a portion of the memory
temporarily.

2. A given computer is running a program which requires 128K of instructions and 512K of data.
The computer has 256K of primary memory and a 4K cache. Memory access time is 80 ns. If
the desired word is in cache, the access time is 15 ns. The hit ratio for this program is 0.9.
What is the effective access time?
The effective access time = 0.9 x 15 + 0.1 x 80 = 13.5 + 8 = 21.5 nanoseconds

3. List 3 ways of mapping memory addresses into cache.


1. Direct mapping.
2. Associative mapping.
3. Set associative mapping.

4. Assume a cache of 32 Kbytes organized as 4 K lines of 8 bytes each. The main memory is 64
MB organized logically as 8 M blocks of 8 bytes each.
a. Determine how to split the address (s-r, r, w) for direct mapping.
b. Determine how to split the address (s, w) for associative mapping.
c. Determine how to split the address (s-d, d, w) for set associative mapping. Assume
each cache set is 4 lines of cache.
Data given:
* Memory size=64 MB * Cache size= 32KB
* Block size = line size = 8 bytes. * Number of cache lines = 4K lines.
* Number of memory blocks = 8M blocks

a. Direct mapping:
Block size = 8 = 23 = 2w  w=3.
Number of lines = 4K = 22x210 = 212 = 2r  r=12
Memory size = 64MB = 26x220 = 226 = 2n  memory address bits n= 26
s = n-w = 26-3 = 23
s-r = 23 – 12 = 11
Tag (s-r) Line (r) Word (w)
11 12 3

b. Associative mapping:
Block size = 8 = 23 = 2w  w=3.
s = n-w = 26 -3 = 23
Tag (s) Word (w)
23 3

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ITDR2102: Computer Organization – Tutorial Answers

c. 4-set associative mapping:


Block size = 8 = 23 = 2w  w=3.
Number of sets in cache= = = 1𝐾 =1x210 = 210 = 2d  d=10
s = n-w = 26-3 = 23
s-d = 23 – 10 = 13

Tag (s-d) Set (d) Word (w)


13 10 3

Extra question for question 4:

d. Determine how to split the address (s-d, d, w) for set associative mapping. Assume
each cache set is 2 lines of cache.

d. 2-set associative mapping:


Block size = 8 = 23 = 2w  w=3.
Number of sets in cache= = = 2𝐾 =21x210 = 211 = 2d  d=11
s = n-w = 26-3 = 23
s-d = 23 – 11 = 12

Tag (s-d) Set (d) Word (w)


12 11 3

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