CS359: Computer Architecture

Single-cycle Processor
(C0mputer Organization: Chapter 4)

Yanyan Shen
Department of Computer Science
and Engineering

1
Fundamentals

The Processor: Datapath & Control

p Our implementation of the MIPS is simplified
m memory-reference instructions: lw, sw
m arithmetic-logical instructions: add, sub, and, or, slt
m control flow instructions: beq, j
Fetch
PC = PC+4
p Generic implementation
m use the program counter (PC) to supply
the instruction address and fetch the Exec Decode
instruction from memory (and update the PC)
m decode the instruction (and read registers)
m execute the instruction

p All instructions (except j) use the ALU after reading the

registers
m How memory-reference? arithmetic? control flow?
2
Fundamentals

How to Design a Processor: step-by-step

p 1. Analyze instruction set => datapath requirements
m the meaning of each instruction is given by the register transfers
m datapath must include storage element for ISA registers
n possibly more

m datapath must support each register transfer

p 2. Select set of datapath components and establish clocking
methodology
p 3. Assemble datapath meeting the requirements
p 4. Analyze implementation of each instruction to determine
setting of control points that effects the register transfer.
p 5. Assemble the control logic

3
Fundamentals

The MIPS Instruction Formats

p All MIPS instructions are 32 bits long. The three instruction formats:
31 26 21 16 11 6 0
m R-type op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
31 26 21 16 0
m I-type
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
m J-type 31 26 0
op target address
6 bits 26 bits
p The different fields are:
m op: operation of the instruction
m rs, rt, rd: the source and destination register specifiers
m shamt: shift amount
m funct: selects the variant of the operation in the “op” field
m address / immediate: address offset or immediate value
m target address: target address of the jump instruction

4
Fundamentals

Focus on a Subset of MIPS Instructions

7 Instructions 31 26 21 16 11 6 0
p ADD and subtract op rs rt rd shamt func
m add rd, rs, rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
m sub rd, rs, rt
p OR Immediate:
m ori rt, rs, imm16
31 26 21 16 0
p LOAD and STORE
op rs rt immediate
m lw rt, rs, imm16
6 bits 5 bits 5 bits 16 bits
m sw rt, rs, imm16
p BRANCH:
m beq rs, rt, imm16
p JUMP:
m j target 31 26 0
op target address
6 bits 26 bits

5
Fundamentals

Aside: Logical Register Transfers

p RTL gives the meaning of the instructions

p All start by fetching the instruction

op | rs | rt | rd | shamt | funct = MEM[ PC ]
op | rs | rt | Imm16 = MEM[ PC ]

inst Register Transfers

ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4
SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4
ORI R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4
LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4
STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4

BEQ if ( R[rs] == R[rt] ) then PC <– PC + 4 +sign_ext(Imm16)] || 00

else PC <– PC + 4 6
Fundamentals

Step 1: Requirements of the Instruction Set

p Memory (MEM)
m Instructions & data
p Registers (R: 32 x 32)
m Read rs
m Read rt
m Write rt or rd
p PC
p Extender (sign/zero extend)
p Add/Sub/OR unit for operation on register(s) or extended
immediate
p Add 4 (+ maybe extended immediate) to PC

7
Fundamentals

Step 2: Components of the Datapath

p Combinational Elements
p Storage Elements
m Clocking methodology

8
Fundamentals

Combinational Logic Elements

p Adder p MUX Select
CarryIn
A A
32 32

MUX
Adder
Sum Y
32 32
B
B Carry 32
32

OP
p ALU
A
32
ALU

Result
32
B
32

9
Fundamentals

Storage Element: Register File

p Register File consists of 32 registers: RW RA RB
m Two 32-bit output busses: Write Enable 5 5 5
busA and busB busA
m One 32-bit input bus: busW busW 32 32-bit 32
32
Clk Registers busB
p Register is selected by: 32
m RA (number) selects the register to put on busA (data)
m RB (number) selects the register to put on busB (data)
m RW (number) selects the register to be written
via busW (data) when Write Enable is 1

p Clock input (CLK)

m The CLK input is a factor ONLY during write operation
m During read operation, behaves as a combinational logic block:
n RA or RB valid => busA or busB valid after “access time.”
10
Fundamentals

Storage Element: Idealized Memory

Write Enable Address
p Memory (idealized)
m One input bus: Data In
Data In DataOut
m One output bus: Data Out 32 32
Clk
p Memory word is selected by:
m Address selects the word to put on Data Out
m Write Enable = 1: address selects the memory
word to be written via the Data In bus

p Clock input (CLK)

m The CLK input is a factor ONLY during write operation
m During read operation, behaves as a combinational logic
block:
n Address valid => Data Out valid after “access time.”

11
Fundamentals

Aside: Clocking Methodologies

p The clocking methodology defines when data in a state
element is valid and stable relative to the clock
m State elements - a memory element such as a register
m Edge-triggered – all state changes occur on a clock edge
p Typical execution
m read contents of state elements -> send values through
combinational logic -> write results to one or more state elements
State Combinational State
element logic element
1 2

clock

one clock cycle

q Assumes state elements are written on every clock cycle;
if not, need explicit write control signal
● write occurs only when both the write control is asserted and the
clock edge occurs
12
Fundamentals

Aside: Clocking Methodologies

Clk
Setup Hold Setup Hold
Don’t Care

. . . .
. . . .
. . . .
p All storage elements are clocked by the same clock edge
p Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew

13
Fundamentals

Step 3: Assemble DataPath meeting our requirements

p Register Transfer Requirements

Þ Datapath Assembly
p Instruction Fetch
p Read Operands and Execute Operation

14
Fundamentals

Generic Steps of Datapath

registers
rd
instruction
memory
PC

rs

memory
ALU

Data
rt

+4 imm
mux

1. Instruction 2. Decode/ 5. Register

3. Execute 4. Memory
Fetch Register Write
Read

15
Fundamentals

Fetching Instructions
p Fetching instructions involves
m reading the instruction from the Instruction Memory M[PC]
m updating the PC value to be the address of the next
(sequential) instruction PC ← PC + 4
clock

Add
Fetch 4
PC = PC+4
Instruction
Memory
Exec Decode
PC Read Instruction
Address

● PC is updated every clock cycle, so it does not need an

explicit write control signal just a clock signal
● Reading from the Instruction Memory is a combinational
activity, so it doesn’t need an explicit read control signal
16
Fundamentals

Decoding Instructions
p Decoding instructions involves
m sending the fetched instruction’s opcode and function field
bits to the control unit

Fetch Control
PC = PC+4 Unit

Exec Decode
Read Addr 1
Read
Instruction Read Addr 2 Data 1

Write Addr Read

Data 2
Write Data
and

● reading two values from the Register File

- Register File addresses are contained in the instruction

17
Fundamentals

Executing R-type Instructions

7 Instructions 31 26 21 16 11 6 0
p ADD and subtract op rs rt rd shamt func
m add rd, rs, rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
m sub rd, rs, rt
p OR Immediate:
m ori rt, rs, imm16
31 26 21 16 0
p LOAD and STORE
op rs rt immediate
m lw rt, rs, imm16
6 bits 5 bits 5 bits 16 bits
m sw rt, rs, imm16
p BRANCH:
m beq rs, rt, imm16
p JUMP:
m j target 31 26 0
op target address
6 bits 26 bits

18
Fundamentals

Datapath of RR R-type
31 26 21 16 11 6 0
op rs rt rd shamt func
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

p RTL R[rd] ← R[rs] op R[rt] Example: add rd, rs, rt

rd rs rt
RegWr 5 5 ALUctr add/sub
5
busA
Rw Ra Rb
busW 32 32-bit 32 Result

ALU
32 Registers 32
Clk busB
32

What are controls signals for

Ra, Rb, Rw correspond to rs, rt, rd
add rd, rs, rt”
ALUctr,RegWr: control signal ALUctr=add RegWr=1
19
Fundamentals

I-type instruction ori

31 26 21 16 11 6 0
p ADD and subtract op rs rt rd shamt func
m add rd, rs, rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
m sub rd, rs, rt
p OR Immediate:
31 26 21 16 0
m ori rt, rs, imm16
op rs rt immediate
p LOAD and STORE 6 bits 5 bits 5 bits 16 bits
m lw rt, rs, imm16
m sw rt, rs, imm16
p BRANCH:
m beq rs, rt, imm16
p JUMP:
m j target
31 26 0
op target address
26 bits
6 bits

20
Fundamentals

RTL: The OR Immediate Instruction

31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
p ori rt, rs, imm16
m M[PC] Instruction Fetech
m R[rt] ← R[rs] or ZeroExt(imm16)
zero extension of 16 bit constant or R[rs]
m PC ← PC + 4 update PC

Zero extension ZeroExt(imm16)

31 1615 0
0000 0000 0000 0000 immediate
16 bits 16 bits

21
Fundamentals
Datapath of Immediate Instruction
p R[rt] ← R[rs] op ZeroExt[imm16]] Example: ori rt, rs, imm16
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
Write the results of R-Type
instruction to Rd Why need multiplexor here?
Rd Rt
RegDst 0 Mux 1 Don’t Care
Rs (Rt) ALUctr
RegWr 5 5 5
busA
Rw Ra Rb
busW 32 Result
32 32-bit

ALU
32 Registers 32
Clk busB
0
32 Mux
ZeroExt

1
imm16
16 32
ALUSrc
Ori control signals RegDst= RegWr= ALUctr= ALUSrc=
Ori control signals RegDst=1 RegWr=1 ALUctr=or ALUSrc=1 22
Fundamentals

Datapath for lw (memory access instruction)

31 26 21 16 11 6 0
p ADD and subtract op rs rt rd shamt func
m add rd, rs, rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
m sub rd, rs, rt
p OR Immediate:
31 26 21 16 0
m ori rt, rs, imm16
op rs rt immediate
p LOAD and STORE 6 bits 5 bits 5 bits 16 bits
m lw rt, rs, imm16
m sw rt, rs, imm16
p BRANCH:
m beq rs, rt, imm16
p JUMP:
m j target
31 26 0
op target address
6 bits 26 bits

23
Fundamentals

RTL: The Load Instruction

31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
p lw rt, rs, imm16
m M[PC] Instruction Fetch
m Addr ← R[rs] + SignExt(imm16) Compute the address
m R[rt] ← M [Addr] Load Data to rt
m PC ← PC + 4 Update PC

Why using signed extension rather than zero extension?

31 16 15 0
0000 0000 00000 0000 0 immediate
31 16 bits 16 15 16 bits 0
1111 1111 1111 1111 1 immediate
16 bits 16 bits
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Fundamentals

Datapath for Load Instruction

p R[rt] ← M[ R[rs] + SignExt[imm16] ] Example: lw rt, rs, imm16
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
Rd Rt
RegDst Why?
0 Mux 1
Don’t Care
Rs ALUctr
RegWr5 5 5 (Rt)
MemtoReg
busA
Rw Ra Rb
busW 32
32 32-bit

ALU
0
32 32

Mux
Registers
Clk busB 0 MemWr 32
32 1
Mux

WrEn Adr
1 Data In
Ext

imm16 32 Data
16 32
Clk Memory
ALUSrc

ExtOp 0:zero extension 1: sign extension

What are control
RegDst=1, signals
RegWr=1, -- RegDst, ExtOp=1,
ALUctr=add, RegWr, ALUctr, ExtOp,
ALUSrc=1, ALUSrc, MemWr,
MemWr=0, MemtoReg?
MemtoReg=1
25
Fundamentals

SW instruction
31 26 21 16 11 6 0
p ADD and subtract op rs rt rd shamt func
m add rd, rs, rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
m sub rd, rs, rt
p OR Immediate: 31 26 21 16 0
m ori rt, rs, imm16 op rs rt immediate
p LOAD and STORE 6 bits 5 bits 5 bits 16 bits
m lw rt, rs, imm16
m sw rt, rs, imm16
p BRANCH:
m beq rs, rt, imm16
p JUMP:
m j target
31 26 0
op target address
6 bits 26 bits

26
Fundamentals

RTL: The Store Instruction

31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits

p sw rt, rs, imm16

m M[PC]
m Addr ← R[rs] + SignExt(imm16)
m Mem[Addr] ← R[rt]
m PC ← PC + 4

27
Fundamentals
Datapath for SW
p M[ R[rs] + SignExt[imm16] ] R[rt] Example: sw rt, rs, imm16

31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
Rd Rt
RegDst
0 Mux 1 Why add this?
Rs
Rt ALUctr
RegWr 5 5 5 MemWr MemtoReg
busA
Rw Ra Rb
busW 32
32 32-bit

ALU
0
32 32

Mux
Registers busB
Clk 0 32
Mux
32 Data In 1
WrEn Adr
1 32
Ext

imm16 32 Data
16 Memory
ALUSrc Clk

ExtOp
RegDst=x, RegWr=0, ALUctr=add, ExtOp=1, ALUSrc=1, MemWr=1, MemtoReg=x
28
Fundamentals

Beq
31 26 21 16 11 6 0
p ADD and subtract op rs rt rd shamt func
m add rd, rs, rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
m sub rd, rs, rt
p OR Immediate: 31 26 21 16 0
m ori rt, rs, imm16 op rs rt immediate
p LOAD and STORE 6 bits 5 bits 5 bits 16 bits
m lw rt, rs, imm16
m sw rt, rs, imm16
p BRANCH:
m beq rs, rt, imm16
p JUMP:
m j target
31 26 0
op target address
6 bits 26 bits

29
Fundamentals

RTL: The Branch Instruction

31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits

p beq rs, rt, imm16

m M[PC]
m Cond ← R[rs] - R[rt] Compare rs and rt
m if (COND eq 0) Calculate the next instruction’s address
PC ← PC + 4 + ( SignExt(imm16) x 4 )
else
PC ← PC + 4

30
Fundamentals
Datapath for beq
p beq rs, rt, imm16 We need to compare Rs and Rt !
31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
Branch
Rd Rt Next Addr
RegDst imm16
0 Mux 1 Logic
Rs Rt 16
RegWr 5 5 5 ALUctr
busA PC
Rw Ra Rb Clk
busW 32

ALU
32 32-bit Zero
32
Clk Registers busB To Instruction
0
32 Memory
Mux

Q: How to design the addressing

1
imm16 logic?
Ext

32
16
ExtOp ALUSrc

RegDst=x, RegWr=0, ALUctr=sub, ExtOp=x, ALUSrc=0, MemWr=0, MemtoReg=x,

Branch=1 31
Fundamentals
Instruction Fetch Unit at the End of Branch
31 26 21 16 0
op rs rt immediate

p if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

Inst
Memory Instruction<31:0>
Branch Adr
Zero

MUX ctrl
Rs Rt ALUctr
RegWr 5 5 5
4 busA
Rw Ra Rb Zero
busW
Adder

32

ALU
32 32-bit
00

0 32
Clk Registers busB
Mux

32
PC
Adder

1
PC Ext

imm16
clk
32
Fundamentals

Jump Operation
31 26 21 16 11 6 0
p ADD and subtract op rs rt rd shamt func
m add rd, rs, rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
m sub rd, rs, rt
p OR Immediate: 31 26 21 16 0
m ori rt, rs, imm16 op rs rt immediate
p LOAD and STORE 6 bits 5 bits 5 bits 16 bits
m lw rt, rs, imm16
m sw rt, rs, imm16
p BRANCH:
m beq rs, rt, imm16
p JUMP:
m j target
31 26 0
op target address
6 bits 26 bits

33
Fundamentals

Executing Jump Operations

p Jump operation involves
m replace the lower 28 bits of the PC with the lower 26 bits of the
fetched instruction shifted left by 2 bits

Add
4
4
Jump
Instruction Shift address
Memory 28
left 2
PC Read Instruction
Address 26

34
Fundamentals

Single Cycle Datapath Without Jump

0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 Data 1 zero
Read Data
PC Instr[31-0] 0 File ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control
Instr[5-0]

35
Fundamentals

Step 4: Adding the Control

p Selecting the operations to perform (ALU, Register File and
Memory read/write)
p Controlling the flow of data (multiplexor inputs)
31 25 20 15 10 5 0
R-type: op rs rt rd shamt funct
q Observations 31 25 20 15 0
● op field always I-Type: op rs rt address offset
in bits 31-26 31 25 0
● addr of registers J-type: op target address
to be read are
always specified by the
rs field (bits 25-21) and rt field (bits 20-16); for lw and
sw rs is the base register
● addr. of register to be written is in one of two places –
in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type
instructions
● offset for beq, lw, and sw always in bits 15-0 36
Fundamentals

R-type Instruction Data/Control Flow

0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 Data 1 zero
Read Data
PC Instr[31-0] 0 File ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control
Instr[5-0]

37
Fundamentals

Load Word Instruction Data/Control Flow

0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 Data 1 zero
Read Data
PC Instr[31-0] 0 File ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control
Instr[5-0]

38
Fundamentals

Branch Instruction Data/Control Flow

0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 Data 1 zero
Read Data
PC Instr[31-0] 0 File ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control
Instr[5-0]

39
Fundamentals

Adding the Jump Operation

Instr[25-0] 1
Shift
26 28 32
left 2
PC+4[31-28] 0
Add 0
Add 1
4 Shift
Jump left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 Data 1 zero
Read Data
PC Instr[31-0] 0 File ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control
Instr[5-0]

40
Fundamentals

Assemble Control Logic

Instruction<31:0>
Inst

<21:25>

<21:25>

<16:20>

<11:15>

<0:15>
Memory
Adr
Op Fun Rt Rs Rd Imm16

Decoder

nPC_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Equal

DATA PATH

41
Fundamentals
A Summary of the Control Signals
func 10 0000 10 0010 We Don’t Care :-)
op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
add sub ori lw sw beq jump
RegDst 1 1 0 0 x x x
ALUSrc 0 0 1 1 1 0 x
MemtoReg 0 0 0 1 x x x
RegWrite 1 1 1 1 0 0 0
MemWrite 0 0 0 0 1 0 0
Branch 0 0 0 0 0 1 0
Jump 0 0 0 0 0 0 1
ExtOp x x 0 1 1 x x
ALUctr<2:0> Add Subtr Or Add Add Subtr xxx

31 26 21 16 11 6 0
R-type op rs rt rd shamt func add, sub

I-type op rs rt immediate ori, lw, sw, beq

J-type op target address jump

42
Fundamentals
The Concept of Local Decoding
Two levels of decoding: Main Control and ALU Control
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
R-type ori lw sw beq jump
RegDst 1 0 0 x x x
ALUSrc 0 1 1 1 0 x
MemtoReg 0 0 1 x x x
RegWrite 1 1 1 0 0 0
MemWrite 0 0 0 1 0 0
Branch 0 0 0 0 1 0
Jump 0 0 0 0 0 1
ExtOp x 0 1 1 x x
ALUctr Add/Subtr Or Add Add Subtr xxx
ALUctr is
func determined by
ALU ALUctr
op Main 6 ALUop and
ALUop Control 3 func, while
6 Control (Local) other control
N=?
signals are

ALU
How many bits will N need? 3, why? determined by
op
R, or, +, -, and, …
43
Fundamentals

The Decoding of the “func” Field

func
op 6 ALU ALUctr
Main
ALUop Control
6 Control 3
N (Local)
Encoding ALUop as follows

R-type ori lw sw beq jump

ALUop (Symbolic) R-type” Or Add Add Subtr xxx
ALUop<2:0> 1 00 0 10 0 00 0 00 001 xxx

31 26 21 16 11 6 0
R-type 000000 rs rt rd shamt func

func<5:0> Instruction Operation ALUctr ALUctr<2:0> ALU Operation

10 0000 add 000 Add
10 0010 subtract 001 Subtract
10 0100 and 010 And
ALU

10 0101 or 110 Or
10 1010 set-on-less-than 001 Subtract

44
Fundamentals

The Truth Table for ALUctr

R-type Instructions Non-R-type Instructions
determined by funct determined by ALUop funct<3:0> Instruction Op.
0000 add
ALUop R-type ori lw sw beq 0010 subtract
(Symbolic) R-type” Or Add Add Subtr 0100 and
ALUop<2:0> 1 00 0 10 0 00 0 00 001 0101 or
1010 set-on-less-than

ALUop func ALU ALUctr

bit2 bit1 bit0 bit<3> bit<2> bit<1> bit<0> Operation bit<2> bit<1> bit<0>
0 0 0 x x x x Add 0 0 0
0 x 1 x x x x Subtract 0 0 1
0 1 0 x x x x Or 1 1 0
1 x x 0 0 0 0 Add 0 0 0
1 x x 0 0 1 0 Subtract 0 0 1
1 x x 0 1 0 0 And 0 1 0
1 x x 0 1 0 1 Or 1 1 0
1 x x 1 0 1 0 Subtract 0 0 1

45
Fundamentals

The Logic Equation for ALUctr<0>

Choose the rows with ALUctr[0]=1

ALUop func
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<0>
0 x 1 x x x x 1
1 x x 0 0 1 0 1
1 x x 1 0 1 0 1

This makes func<3> a don’t care

p ALUctr<0> = !ALUop<2> & ALUop<0> +

ALUop<2> & !func<2> & func<1> & !func<0>

46
Fundamentals

The Logic Equation for ALUctr<1>

Choose the rows with ALUctr[1]=1

ALUop func
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<1>
0 1 0 x x x x 1

1 x x 0 1 0 0 1
1 x x 0 1 0 1 1

p ALUctr<1> = !ALUop<2> & ALUop<1> & ! ALUop<0> +

ALUop<2> & !func<3> & func<2> & !func<1>

47
Fundamentals

The Logic Equation for ALUctr<2>

Choose the rows with ALUctr[2]=1

ALUop func
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<2>
0 1 0 x x x x 1
1 x x 0 1 0 1 1

p ALUctr<2> = !ALUop<2> & ALUop<1> & !ALUop<0>

+ ALUop<2> & !func<3> & func<2> & !func<1> & func<0>

48
Fundamentals

Summary of Control Logic of Local Control

func
6 ALU ALUctr
ALUop Contro
3
l
3
(Local)
p ALUctr<0> = !ALUop<2> & ALUop<0> +
ALUop<2> & !func<2> & func<1> & !func<0>
p ALUctr<1> = !ALUop<2> & ALUop<1> & !ALUop<0> +
ALUop<2> & !func<3> & func<2> & !func<1>
p ALUctr<2> = !ALUop<2> & ALUop<1> & !ALUop<0> +
ALUop<2> & !func<3> & func<2> & !func<1> & func<0>

49
Fundamentals
The “Truth Table” for the Main Control
RegDst
func
ALUSrc ALUctr
op 6 ALU
Main :
Control 3
6 Control ALUop
(Local)
Output of Main Control 3
Input of main control
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
R-type ori lw sw beq jump
RegDst 1 0 0 x x x
ALUSrc 0 1 1 1 0 x
MemtoReg 0 0 1 x x x
RegWrite 1 1 1 0 0 0
MemWrite 0 0 0 1 0 0
Branch 0 0 0 0 1 0
Jump 0 0 0 0 0 1
ExtOp x 0 1 1 x x
ALUop (Symbolic) R-type” Or Add Add Subtr xxx
ALUop <2> 1 0 0 0 0 x
ALUop <1> x 1 0 0 x x
ALUop <0> x 0 0 0 1 x

50
Fundamentals

The “Truth Table” for RegWrite

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
R-type ori lw sw beq jump
RegWrite 1 1 1 0 0 0

p RegWrite = R-type + ori + lw

= !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type)
+ !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0>(ori)
+ op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0>(lw)
..
op<5> ..
op<5> ..
op<5> ..
op<5> ..
op<5> ..
op<5>
<0> <0> <0> <0> <0> op<0>

Decoder

R-type ori lw sw beq jump

RegWrite

51
Fundamentals

Assemble Main Control (PLA)

op<5>. . op<5>. . op<5>. . op<5>. . op<5>. . op<5>. .
<0> <0> <0> <0> <0> op<0>
Decoder

R-type ori lw sw beq jump

RegWrite

ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUop<2>
ALUop<1>
ALUop<0>
52
Fundamentals

The Complete Single Cycle Data Path with Control

ALUop
ALU ALUctr
RegDst 3 func
op Control 3
Main 6
ALUSrc Instr<5:0>
6 Control :
Instr<31:26> Branch Instruction<31:0>
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Jump
Rd Rt Fetch Unit
RegDst Clk
1 Mux 0
Rs Rt Rt Rs Rd Imm16
RegWr 5 5 5 ALUctr
MemtoReg
busA Zero MemWr
Rw Ra Rb
busW 32
32 32-bit

ALU
32 0
Registers busB 0 32

Mux
32
Mux

Clk 32
32
WrEn Adr 1
1 Data In
Ext

imm16 Data
32
Instr<15:0> 16 Clk Memory
ALUSrc

ExtOp
53