As originally published in the SMTA International Conference Proceedings.
SOLDER JOINT RELIABILITY ANALYSIS AND TESTING
OF A DUAL ROW QFN PACKAGE
Luke England and Yong Liu
Fairchild Semiconductor
South Portland, ME, USA
[email protected],
[email protected] Richard Qian1 and Ji-Hwan Kim2
Fairchild Semiconductor
Suzhou, China1 and Bucheon, Korea2
[email protected],
[email protected]ABSTRACT Key words: QFN, dual row, mechanical modeling, thermal
QFN packages have become mainstream designs for cycle
mobile applications. As more applications adopt the QFN
style packages, I/O count requirements are increasing. The INTRODUCTION
typical method for increasing pin count in a QFN package As mobile electronic devices become smaller, the shrinking
is to increase the body size to accommodate the additional of packages for these devices is a necessity. QFN style
lead fingers. This is undesirable though, as mobile device package have become mainstream technology in mobile
users are pushing for smaller package sizes. By using a applications throughout the industry. Their leadframe based
dual row design, more lead fingers can be added in the technology makes them ideal for ease of manufacturing at a
same overall body size. This increases the overall low cost, and also provide excellent thermal performance
performance to package size ratio. for high power devices. As I/O counts increase, many
suppliers are moving toward substrate based packages such
Previous studies published on dual row QFN packages as BGA to avoid increasing the package area while
focus mainly on design considerations for manufacturing. increasing the number of interconnects. These package
[1-3] Since the current design uses standard lead frame types are higher cost, however, due to the more expensive
processing techniques, no additional processing strategies substrates.
are needed compared to single row QFN production.
Dual row QFN designs help to bridge the gap between
This study focused on the board level solder joint reliability conventional single row QFN packages and BGA style
of a 28 lead dual row QFN package. Prior to manufacturing, packages. They enable a higher I/O count per area of single
a mechanical modeling DOE was performed for various row QFN packages, and they also maintain similar costing
dual row QFN footprints to estimate the solder joint due to the leadframe based technology. This makes them
lifetime through temperature cycle testing. The modeling attractive over substrate based packages in many cases.
was followed by prototype manufacturing of daisy chain
units. The daisy chain devices were subjected to Within the dual row QFN family, there are multiple options
temperature cycle testing according to JEDEC for design. The inner row of leadfingers must be supported
specifications. Testing was continued until the complete during manufacturing using tie bars that can be connected
lifetime estimation curve could be obtained. It was to the center die attach pad (DAP), if available, or to the
determined that a dual row design can actually improve same connecting bar that the outer row of leadfingers is
solder joint reliability performance when compared to a attached to. [2] The later is preferred because connecting
single row design of similar body size. Since there are no the inner row of leadfingers to the DAP requires an extra
lead fingers in the immediate corners of the package for the sawing process to electrically separate the leadfingers from
dual row design, which is typically the highest stress area the DAP. Connecting the inner row of leadfingers to the
of the package during testing, the overall solder joint same connecting bar as the outer row allows all leadfingers
lifetime can be increased. Although the typical failed lead to become electrically isolated during one saw pass.
fingers on the dual row package were still the farthest
distance away from the package center, these lead fingers The option also exists for inline or staggered row
are not located in the package corners. Final results show configurations, which can both be used in either leadfinger
that the dual row QFN package has good performance tie bar connection method described previously. The
through temperature cycle testing, with a performance staggered dual row configuration does have some
increase over standard single row QFN packages. advantages over the inline configuration, however. For one,
a larger number of leadfingers can be designed into a
As originally published in the SMTA International Conference Proceedings.
package of a specific x-y size. During solder paste printing Inline and staggered dual row configurations were designed
for surface mounting of the devices, the staggered row using minimum leadframe design rules and dimensions. No
configuration minimizes the chance for solder bridging JEDEC outline was followed (i.e. MO-267). Designs for
since the closest points between two inter row pads is a each are shown in Figure 1 and 2. It can be seen that the
corner rather than an entire side. staggered row design has 28 leads, but the inline
configuration only allowed for 26 leads. This is essentially
because the staggered design can have a smaller between
row pitch than the inline design due to leadframe metal-to-
metal feature and half etch design rules. The major features
(a) of the final package design are listed in Table 1.
Table 1: Dual row QFN package design features.
(c) Design Feature Value
Package Size 2.9x3.6mm
Package Thickness 0.55mm Max
(b)
Leadframe Thickness 6mil (Cu)
Lead Count 28
Figure 1: Drawings showing the design and finite
element model of the staggered dual row package. (a) Lead Size 0.2x0.25mm
Leadframe (b) Top Package Surface (c) Bottom Package
Within Row Pitch 0.60mm
S f
Between Row Pitch 0.375mm
DAP Size 1.14x1.84mm
Mechanical Modeling
Finite element models were constructed initially to predict
(a)
the best performing leadframe configuration. A three-
dimensional non-linear finite element model was developed
(c) in ANSYS for the numerical simulations. The finite
element models used for the staggered and inline designs
are shown in Figures 1 and 2. In order to simplify the
calculations, wire bonding was ignored in the modeling.
Solder was assumed to be SAC405 since accurate modeling
(b) parameters for this alloy were previously obtained. [4]
Figure 2: Drawings showing the design and finite The thermal cycle testing board contained 32 packages
element model of the inline dual row package. (a) mounted to a single board. The board is inserted into a
Leadframe (b) Top Package Surface (c) Bottom Package socket for electrical resistance monitoring. Figure 3a shows
S f the overall board layout for thermal cycle testing. To
simplify calculations only one package and the board area
This study focused on the board level thermal cycle
immediately surrounding it were used in the modeling,
reliability of a 28L dual row QFN package. Specific
which is illustrated in Figure 3b. Details of the test board
package size requirements for a particular application were
design are further discussed in the following section.
given, and both inline and staggered configurations were
initially compared through designs and modeling activities.
Figure 4 shows the finite element model of the package and
After the ideal configuration was selected, leadframes were
the portion of the thermal cycle testing board that was used
procured, and daisy chain devices were created for board
in modeling. For the calculations, the two surfaces of the
level thermal cycle testing. The final thermal cycle results
thermal cycle testing board were set to be symmetrical
were then compared to the mechanical modeling results for
planes. Anand’s constitutive model was used and the
accuracy.
material properties were described as viscoplastic elements.
The Anand constants of SAC405 solder that were used for
EXPERIMENTAL
modeling are listed in Table 2. For the calculations, the
Package Design
thermal load is considered to be uniform. Temperature is
A target package size of 2.9x3.6mm with a 0.55mm
applied to all elements of the model (package, solder, and
thickness was given for a particular application. The goal
test board). The temperature range for modeling was -40C-
was to fit as many I/O’s into this package size as possible.
As originally published in the SMTA International Conference Proceedings.
125C with conditions that match those described in the
following section.
In addition to stress modeling, the first failure and
characteristic lifetime were also modeled using previous
known numerical methods. [5]
Initial modeling was performed using a single layer
element in the solder in order to reduce calculation time.
This method was sufficient for a general comparison of the
design configurations in order to predict the best performer. (b)
Following completion of thermal cycle testing, however, it
was found that the modeling results did not agree well with
the experimentally determine values. The model was (a)
subsequently adjusted to include five layer elements in the Figure 3: (a) Thermal cycle testing board drawing. (b)
solder, which helped to improve the accuracy of the Part of thermal cycling board in modeling.
modeling results.
Daisy Chain Testing
Daisy chain packages were assembled using the final
leadframe design. In order to form the continuous electrical
path for resistance monitoring, leadfingers were wire
bonded together as shown in Figure 5. The corresponding
lands were connected in the test PCB.
The PCB test board design followed the IPC-9701 standard.
It was a single board containing 32 test sites, and the
overall board layout is shown in Figure 3a. The board
contained 8 total layers (1+6+1), and was fabricated using (a)
standard build-up technology. Solder mask was NSMD
Table 2: Experimentally determined fitted Anand model
constants for SAC405 solder alloy. [4]
Description Symbol Constant
Initial value of s so 20 MPa
Activation energy Q/R 10561 K
Pre-exponential factor A 325/s
Stress multiplier ζ 10
Strain rate sensitivity of (b)
stress
m 0.32
Hardening coefficient ho 8.0E5 MPa
Coefficient for
deformation resistance ŝ 42.1 MPa
saturation value
Strain rate sensitivity of Figure 4: (a) Board model used for thermal cycle testing.
saturation value
n 0.02 (b) Finite element model of package mounted to test
board. Although these show the inline design specifically,
Strain rate sensitivity of they are representative of the staggered design as well.
hardening coefficient a 2.57
As originally published in the SMTA International Conference Proceedings.
with Via-in-Pad land pads. Surface mounting also followed
the IPC-9701 standard, and was done using stencil printing
with SAC305 paste and component placement. Reflow was
performed in a nitrogen atmosphere. There was some
difficulty in getting good solder paste release out of the
small apertures, but using a 2mil thick stencil minimized
the issue. A 2mil thick stencil is not ideal for
manufacturing, but time constraints prevented in depth
surface mount studies using a more conventional 4mil thick
stencil.
Thermal cycle testing was done according to IPC-9701
condition TC3. The temperature cycle range was from -40-
125C. Two cycles per hour were performed, and a 10min
dwell time was used at each peak. Daisy chain resistance
was continuously monitored using an event detector, and a
fail was recorded if the resistance exceeded the set (a) (b)
threshold of 1000. Final data analyzed and a Weibull plot Figure 6: Resulting maximum Von-Mises stress of the
was generated using the two-parameter distribution solder joints. (a) Staggered: 59.25MPa (b) Inline: 59.3MPa
function shown in the following equation:
t
F (t ) 1 exp
where F(t) is the cumulative density function, is the scale
parameter or characteristic lifetime, and is the shape
parameter or slope. [6]
(a) (b)
Figure 7: Resulting maximum viscoplastic strain
energy density of the solder joints. (a) Staggered =
2.82MPa (b) Inline = 2.83MPa
2.00
1.80 Staggered Lead Design
1.60 Inline Lead Design
Plastic work / volume (Mpa) ,
1.40
Figure 5: Package sketch showing the wire bond scheme 1.20
for the daisy chain packages. The leadfingers were bonded
1.00
together, and corresponding land pads on the PCB were
0.80
connected to form the electrical resistance loop. A dummy
die was present in the package for testing, but no wire 0.60
bonds were made to it. 0.40
0.20
RESULTS AND DISCUSSION 0.00
Modeling 0 1000 2000 3000 4000 5000 6000 7000 8000
Figure 6 shows the max Von-Mises stress and Figure 7 time (sec)
shows the viscoplastic energy density after the fourth
temperature cycle. It can be seen that both the max Von- Figure 8: Plot showing a comparison of the viscoplastic
strain energy densities for the staggered and inline designs.
As originally published in the SMTA International Conference Proceedings.
Mises stress and viscoplastic strain energy density of the
inline design are slightly higher than those of the staggered
design. Within the solder joint, both the max Von-Mises
stress and viscoplastic strain energy density are located at
the point where the solder paste connects to the package
leadfinger. This predicts that the failing solder crack during
testing will appear near this interface. Figure 8 shows the
viscoplastic strain energy density comparison through the (a)
first four temperature cycles. It can be seen that the
viscoplastic strain energy density is rising at a greater rate
for the inline design, which indicates that the staggered
design is more robust through thermal cycling.
Once it was determined that the staggered configuration
was the optimum configuration, the overall effects of the
test board structure were also modeled. Two different board
types were investigated. Table 3 shows the conditions of
each group along with the results, while Figure 9 shows a
cross sectional view of the model with and without the
center Cu layers in the board. (b)
Figure 10 shows the resulting maximum Von-Mises
stresses and viscoplastic energy density for each group
tested. A definite dependence upon internal Cu layer
content can be seen in the Von-Mises stress and predicted
lifetime values. The modeling results show that the better
performance can be gained by using a board with the least Figure 9: Cross section drawing of package/board model
amount of Cu layers possible. The plot of viscoplastic (a) without and (b) with center Cu layers.
energy density for each group illustrates this. The reason is
because the board will then be less stiff overall, which will
result in less stress applied to the solder joints due to the
material’s CTE mismatch. Although this configuration was (a) (b)
shown to be the best case, our actual thermal cycle testing
was done using the board with multiple layers of Cu. The
reason is that this follows the IPC-9701 specification for
test board design. By testing this configuration, the worst
case is essentially being verified.
Table 3: Modeling group details and their corresponding (c) (d)
lifetime predictions. 2-Cu layer boards have only front and
backside Cu layers, while 8-Cu layer boards contain 6
internal Cu layers (1+6+1 Configuration). Group B
matches the experimental board design.
Predicted Character
Board # of Cu
Group First Cycle
Thickness Layers
Failure Failure
(e) (f)
A* 2.35mm 2 7,232 11,761
B* 2.35mm 8 6,016 9,784
Thermal Cycle Testing
Based on the modeling results described in the previous
section, board level thermal cycle testing was performed on
the staggered dual row configuration only. The package Figure 10: Resulting maximum Von-Mises stress and
proved to be very robust as testing was stopped at 9,528 viscoplastic strain energy density for the two modeling
cycles with only a 53% failure rate. conditions. (a-b) Location of results (c) Group A:
58.87MPa (d) Group B: 59.25MPa (e) Group A:
The thermal cycle Weibull plot is shown in Figure 12 along 2.64MPa (f) Group B: 2.82MPa.
with the two sided confidence bounds at a 90% confidence
As originally published in the SMTA International Conference Proceedings.
ReliaSoft W eibull++ 7 - www.ReliaSoft.com
99
2.00
1.80 Staggered (8 Layer Cu) 90 = 1.11
1.60 Staggered (2 Layer Cu) = 1.57x104
Plastic work / volume (Mpa) ,
1.40 50
1.20
Unreliability, F(t)
1.00
0.80
10
0.60
0.40 5
0.20
0.00
0 1000 2000 3000 4000 5000 6000 7000 8000 1
100 1000 10000
Cycles
time (sec)
Figure 11: Plot showing a comparison of the viscoplastic Figure 12: Weibull plot showing all thermal cycle failures.
strain energy densities for each test group listed in Table 3. Early failures before 3,500 cycles (shown in brackets) are
most likely surface mount related, coming from the
level. The failures can be grouped into two categories – difficulties encountered during board assembly. The 95%
failures less than 3,500 cycles and failures greater than confidence bounds indicate marginal lifetime prediction.
6,000 cycles. It is suspected that the early failures (< 3,500
ReliaSoft W eibull++ 7 - www.ReliaSoft.com
cycles) are the result of the surface mounting issues that 99
Probability - Weibull
were encountered during board assembly, which are
described further in Experimental section. When looking at 90 = 7.76
the failures over 6,000 cycles a very tight Weibull = 1.003x104
distribution can be seen. This plot is shown in Figure 13. 50
This suggests a first failure at approximately 5,500 cycles
Unreliability, F(t)
when consistent surface mounting can be achieved, with a
50% failure rate of almost 10,000 cycles. This data matches
our modeling results very well (see Table 3). Since there is 10
such good matching between modeling and experimental 5
data, it supports the suspicion that the early failures were
the result of surface mounting problems. Although the early
failures appear to be in a separate grouping, they are still
1
occurring after enough thermal cycles for sufficient 100 1000
Cycles
10000
reliability in mobile applications, which is the main target
of this package type. Figure 13a: Weibull plot showing failures over 6,000
cycles. The 95% confidence bounds are tight around the
Failure analysis was performed on select daisy chain best fit line, which indicates very good lifetime prediction.
packages. Cross sections of Pin #26 and Pin #28 of the Scale is the same as shown in Figure 12.
device that failed at 8,311 cycles are shown in Figure 14,
ReliaSoft W eibull++ 7 - www.ReliaSoft.com
along with a diagram showing the plane of cross sectioning. 99
Probability - Weibull
These pins are located in the package end position, which is
one of the points of highest stress due to the large distance 90 = 7.76
from the package centroid. Based on this it was expected = 1.003x104
that these pins would be the first to fail. 50
Unreliability, F(t)
Unfortunately the board design contained all of the test
samples, so failures were unable to be pulled for analysis
immediately after an event was detected. Many of the 10
devices, especially the early failures, saw extra thermal 5
cycles after failure occurred. For instance, the first failure
at 665 cycles was stressed all the way through 9,528 cycles
when testing ended. This made it difficult to determine the
1
root cause of failure. Based on this experience, it is 3000
Cycles
10000
recommended that multiple boards be used with fewer
package sites per board to enable more accurate failure Figure 13b: Weibull plot repeating results of 13a, but at a
analysis. higher scale (3,000-10,000 cycles) for better data viewing.
As originally published in the SMTA International Conference Proceedings.
Both of these design differences help the staggered
configuration to better resist the stresses applied during
thermal cycling due to material CTE mismatches.
Leadframes were designed in the staggered configuration,
26 and daisy chain packages were assembled for thermal cycle
(a) testing. The results revealed a very robust package, and
28 testing was stopped after just over 9,500 cycles with only a
53% failure rate. Failures appear to be segregated into two
groups. It is suspected, but not proven, that the group of
early failures is stemming from the surface mounting issues
encountered during test board assembly.
Initial modeling predictions did not provide a good match
to the experimental data. Subsequent adjustments to the
calculations greatly improved the predictions, and resulted
in a good correlation between modeling and experimental
data. For instance, initial modeling only utilized one layer
element through the solder joint, and increasing to five
layer elements provided more accurate calculations. In
(b) addition, the material properties used in the model greatly
Crack
affect the outcome; therefore, it is critical to have accurate
material property inputs in order to achieve good results.
REFERENCES
1. Y. Ming et al., "Design considerations on solder joint
reliability of dual row quad flat no-lead packages,"
Proc. of Electronics Packaging Technology
Conference, 2004, pp. 308-312.
2. M.J. Ramos et al., "The Method of Making Low-cost
Multiple-Row QFN," Proc. of International Electronic
Manufacturing Technology Symposium, 2007, pp. 261-
(c) 267.
Crack
3. D.V. Retuta et al., "Design and process optimization
for dual row QFN," Proc. of Electronic Components
and Technology Conference, 2006, pp. 9 pp.
4. Q. Wang et al., "Experimental Determination and
Modification of Anand Model Constants for Pb-Free
Material 95.5Sn4.0Ag0.5Cu," Proc. of International
Conference on Thermal, Mechanical and Multi-
Physics Simulation Experiments in Microelectronics
Figure 14: (a) Diagram showing cross section plane for and Micro-Systems, EuroSime 2007, pp. 1-9.
failure analysis. (b) Pin 26 cross section. (c) Pin 28 cross 5. R. Darveaux, "Effect of simulation methodology on
section. Failure mode is solder cracking. solder joint crack growth correlation," Proc. of
Electronic Components and Technology Conference,
CONCLUSIONS
2000, pp. 1048-1058.
Mechanical modeling of two dual row QFN design
6. www.weibull.com.
configurations (staggered and inline) for a given x-y
package size was performed. The staggered configuration
was predicted to have better thermal cycle performance for
two main reasons:
The staggered configuration simply has more
pins/leadfingers within the given package size.
The inline configuration has only two leadfingers on
each end, while the staggered configuration has three
leadfingers on each end.
