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8086 Pin Configuration Part 5B

The document discusses the pin configurations and functions of the 8086 microprocessor. It describes several pins including: DT/R which controls data direction; DEN which enables the 8286 transreceiver; INTR which requests interrupts; NMI which triggers non-maskable interrupts; INTA which acknowledges interrupts; HOLD and HLDA used for DMA transfers; RQ/GT1 and RQ/GT0 which are request/grant signals for other processors; LOCK which prevents other processors from accessing the bus; and QS1 and QS0 which provide the status of the instruction queue. It also outlines the S0, S1, and S2 status pins which indicate the current operation to the 8288 bus controller.

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127 views

8086 Pin Configuration Part 5B

The document discusses the pin configurations and functions of the 8086 microprocessor. It describes several pins including: DT/R which controls data direction; DEN which enables the 8286 transreceiver; INTR which requests interrupts; NMI which triggers non-maskable interrupts; INTA which acknowledges interrupts; HOLD and HLDA used for DMA transfers; RQ/GT1 and RQ/GT0 which are request/grant signals for other processors; LOCK which prevents other processors from accessing the bus; and QS1 and QS0 which provide the status of the instruction queue. It also outlines the S0, S1, and S2 status pins which indicate the current operation to the 8288 bus controller.

Uploaded by

AMIT VERMA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Dr Manjusha

Microprocessor and Interfacing


Devices/Peripherals

8086 Pin Configuration

Part -5 B
Dr Manjusha Deshmukh
Dr Manjusha Deshmukh
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Dr Manjusha

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DEN, DT/ R Dr Manjusha

• DT/ R pin 27. 0


• It decides the
1 transmit
direction of data flow
through the 0
transreceiver. 8286
8086 Octal 11110000 20006 H
Bus Transceiver
A 16-A19 3H 3H
• DEN pin 26
Data Enable. It is used
to enable Transreceiver 2000 H 2000 H
20003 H

8286.

5 V DC Memory
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• INTR pin 18 Dr Manjusha
It is an interrupt request signal, Device
which is sampled during the last
clock cycle of each instruction to INTR 1
determine if the processor NMI
considered this as an interrupt or
not. INTA 0
• NMI pin 17
It stands for non- interrupt It is
an edge triggered inputnon Main Program Interrupt Routine
maskable, which causes an InstQ1
1
interrupt request to the InstQ1
1
microprocessor. InstQ2
2 InstQ2
2
• INTA pin 24. InstQ3
3 InstQ3
3
InstQ4
4
• It is an interrupt InstQ4
4
acknowledgement. When the InstQ5
5 InstQ5
5
microprocessor receives this InstQ6
6
signal, it acknowledges the InstQ7
7
interrupt.
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• Used for DMA Dr Manjusha

• HOLD pin 31.( Minimum Mode) Device 1


HOLD 1
Byte 1
Byte 2
This signal indicates to the
HLDA 1 Byte 3
processor that external devices
Byte 4
are requesting to access the
Byte 5
address/data buses. Main Program

Inst 1
• HLDA pin 30 ( Minimum Mode) Inst 2
Inst 3
Inst 4
It stands for Hold Device 2
Inst 5
Acknowledgement signal .
Inst 6
Inst 7
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RQ/GT1 and RQ/GT0
Pin 30 and 31 (Maximum Mode) RQ/GT0 0
0
These are the Request/Grant signals Processor 2
used by the other processors Inst 1
requesting the CPU to release the Main
Inst 2
TEST 1
system bus. Program Inst 3
Inst 1 Inst 4
• LOCK pin 29. (Maximum Mode) Inst 5
Inst 2
• When this signal is active, it Inst 3 Inst 6
indicates to the other processors Inst 4 Inst 7
not to ask the CPU to leave the Inst 5
system bus. Inst 6 Processor 3
LOCK 0
TEST Inst 7

If the TEST pin is Low, execution


continues. Otherwise the processor 0
waits in an "idle" state. RQ/GT
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• QS1 and QS0 pin 24 and 25 ( Minimum Mode)

These are queue status signals. These signals provide the status of instruction
queue.
Their conditions are shown in the following table −
QS0 QS1 Status
0 0 No operation
0 1 First byte of opcode
from the queue

1 0 Empty the queue


1 1 Subsequent byte from
the queue
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• S0, S1, S2 pin 26, 27, and 28. ( Maximum Mode) Dr Manjusha

• These are the status signals that provide the status of operation, which
is used by the Bus Controller 8288 to generate memory & I/O control
signals.
S
2 1 S 0S Status 8086 8288 oo0
INTA
0 0 0 Interrupt
acknowledgement S0 S0 oo1 I/O Read

0 0 1 I/O Read S1 S1 o10 I/O Write

0 1 0 I/O Write S2 S2 Halt

0 1 1 Halt 100 Opcode fetch


1 0 0 Opcode fetch
Bus Memory read
1 0 1 Memory read Controller
Microprocessor Memory write
1 1 0 Memory write 111 Passive
1 1 1 Passive Dr Manjusha Deshmukh
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Dr Manjusha Deshmukh

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