Abstract:

The technical and economic growth of the twentieth century was marked by evolution
of electronic devices and gadgets. The day-to-day lifestyle has been significantly affected by
the advancement in communication systems, information systems and consumer electronics.
The lifeline of progress has been the invention of the transistor and its dynamic up-gradation.
Discovery of fabricating Integrated Circuits (IC's) revolutionized the concept of electronic
circuits.

With advent of time the size of components decreased, which led to increase in
component density. This trend of decreasing device size and denser integrated circuits is
being limited by the current lithography techniques. Non-unifomity of doping, quantum
mechanical tunneling of electrons from source to drain and leakage of electrons through gate
oxide limit scaling down of devices.

Heat dissipation and capacitive coupling between circuit components becomes

significant with decreasing size of the components.

To deal with this constraint, the search M on to look around for alternative materials
for electronic device application and new methods for electronic device fabrication. Such
material is comprised of organic molecules, proteins, carbon materials, DNA and the list is
endless which can be grown in the laboratory. Many molecules show interesting electronic
properties, which make them probable candidates for electronic device applications.

The challenge is to interpret their electronic properties at nanoscale so as to exploit

them for use in new generation electronic devices. Need to trim downsize and have a higher
component density have ushered us into an era of nano-electronics.

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 CHAPTER 1

INTRODUCTION
Nano electronic is concerned with understanding and exploiting the properties of devices, which
have dimensions at the nano meter scale.

Microelectronics will gradually evolve into nano-electronic. In fact, this has already happened as
can be seen from the smallest feature size of present integrated circuits, which is below of one
micrometer. It is currently believed that optical lithography can be used for ground rules down to
150 nm and might even be used for the 100 nm generation and below. This would imply an
increasing process and mask complexity, and consequently, increasing the cost.

Molecular-scale electronic has been widely touted as "the next step" in electronic
miniaturization, with theory and research suggesting that single molecules may have the
capability to take the place of today's much larger electronic components.

what are the advantages of scaling down of devices?

Speed of operation – Reduction of the parasitic capacitances associated with non-conductive

paths in an electronic device leads to a higher cut-off frequency. This enables a device to operate
at much higher speeds. Density – An obvious advantage. This reduces size and cuts materials
cost. Power dissipation - This is reduced due to lesser resistance in interconnects and currents
flowing in smaller circuits. In lasers, the use of lower dimensional systems reduces the threshold
current due to improved density of states distribution. New applications - This enables certain
uses, currently speculative, but very much in the offing.

Integrated circuits are also known as microelectronic. The term micro derives from micro-
fabrication technology, which embraces all highly sophisticated techniques like optical- and
electron-beam lithography, metallization, implantation and etching that allow generating
structures on the scale of one micrometer.

In the early 1970's, two scientists, Ari Aviram and Mark Ratner, began to envision electronic
circuit elements made from single molecules and described in detail how they might function.

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This was the origin of the field of molecular electronics, now sometimes called molecular-scale
electronics.

The emergence of molecular electronics and spintronics is providing a challenge to traditional

electronic manufacturing techniques. Significant reduction in size and the sheer enormity of
numbers in manufacturing are the benefits of molecular electronics. Scientists predict that
computers will be assembled using molecules in the future, pushing technology far beyond the
limits of silicon.

1.1 WHAT IS NANOELECTRONICS

Nanoelectronics refers to the use of nano technology on electronic components,

especially transistors. Although the term nanotechnology is generally defined as utilizing
technology less than 100 nm in size, nanoelectronics often refer to transistor devices that are so
small that inter-atomic interactions and quantum mechanical properties need to be studied
extensively. As a result, present transistors do not fall under this category, even though these
devices are manufactured with 45 nm, 32 nm, or 22 nm technology.

Nanoelectronics are sometimes considered as disruptive technology because present candidates

are significantly different from traditional transistors. Some of these candidates include: hybrid
molecular/semiconductor electronics, one dimensional nano tubes /nano wires or advanced
molecular electronics.

1.2 WHY NANO

The term Nano is occupying a remarkable place in modern technology. But I believe
many of us are wondering what Nano can really do for us. The aim of this blog is to give an
overview about the nanotechnology to students, academic heads aiming to start nanotechnology
course in their institutes, and industrialists willing to know the potentiality of nanotechnology to
influence their industry.

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The basic element of most of the electronic devices has been the transistor which replaced
previously existing vacuum tubes, since its invention in 1947 by John Bardeen and Walter
Brattain at AT&T's Bell Labs in the United States. A Nobel Laureaute of Physics for the year
1965, "Richard Fenyman" has emphasized the potential of nanotechnology with his famous
quote "There's Plenty of Room at the Bottom" made in 1959. In 1965, Gordon E. Moore, co-
founder of Intel predicted that the number of components on the integrated circuit doubles every
two years for at least 10 years from then. This trend is called Moore's law has been valid even
now and is expected to continue for a couple of more years.

1.3 APPROACHES IN NANOELECTRONICS

1.3.1 BOTTOM UP

Fig 1. Nanoelectronics bottom up

Electronics obtained through the bottom-up approach of molecular-level control of

material composition and structure may lead to devices and fabrication strategies not possible
with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-
up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar
motif.

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 First, we will discuss representative electromechanical and resistance-change memory
devices based on carbon nanotube and core–shell nanowire structures, respectively. These device
structures show robust switching, promising performance metrics and the potential for terabit-
scale density.

Second, we will review architectures being developed for circuit-level integration, hybrid
crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key
concepts such lithography-independent, chemically coded stochastic demultiplexer’s. Finally,
bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional,
vertically integrated multifunctional circuits, will be critically discussed.

1.3.2 TOP DOWN

The most common top-down approach to fabrication involves lithographic patterning

techniques using short-wavelength optical sources. A key advantage of the top-down approach—
as developed in the fabrication of integrated circuits—is that the parts are both patterned and
built in place, so that no assembly step is needed. Optical lithography is a relatively mature field
because of the high degree of refinement in microelectronic chip manufacturing, with current
short-wavelength optical lithography techniques reaching dimensions just below 100 nanometers
(the traditional threshold definition of the nanoscale).

Shorter-wavelength sources, such as extreme ultraviolet and X-ray, are being developed
to allow lithographic printing techniques to reach dimensions from 10 to 100 nanometers.
Scanning beam techniques such as electron-beam lithography provide patterns down to about 20
nanometers. Here the pattern is written by sweeping a finely focused electron beam across the
surface. Focused ion beams are also used for direct processing and patterning of wafers, although
with somewhat less resolution than in electron-beam lithography. Still-smaller features are
obtained by using scanning probes to deposit or remove thin layers.

Mechanical printing techniques—nanoscale imprinting, stamping, and molding—have

been extended to the surprisingly small dimensions of about 20 to 40 nanometers. The details of
these techniques vary, but they are all based on making a master “stamp” by a high-resolution
technique such as electron-beam lithography and then applying this stamp, or subsequent

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generations of it, to a surface to create the pattern. In one variation a stamp’s surface is coated
with a very thin layer of material (the “ink”) that can then be deposited (“inked”) directly onto
the surface to reproduce the stamp’s pattern. For example, the controlled patterning of a
molecular monolayer on a surface can be achieved by stamping an ink of thiol functionalized
organic molecules directly onto a gold-coated surface (molecules that contain a sulfur end group,
called a thiol, bond strongly to gold).

In another approach the stamp is used mechanically to press the pattern into a thin layer
of material. This surface layer is typically a polymeric material that has been made pliable for the
molding process by being heated during the stamping procedure. Plasma etching can then be
used to remove the thin layer of the masking material under the stamped regions; any residual
polymer is thus removed, and a nanoscale lithographic pattern is left on the surface. Still another
variation is to make the relief pattern out of photoresist on a silicon wafer by optical or electron-
beam lithography and then pour a liquid precursor—for example, polydimethylsiloxane, a form
of silicone—over the pattern and then cure it. The result is a rubbery solid that can be peeled off
and used as a stamp.

These stamps can be inked and printed as described above, or they can be pressed to the
surface and a liquid polymer allowed to flow into the raised regions of the mask by capillary
action and cured in place. A distinction for this latter approach is that the stamp is flexible and
can thus be used to print nanoscale features on curved surfaces.

These nanoscale printing techniques offer several advantages beyond the ability to use a
wider variety of materials with curved surfaces. In particular, such approaches can be carried out
in ordinary laboratories with far-less-expensive equipment than that needed for conventional
submicron lithography. The challenge for all top-down techniques is that, while they work well
at the microscale (at millionths of a meter), it becomes increasingly difficult to apply them at
nanoscale dimensions.

A second disadvantage is that they involve planar techniques, which means that
structures are created by the addition and subtraction of patterned layers (deposition and
etching), so arbitrary three-dimensional objects are difficult to construct.

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 CHAPTER 2

LITERATURE.

2.1 BOTTOM / CORE DEVICES IN NANO ELECTRONICS

2.1.1 CARBON NANOTUBES (CNTS):

Fig 2. Carbon Nanotubes

Carbon Nanotubes (Cnts) are allotropes of carbon with a cylindrical nanostructure.

Nanotubes have been constructed with length-to-diameter ratio of up to
132,000,000:1,[1] significantly larger than for any other material. These
cylindrical carbon molecules have unusual properties, which are valuable for
nanotechnology, electronics, optics and other fields of materials science and technology. In
particular, owing to their extraordinary thermal conductivity and mechanical
and electrical properties, carbon nanotubes find applications as additives to various structural
materials

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 2.1.2 ELECTRICAL PROPERTIES

Fig 3. CNT Electrical properties

Band structures computed using tight binding approximation for CNT (zigzag, metallic)
CNT (semiconducting) and CNT (armchair, metallic).

Because of the symmetry and unique electronic structure of graphene, the structure of a
nanotube strongly affects its electrical properties. For a given (nm.) nanotube, if n = m, the
nanotube is metallic; if n − m is a multiple of 3, then the nanotube is semiconducting with a very
small band gap, otherwise the nanotube is a moderate semiconductor. Thus, all armchair (n = m)
nanotubes are metallic, and nanotubes etc. are semiconducting.

However, this rule has exceptions, because curvature effects in small diameter carbon
nanotubes can strongly influence electrical properties. Thus, SWCNT that should be
semiconducting in fact is metallic according to the calculations. Likewise, vice versa—zigzag
and chiral SWCNTs with small diameters that should be metallic have finite gap (armchair
nanotubes remain metallic). In theory, metallic nanotubes can carry an electric current density of
4 × 109 A/cm2, which is more than 1,000 times greater than those of metals such
as copper, where for copper interconnects current densities are limited by electromigration.

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 2.1.3 FABRICATION OF CARBON NANOTUBES
FABRICATION

The most common method used to fabricate carbon nanotubes is electric-arc discharge.
An electric arc is an electrical breakdown of a gas which produces an ongoing plasma discharge,
similar to the instant spark, resulting from a current flowing through normally nonconductive
material such as air. The arc occurs in the gas-filled space between two conductive electrodes
(often made of carbon) and it results in a very high temperature, capable of melting or vaporizing
just about anything. So, this process takes place like this:

1) A current is run through an anode, or a positively charged piece of carbon,

2) Then this current jumps through a certain type of plasma material to a cathode, or a negatively
charged piece of carbon, where there is an evaporation and deposition of carbon particles in
through the plasma,

3) Finally, an outer hard-shell region made of decomposed graphite is formed and an inner core
region with loosely packed columns which consist of straight, stiff multi shell carbon nanotubes
and closed polyhedral particles (also known as carbon nanoparticles). These columns grow at a
rate of approximately 1mm per minute on the cathode surface. The best result of carbon
nanotubes and nanoparticles from the anode that can be obtained is about 25%. The average
temperature in the plasma where the nanotubes are formed is very high at 4000 K (about 6740
degrees F).

To obtain single-shell carbon nanotubes, a catalyst must be added to the evaporated

carbon. This catalyst is commonly a metal such as cobalt, nickel, or a mixture of certain other
metals. This metal catalyst along with graphite powder is added in a hole drilled through the
anode contact (we will see later that this catalyst addition adds to the impurities on the
nanotubes). During the arc-discharge, web-like structures are formed around the cooler parts of
the electrodes. Within these structures, bundles of 10-100 single shell nanotubes are formed. This
particular method is normally very inefficient, but the use of a nickel-yttrium catalyst has
improved the efficiency and overall production of single shell nanotubes.

silicon oxide substrate can be used as the gate oxide and adding a metal contact on the back

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makes the semiconducting CNT gate able.

This technique suffered from several drawbacks, which made for non-optimized
transistors. The first was the metal contact, which actually had very little contact to the CNT,
since the nanotube just lay on top of it and the contact area was therefore very small. Also, due to
the semiconducting nature of the CNT, a Schott key Barrier forms at the metal-semiconductor
interface, increasing the contact resistance. The second drawback was due to the back-gate
device geometry. Its thickness made it difficult to switch the devices on and off using low
voltages, and the fabrication process led to poor contact between the gate dielectric and CNT.

Top-gated CNTFETs

Fig 6. The process for fabricating a top-gated CNTFET.

Eventually, researchers migrated from the back-gate approach to a more advanced top-gate
fabrication process. In the first step, single-walled carbon nanotubes are solution deposited onto
a silicon oxide substrate. Individual nanotubes are then located via atomic force microscope or
scanning electron microscope. After an individual tube is isolated, source and drain contacts are
defined and patterned using high resolution electron beam lithography. A high temperature
anneal step reduces the contact resistance by improving adhesion between the contacts and CNT.
A thin top-gate dielectric is then deposited on top of the nanotube, either via evaporation or
atomic layer deposition. Finally, the top gate contact is deposited on the gate dielectric,
completing the process.

Arrays of top-gated CNTFETs can be fabricated on the same wafer, since the gate

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contacts are electrically isolated from each other, unlike in the back-gated case. Also, due to the
thinness of the gate dielectric, a larger electric field can be generated with respect to the
nanotube using a lower gate voltage. These advantages mean top-gated devices are generally
preferred over back-gated CNTFETs, despite their more complex fabrication process.

Wrap-around gate CNTFETs

Sheathed CNT

Gate all-around CNT Device

Wrap-around gate CNTFETs, also known as gate-all-around CNTFETs were developed in

2008, and are a further improvement upon the top-gate device geometry. In this device, instead
of gating just the part of the CNT that is closer to the metal gate contact, the entire circumference
of the nanotube is gated. This should ideally improve the electrical performance of the CNTFET,
reducing leakage current and improving the device on/off ratio.

Device fabrication begins by first wrapping CNTs in a gate dielectric and gate contact via atomic
layer deposition. These wrapped nanotubes are then solution-deposited on an insulating substrate,
where the wrappings are partially etched off, exposing the ends of the nanotube. The source,
drain, and gate contacts are then deposited onto the CNT ends and the metallic outer gate
wrapping.

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2.2 SI NANODOTS

fig 9. Si nanodots

What Are Nanodots?

Nanodots, also known as quantum dots, consist of 100s-1000s of atoms of inorganic

semiconductor nanoparticles and are approximately one billionth of a meter in size. Developed in
the mid-1980s for optoelectronic applications, they have interesting structural, electronic, and
optical properties - they strongly absorb light in the near UV range and re-emit visible light that
has its color determined by both the nanodot size and surface chemistry. And as the size of
nanodots can be controlled during synthesis with nanoscale precision, so the optical properties
can be manipulated. In addition, nanodots have a longer life than organic fluorophores, and have
a broad excitation spectrum. These factors combined make the use of quantum dots as light-
emitting phosphors a strong candidate for a major application of nanotechnology in the future.

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 2.2.1 FABRICATION OF SI NANODOTS

Fig 10. Fabrication Of Si Nanodots

schematically in Figure 1(a). Details of the fabrication process can be found elsewhere.19 In our
experiment, optical deep-UV lithography (DUVL) was used to form the initial polysilicon line
patterns with widths of 250 nm, lengths of12 μm, and thicknesses of 120 nm. A 10-nm-thick
silicon dioxide film was deposited conformally by low-pressure chemical vapor deposition
(LPCVD). Directional blank etching of the silicon dioxide film removes the film on the
horizontal surface to leave residual silicon dioxide spacer nanowires on the sidewalls of the
original polysilicon features. Silicon dioxide nanowires were formed by selective removal of the
polysilicon using reactive ion etching (RIE).
Then the silicon dioxide nanowire pattern was transferred into the silicon substrate to
form silicon nanowires. Note that the width of the silicon nanowire pattern is determined by the
thickness of the conformal silicon dioxide layer, whereas the pitch of the silicon nanowire is
determined by the initial line width of the optical lithography. Because the thickness of the
deposited film can be controlled to 10 nm or less with high precision, this method permits the
generation of nanopatterns far smaller than possible by optical lithography. In this way, we have
batch-fabricated high aspect ratio sub-20-nm Si wires from 250-nm patterns generated by DUV
optical photolithography (Figure 1b and c).

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 2.2.2 ELECTRICAL PROPERTIES

The electrical transport behavior of n-n indium nitride nanodot-silicon (InN ND-Si)
heterostructure Schottky diodes is reported here, which have been fabricated by plasma-assisted
molecular beam epitaxy. InN ND structures were grown on a 20 nmInN buffer layer on Si
substrates. These dots were found to be single crystalline and grown along [0 0 0 1] direction.
Temperature-dependent current density-voltage plots (J-V-T) reveal that the ideality factor (?)
and Schottky barrier height (SBH) (FB) are temperature dependent. The incorrect values of the
Richardson constant (A**) produced suggest an inhomogeneous barrier.

Descriptions of the experimental results were explained by using two models. First one is
barrier height inhomogeneities (BHIs) model, in which considering an effective area of the
inhomogeneous contact provided a procedure for a correct determination of A**. The
Richardson constant is extracted ~110 A cm-2 K-2 using the BHI model and that is in very good
agreement with the theoretical value of 112 A cm-2 K-2. The second model uses Gaussian
statistics and by this, mean barrier height F0 and A** were found to be 0.69 eV and 113 A cm-2
K-2, respectively.

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2.3 NANOWIRES

A nanowire is a nanostructure, with the diameter of the order of a nanometer

(10−9 meters). Alternatively, nanowires can be defined as structures that have a thickness or
diameter constrained to tens of nanometers or less and an unconstrained length. At these scales,
quantum mechanical effects are important — which coined the term "quantum wires". Many
different types of nanowires exist, including metallic (e.g., Ni, Pt, Au), semiconducting
(e.g., Si, InP, GaN, etc.), and insulating (e.g., SiO2, TiO2). Molecular nanowires are composed of
repeating molecular units either organic (e.g., DNA) or inorganic (e.g. Mo6S9-xIx).

The nanowires could be used, in the near future, to link tiny components into extremely
small circuits. Using nanotechnology, such components could be created out of chemical
compounds.

Fig 11. Nanowires

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 2.3.1 FABRICATION OF NANOWIRES AT SURFACES

The goal of this project is the design of artificial materials that consist of
ultrafine wires or linear arrays of dots, ten to hundred times finer than those produced with
commercial micro-structure fabrication techniques. In fact, we have gone all the way down
to atom chains which may be viewed as the ultimate nanowires (scroll to the bottom for those).
These patterns are formed by self-assembly, where atoms arrange themselves naturally
at stepped silicon surfaces.

An important aspect in fabricating nanowires is the ability to prepare wires of an any material on
any substrate with any thickness. In particular, using silicon wafers as substrate is highly-
desirable. To achieve this goal we suggest the following "universal" process. First, a silicon
substrate with a regular array of steps is prepared (A). Then, stripes (B) or dots (C) of a
passivating material are attached to the step edges. This part is analogous to creating a
photoresist mask in traditional lithography.

As mask material we use calcium fluoride, which is lattice-matched to silicon and chemically
inert. Eventually, the desired material is deposited on the remaining silicon, for example by
substrate-selective chemical vapor deposition (CVD) or electroplating. Alternatively, calcium
fluoride could become useful as an etch mask for producing trenches in the silicon that can be
filled with new materials to achieve a planar structure.

The figure below shows the preparation of calcium fluoride masks in schematic form (top),
together with actual data (bottom).

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 Fig 12 Preparation Of Calcium Fluoride Masks

To start along this pathway, we determine the conditions for obtaining highly-regular step
structures on silicon. The images below demonstrate the range of step arrays that can be formed
on silicon surfaces by self-assembly. Typically, the step spacing is comparable to the size of a
virus. These images are taken with a scanning tunneling microscope (STM). They show the
derivative of the tip height. That gives the impression of a surface illuminated from the left, with
the steps casting dark shadows to the right.

Particularly perfect step arrays could be achieved on the Si(111)7x7 surface. The 7x7
structure causes steps running along the [011]-direction to become extremely straight, because
each kink requires generating 14 new rows of silicon atoms (7 rows, two layers deep). The step
edges are atomically-straight with a kink spacing as low as a single kink in 20,000 atoms, as
seen in the image below. These are taken with a scanning tunneling microscope (STM). The x-
derivative of the topography is displayed, which makes steps appear as dark lines. The image on
the right zooms in on the terrace between two steps (heavy dark lines). The atomic pattern of the
7x7 structure structure is resolved, which has fine grooves built in that run parallel to the step

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edges. These grooves are 2.3 nm apart and determine the location of possible step edges. They
may be viewed as the LEGO blocks of the aspiring nano-engineer.
Fabrication of straight steps:

Our "universal process" can be carried further by producing a calcium fluoride mask, as shown
in the image below. A stepped silicon surface is coated with a layer of CaF1 and CaF2 stripes are
formed on top of that layer. These stripes are continuous and do not touch each other, because
adjacent stripes cannot bond to each other. The stripe width of 7 nm achieved here is well below
the resolution of 180 nm achieved in commercial lithography for chip fabrication.

The third step of the "universal process" involves selective deposition or etching between the
masked areas. The picture below shows that molecules can be deposited selectively in the
CaF1 grooves between CaF2stripes. Using organometallic molecules, such as ferrocene, it is
possible to fabricate iron wires 3 nanometers wide.

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 2.3.2 ELECTRICAL PROPERTIES

A simple and useful experimental alternative to field-effect transistors for measuring

electrical properties (free electron concentration nd, electrical mobility μ, and conductivity σ) in
individual nanowires has been developed. A combined model involving thermionic emission and
tunneling through interface states is proposed to describe the electrical conduction through the
platinum nanowire contacts, fabricated by focused ion beam techniques. Current-voltage (I-V)
plots of single nanowires measured in both two- and four-probe configurations revealed high
contact resistances and rectifying characteristics. The observed electrical behavior was modeled
using an equivalent circuit constituted by a resistance placed between two back-to-back Schottky
barriers, arising from the metal-semiconductor-metal (M-S-M) junctions. Temperature-
dependent I-V measurements revealed effective Schottky barrier heights up to ΦBE=0.4 eV.

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 CHAPTER 3
ARCHITECTURE

3.1 APPLICATION BUILT USING BOTTOM DEVICES

3.1.1 CNFET

Carbon Nanotube FETs (CNFETs) are showing significant promise in nanoelectronics.

They are one of the principal areas of research that are seen as having the capability of replacing
MOSFET transistors. In fact, their performance is much better than MOSFETs below 10nm, with
the operation frequencies of CNFET devices being up to1000 times greater. This project
investigates various properties of CNFETs and particularly their application in digital logic
design. Various logic gates were built using CNFETs, and their properties are studied. Finally, a
4-bit Ripple Carry Adder (RCA) was built using the gates and the power dissipation and
propagation times are observed.

The logic gates built were the inverter (INV), NAND, NOR, XOR, AND and OR. The
gates were implemented using the generic Pull-Up- and Pull-Down-Network with a 0.5V power
supply. Parasitic capacitances of the gates were estimated and included in the models. The gates
were then simulated.

3.1.2 CNT

Current use and application of nanotubes has mostly been limited to the use of bulk
nanotubes, which is a mass of rather unorganized fragments of nanotubes. Bulk nanotube
materials may never achieve a tensile strength similar to that of individual tubes, but such
composites may, nevertheless, yield strengths sufficient for many applications. Bulk carbon
nanotubes have already been used as composite fibers in polymers to improve the mechanical,
thermal and electrical properties of the bulk product.

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➢ Easton-Bell Sports, Inc. have been in partnership with Zyvex Performance Materials,
using CNT technology in a number of their bicycle components—including flat and riser
handlebars, cranks, forks, seat posts, stems and aero bars.

➢ Zyvex Technologies has also built a 54' maritime vessel, the Piranha Unmanned Surface
Vessel, as a technology demonstrator for what is possible using CNT technology. CNTs
help improve the structural performance of the vessel, resulting in a lightweight 8,000 lb
boat that can carry a payload of 15,000 lb. over a range of 2,500 miles.

➢ Amory Europe Oy manufactures Hybtonite carbon Nano epoxy resins where carbon
nanotubes have been chemically activated to bond to epoxy, resulting in a composite
material that is 20% to 30% stronger than other composite materials. It has been used for
wind turbines, marine paints and variety of sports gear such as skis, ice hockey sticks,
baseball bats, hunting arrows, and surfboards.

Other current applications include:

➢ Tips for atomic force microscope probes

➢ In tissue engineering, carbon nanotubes can act as scaffolding for bone growth

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3.2 MEMORY

Memory storage

Electronic memory designs in the past have largely relied on the formation of transistors.
However, research into crossbar switch based electronics have offered an alternative using
reconfigurable interconnections between vertical and horizontal wiring arrays to create ultra-
high-density memories. Two leaders in this area are Nantero which has developed a carbon
nanotube based crossbar memory called Nano-RAM and Hewlett-Packard which has proposed
the use of memristor material as a future replacement of Flash memory

An example of such novel devices is based on spintronics. The dependence of the

resistance of a material (due to the spin of the electrons) on an external field is
called magnetoresistance. This effect can be significantly amplified (GMR - Giant Magneto-
Resistance) for nanosized objects, for example when two ferromagnetic layers are separated by a
nonmagnetic layer, which is several nanometers thick (e.g., Co-Cu-Co). The GMR effect has led
to a strong increase in the data storage density of hard disks and made the gigabyte range
possible.

The so-called tunneling magnetoresistance (TMR) is very similar to GMR and based on the spin
dependent tunneling of electrons through adjacent ferromagnetic layers. Both GMR and TMR
effects can be used to create a non-volatile main memory for computers, such as the so-called
magnetic random-access memory or MRAM

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 CHAPTER 4

ADVANTAGES AND DISADVANTAGES OF

NANO ELECTRONICS

4.1 Advantages.

➢ It extends the limits of electronics

Unlike silicon microchips. nanochips will make it possible to build very precise circuits
at an atomic level.

➢ It allows a more effective medicine

Arteries can be unblocked. cells can be selectively attacked; damaged genes can be
repaired and faster and more precise surgeries can be performed.

➢ Promoting renewable energies

It enables new ways to obtain and store energy. It also makes solar panels cheaper and
more efficient.

➢ Cost Effective
Manufacturing and application cost is economical

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 4.2 Disadvantages

❖ It threatens the environment

This type of technology could cause negative effects on the environment by generating
new toxins and pollutants.

❖ It has an impact on the job market

The obsolete materials and changes in production processes

could destroy jobs, but this technology could create others.

❖ It compromises the safety

The properties of this technology could facilitate espionage, the production li. of nano
weapons and smart bullets.

It extends the limits of electronics

Unlike silicon microchips. nanochips will make it possible to build very precise circuits at an atomic level.

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 CHAPTER 5:

FUTURE SCOPE

5.1 FUTURE SCOPE OF NANOELECTRONICS

Nanoelectronics is flourishing its manufacturing day by day scientists are exploring new
characteristics of natural resources with the help of nanoelectronics. Smallest featured integrated
circuit chip which are further inserted into robots are the inventions of nanoelectronics.
Microelectronics is also evolving gradually in the nano electronics which would of great use to
the technological world in the coming future.

Researchers are now predicting that intelligent devices like computers will be assembled in the
future by using molecules which would be the major achievement of nanoelectronics.

We can imagine a future for hybrid devices, combining the strength of both approaches.
In such a scenario, we would use exotic materials for new functions that are needed only at
certain places on a very large-scale circuit that is generated by a conventional semiconductor
process. Newly synthesized nanostructures can also compete in applications where perfection is
not of paramount importance but cheap processing, chemical flexibility, and function are.

Electronic biosensors in which carbon nanotubes or nanowires are used to detect specific
molecules are certainly one of those promising areas, but there may well be others that we have
not imagined yet.

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 CHAPTER 6:

CONCLUSION
Electronics obtained through the bottom-up approach of molecular-level control of
material composition and structure may lead to devices and fabrication strategies not possible
with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-
up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar
motif.

First, we discussed representative electromechanical and resistance-change memory

devices based on carbon nanotube and core-shell nanowire structures, respectively. These device
structures show robust switching, promising performance metrics and the potential for terabit-
scale density.

Second, we will revied architectures being developed for circuit-level integration, hybrid
crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key
concepts such lithography-independent, chemically coded stochastic demultiplexer’s. Finally,
bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional,
vertically integrated multifunctional circuits

Page 25
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 CONTENTS:

TOPIC Page no.

1.Introduction of Nano Electronics 1-5

1.1 What is Nano Electronics 2

1.2 Why Nano 2

1.3 Approaches in Nano Electronics 3-5

1.3.1 Bottom Up 3-4

1.3.2 Top Down 4-5

2.Literature 6-18

2.1 Bottom /Core Devices in Nano Electronics 6-10

2.1.1 Carbon Nano Tubes (CNT’s) 6

2.1.2 Electrical Properties 7

2.1.3 Fabrication of carbon Nano Tubes 8-10

2.2 S.I. Nano Dots 11-13

2.2.1 Fabrication of SI Nano Dots 12

2.2.2Electrical Properties 13

2.3 Nano Wires 14-18

2.3.1 Fabrication of Nano Wires 15-17

2.3.2 Electrical Properties 18

3.Architecture 19-21

3.1 Application Built using Bottom Devices 19-20

3.1.1 CNFET 19

3.1.2 CNT 19

3.2 Memories 21

4.Advantanges and Disadvantages of Nano Electronics 22-23

4.1 Advantages 22

4.2 Disadvantages 23

5. Future Scope 24

6. Conclusion 25

7.References 26