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Assignment 1

1. The document describes three assignments for a VLSI design course. The first assignment involves designing an inverter with a symmetric VTC curve and analyzing its characteristics for different Kn/Kp values. The second analyzes driving current for different Kn/Kp values. The third involves designing a CMOS logic circuit for the expression Y=A'B'+CD and analyzing its input-output characteristics. 2. For the first assignment, the student simulated an inverter for Kn/Kp values of 0.3, 0.5, 1, 3, and 5. Metrics like switching threshold, VOH, VOL, VIL, and VIH were calculated and average equivalent resistances of PUN and

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Yatharth Anand
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103 views

Assignment 1

1. The document describes three assignments for a VLSI design course. The first assignment involves designing an inverter with a symmetric VTC curve and analyzing its characteristics for different Kn/Kp values. The second analyzes driving current for different Kn/Kp values. The third involves designing a CMOS logic circuit for the expression Y=A'B'+CD and analyzing its input-output characteristics. 2. For the first assignment, the student simulated an inverter for Kn/Kp values of 0.3, 0.5, 1, 3, and 5. Metrics like switching threshold, VOH, VOL, VIL, and VIH were calculated and average equivalent resistances of PUN and

Uploaded by

Yatharth Anand
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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ASSIGNMENT 1

COURSE NO.: MEL G621


COURSE TITLE: VLSI DESIGN

NAME: SARTHAK SRIVASTAVA


STUDENT ID: 2022H1400071G

AIM

1. Design an inverter with symmetric VTC curve. Plot the VTC curves for different
Kn/Kp values of 0.3, 0.5, 1, 3, 5. Find out he switching threshold, VOH, VOL, VIL and
VIH for each cases. Also, find the average equivalent resistance for PUN and PDN for
each cases using the simulation.
Find out the dealy for L to H and H to L transitions of input for KN/KP=0.3, 1, 5.

2. Find the dc driving current for each cases as give below. Sizes of all the nMOS
transistor are same and input voltage is VDD/2. Explain why the driving current is
different for each cases.

3. Design the CMOS logic circuit and simulate in cadence for the below logical
expression. The driving strength must be equal to the inverter of size 1x. Show the
input-output transient characteristics.
Y=A’B’ + CD

SOLUTION FOR QUES 1

CIRCUIT DIAGRAM
PART 1: PLOTTING THE VTC CURVE AND FINDING THE VALUES OF
SWITCHING THRESHOLD, VOH, VOL, VIL, VIH FOR DIFEERENT
VALUES OF KN/KP.

Hence,The cicuit has been appropriately designed and run for different values of
Kn/Kp i.e. different values of x(say).

 For x=0.3

VOH=1.59538V, VIL=.0.8889V
VIH=1.19385V, VOL=0.44314V

Switching Threshold=956.085mv

 FOR x=0.5
VOH=1.60339V,VIL=800.822

VOL=66.4643mV, VIH= 1.09918V


SWITCHING THRESHOLD= 924.586mV

 FOR x=1

VOH=1.63602V, VIL=668.864mV
VOL=69.4448mV, VIH=998.123mV

SWITCHING THRESHOLD= 825.547mV

FOR x=3
VOH=1.67248V,VIL=475.456

VOL=60.085mV, VIH=796.419mV
SWITCHING THRESHOLD=645.579mV

FOR x=5

VOH= 1.67888V, VIL=425.39mV


VOL=49.7203mV, VIH= 735.863mV

SWWITCHING THRESHOLD=567.898mV

PART 2 OF SOLUTION 1
FINDING AVERAGE EQUIVALENT RESISTANCE OF PUN AND PDN FOR
EACH CASE.
The value of Gds has been calculated for each of the cases
FOR x=0.3

FOR x= 0.5
FOR x=1

FOR x=3
FOR x=5

Finding Gds for Pull Up Network


CALCULATING THE RESISTANCE

PART 3 OF SOLUTION 1
CALCULATION OF DELAY for ‘L to H’ and ‘H to L’ for different values of x

NOTE: The value of delay for L to H and H to L have been shown on same calculator
result screen adjusant to each other.
FOR x=0.3

FOR x=1
FOR x=5

SOLUTION FOR QUES NO. 2

CIRCUIT
OUTPUT PLOT
EXPLANATION FOR THE VARIATION IN DRAIN CURRENT:
SOLUTION FOR QUES NO. 3

CIRCUIT DIAGRAM

OUTPUT WAVEFORM

The result are quite very evident from the above output waveform. The output
changes as per the logic
Y= A’B’+CD

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