ABSTRACT

In order to do this project, a Flash Analog to Digital Converter is needed. The resistive ladder
network, comparators, thermometer to binary encoder attempt to compensate the projected
Flash ADC. For this sake ELECTRONIC DESIGN AUTOMATION (EDA) Tanner tools have
been used during the construction of the circuit, which make use of 180nanometers technology.
The resistive ladder network which have 1.8 V of reference voltage applied to it. Within the
flash ADC, the comparator is a two-stage functional amplifier. Binary code is received from
the thermometer code with the aid of utilising a priority encoder. The primary issue with flash
ADC is that as the resolutions bit count rises, the area of the circuit as well as its power
consumption rise. Through optimising the encoder circuitry, we particularly designed to reduce
the ADC's propagation delay in this project. In order to avoid tranquilly, an encoder is enforced
using a 2:1 multiplexer constructed by domino sense. Parameters of the Flash ADC's
performance, such delay and average power, are determined and compared.

Keywords: Flash ADC, Domino logic, 2:1 Multiplexer based encoder.

 CONTENTS
SL NO. PARTICULARS PAGE NO.

1. INTRODUCTION 01

2. LITERATURE SURVEY 05

3. METHODOLOGY 07

3.1 EXISTING METHOD 07

3.1.1 Flash ADC Architecture 08

3.1.2 Ladder network with resistance 09

3.1.3 Employing an operational amplifier as a comparator 09

3.1.4 The design of a thermometer to binary code encoder 10

3.2 PROPOSED METHOD 11

3.2.1 THE DOMINO LOGIC 12

3.2.2 Domino Logic-based MUX 12

4. SOFTWARE REQUIREMENTS 14

4.1 MODELLING APPARATUS 14

5. SIMULATION RESULT 16

6. ADVANTAGES AND APPLICATIONS 19

7. CONCLUSION 20

REFERENCES 21
 LIST OF FIGURES

SL NO. FIGURES PAGE NO.

Fig 3.1 Circuit of Flash ADC 08

Fig 3.2 Resistive Ladder Network 08

Fig 3.3 Comparator block diagram 09

Fig 3.4 Block schematic for a two-stage Op-Amp 09

Fig 3.5 Encoder Configuration Employing 2:1 Multiplexer 10

Fig 3.6 Transmission gate utilised for Mux (Switch Logic) 11

Fig 3.7 Block Diagram of Domino Logic 12

Fig 3.8 2:1 MUX Using Domino Logic 12

Fig 3.9 Schematic Of 2:1 MUX Using Domino Logic 13

Fig 5.1 Schematic Of Flash ADC 16

Fig 5.2 Mux Based Encoder Using Domino Logic 17

Fig 5.3 Output Waveforms Of Flash ADC 17

LIST OF TABLE

SL NO. TABLE PAGE NO.

Table 5.1 Comparison of Flash ADC between different 17

MUX based encoders

 DESIGN OF HIGH PERFORMANCE FLASH ADC USING DOMINO LOGIC

CHAPTER 1

INTRODUCTION
The fast development of science and technology has led to significant advancements in digital
signal processing. Presently larger part of domains in digital, signal processor has a number of
benefits, including design and programmability flexibility, decreased silicon space, high
precision, and a lesser level of power usage, as well. The design process is quicker and more
affordable. So it is feasible to create a system that has high speed and little area. In wireless
communication, picture processing, etc., an analog to digital converter that gives substantially
better speed is necessary.[2]

Reducing the characteristic sizes, supply voltages, and transistor channel lengths makes it more
difficult to construct analogue circuits. Op amps may readily back and forth of all performance
characteristics, including gain, phase, phase margin, unity gain bandwidth, etc. By adjusting
the width and length of the transistors to be in the saturation area, the design may be
implemented with a variety of aspect ratios and provide improved performance.

The use of portable, long-lasting battery digital systems is advocated by creating applications
with lower power requirements is the only way to do this. In the vast majority of mixed-signal
systems, ADCs serve as front-end components, our main goal was to create an ADC with a
lower power need, which provides a faster response time. Different ADC architectural types
exist, including successive approximation ADCs, Flash ADCs, sigma-delta designs, etc. These
ADCs are used in processors where bandwidth will be in broad range and high speed are
needed. Flash ADC is chosen among them because it delivers high speed due to its collateral
design, the processing time is not restricted by resolution.

In today's digital age, analog-to-digital converters are a vital technology with a wide range of
applications. Compared to conventional ADCs, the flash converter is a high-speed converter.
It comprises of 2N comparators that provide output that is thermometer-coded and is then
translated by an encoder to a digital output. Comparator is crucial for high-speed applications
employing minimization techniques in high-speed ADCs. The primary drawback of flash type
ADC is that it consumes a lot of power, hence low power flash type ADC and low power
comparator design is the goal. Gain, phase, gain bandwidth, resolution, speed, area, and power
dissipation are the design-related concerns. As a high gain comparator, a straightforward two
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stage op-amp with miller capacitance can be utilised. It is simple to use when the electricity is
low.

1.1 ADC

A digital signal is created by converting an analogue signal using an analog to digital converter.
A binary code is concatenation of bits 0 and is used to represent the digital signal.

ADCs come in two varieties: Direct type ADCs and Indirect type ADCs.

A direct type ADC is one that converts analog signals directly to digital signals by using
internally produced equivalent digital (binary) code to compare with the analogue input.

Here are some instances of ADCs of the Direct form:

• Counter ADC
• Successive Approximation ADC
• Flash ADC

ADCs are classified as being of the indirect kind if they convert analogue signals into digital
signals in this way. Generally speaking, it first transforms the analog input into a linear function
of time (or frequency) before producing the digital (binary) output.

The finest instance of an ADC of the indirect variety is the dual slope ADC.

1.2 Flash type ADC

For a comparable analogue input, a flash ADC quickly generates an analogous digital output.
As a result, the flash type ADC is the quickest ADC. Including a voltage divider network, seven
comparators, and a priority encoder, the 3-bit flash type ADC has these components.

1.3 Following are the steps involved in operating a 3-bit flash type ADC:

The eight identical resistors make up the voltage divider network. Over the course of the
network as a whole, a reference voltage VR is applied in relation to the ground. The integer
multiples from 1 to 8 will represent the voltage drop thoroughly top to bottom across each
resistor with respect to ground. The voltage originating from outside. The positive input
terminal of every comparator receives the application of Vi. When supplied to the negative
input terminal of comparators, the voltage drop across each resistor from top to bottom with

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respect to ground is measured. Each comparator performs comparison processes

simultaneously. As far as vi is greater than the voltage drop existing at the corresponding other
input point, the comparator provides a value of "1" as its output. In a way similar, the
comparator's outcome will be"0" when Vi is lower than or equal to the voltage drop existing at
the corresponding other input point. The priority encoder receives an input from all of the
comparator outputs. The binary code (digital output) that this priority encoder generates
corresponds to the high priority input that has a value of 1. Consequently, the double
counterpart of the external analog input voltage, vi, is all that is produced by the priority
encoder.

The flash ADC is employed to the situations spots a rapid transformation rate from analog input
to digital data is required.

1.4 The Two Stage Op-amp:

The differential stage of the operational-amplifier is composed of transistors M1, M2, M3, and
M4. The differential inputs of the amplifier are created by the two M1 and M2 nMOS
transistors. In terms of the transistors, the gates M1 and M2 are the inverting and non-inverting
inputs, respectively. The principal resistances that affect the output are those of the input
transistors and the M3 and M4 active load transistors. The use of existing reflection active load
transistors M3 and M4 has advantages since the load enhances common mode rejection ratio
while the current mirror can support in converting input signals from differential to single-
ended. The present of M1 and M3 are identical because M1 is reflected by M3, and the current
of M2 and M4 are also equal since M4 subtracts the current from M2. The second stage, which
was a current sink load inverter, is made up of the transistors M6 and M7. The common source
arrangement, that amplifies the output of M2's drain through M6, is used. In addition, four
transistors were used to achieve the op-biasing. amp's The bias string controls transistors M5
and M8, which drain a specific quantity of current dependent on the gate to source voltage. The
first stage's output is coupled to a compensation capacitor (CC). Its purpose was to lower the
dominating pole's frequency and shift the output pole farther from the origin. A load capacitor
is being fixed to the op-amp's outputs.

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1.5 Encoder:

Performing the opposite of a decoder, an encoder is a combinational circuit. It can have up to

N output lines are obtained when 2N inputs are given. Generation of binary code takes place
which is idenctical to the input lines, actively high. As a consequence , the encoder uses N bits
to encrypt 2N incoming lines. The enabling signal may or may not be represented in encoders.

1.6 Priority Encoder:

Priority Encoders turn all of their data inputs into equivalent binary codes at their output by
processing each one of them individually.

1.7 The Domino Logic:

The Domino logic family is used in a broad range of applications, including those requiring
microprocessors, dynamic memory, digital signal processors, and other devices with low
transistor counts and high operating speeds. CMOS-based dynamic logic systems that employ
either p-MOS or n-MOS for the pull down or pull up network have evolved into domino logic.
Domino logic is used to create complete adders, which uses less transistors than traditional
CMOS logic while still producing high-performance devices.

1.8 Problem Statement:

• By a Mux-based encoder to create a two-stage opamp and a flash ADC.

• Mux is created utilising PTL & CMOS logics.
• When employing PTL logic, a buffer is necessary to get better results because power
dissipation is higher in cmos logic.

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CHAPTER 2

LITERATURE REVIEW
[1] This attracted significant research a Flash Analog to Digital Converter with a 3-bit range.
The thermometer to binary encoder, comparators, and a resistive ladder network make up the
proposed Flash ADC. This study proposes the lower power op-amp that differs from the
conventional one’s as well as encoder that splashes full adders and pass transistor logic gates.
The work is carried out by LT spice software tool.

[2] Due to its suitability for a wide variety of applications, Adc’s plays vital part in the
computerised world of today. Although Flash Analog to Digital Converter is the quickest ADC
currently in use, which has a very high energy consumption. In order to increase the electric
grid of top speed, medium resolution flash ADCs, this research proposes to establish a super
low design philosophy. By lowering the power level, a digitized system's power consumption
can be reduced, but unless the time duration is increased. Thus, a flash ADC working at
extraordinarily low voltage (ELV) employing 45nm CMOS technology is developed using a
voltage enhancing oriented comparator with the forward body biasing path. Since this supplied
voltage is lower using this way, the delay time is kept almost consistent, which lowers the
capability usage. The offsetting compensating methodology allows use of body-bias
calibrating.

[3] Under this work, a 3-bit flash Adc is constructed using threshold inverter quantization
(TIQ). The key advantage of this method over previous Flash ADC implementations is the lack
of biggest distinction voltage power supply. The changing voltage of the generator may be
regulated via selecting PMOS and nmos transistors with the right breadth to height ratios. Such
framework provides a thermometer, a binary encoder, a gain booster, and a TIQ comparator.
The comparative Region's measurements have changed as a result.

[4] The speedy of Adc is the Flash Adc hence called as parallel Adc. For the applications
acquiring greater bandwidth it acts as an exemplar. The designed circuits involves resistor
ladder, comparator and an encoder circuit. The outcomes of the comparator is in the form of
thermometer code. This have to be converted to respective binary code by utilizing the suitable
encoder. To reduce the energy dissipation is the crucial concern to design low power Flash
Adc.
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[5] Sonu Kumar and Anjali Sharma suggested a method for creating opamps that makes use of
complimentary metal oxide semiconductor process. Resulting in reduced constant electricity
consumption and strong noise resistance of CMOS chips, they chose this technology to
construct an operational amplifier. With a strength of 44.98dB, a phases margins of 63 degree
courses, a gain-bandwidth product of 33.4MHz, and an electricity usage of 276W, the
performance parameters of a two-stage operational amplifier are established.

[6] Analog-to-digital converter emerged as totally vital section of electronics within side the
contemporary virtual global as they consists of huge sort of beneficiaries. Amid wholly the
analog-to-digital converters available, the Flash ADC is one of the expedicious ADC however
a prime disadvantage of this Analog-to-digital converter is its electricity consumption. So, the
principle goal of this work is to put in force a excessive pace low electricity Flash ADC. A
layout with 3-bit decision has been carried out the use of seven OTA primarily based totally
comparators with a corresponding voltage of 250mV and excessive pace encoder were carried
out the use of 4 complete adders upon which the combination of various block ADC has been
designed. All the circuits are simulated the use of 180nm era in Cadence Virtuoso Design
environment. The deliver voltage is 1.8v. Analog output of every comparator relying upon the
contrast among the enter and the reference voltage is fed to the encoder and ultimately the
compressed virtual output is obtained.

[7] This work describes that Adc is being built in the 28nanometer low power digital CMOS
which helps in enlarging the circuit designed. The circuit was designed with the goal of
achieving speed performance above state of the art for a single ADC core. To the extinct the
Adc has the capability of consigning the samples without any overlay, that makes more reliable.
The conferred ADC entitles towering samples which leads to the more beneficiary.

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CHAPTER 3

METHODOLOGY

3.1 EXISTING METHOD

Since science and technology have developed so quickly, digital signal processing has made
tremendous strides. Signal processing has a number of benefits in most digital areas decreased
silicon area, excellent precision, design and programming freedom, moreover a lower quantity
of power usage. Easier and more affordable, the design process. As a result, a system that is
both fast and small may be designed. Wireless communication, picture processing, and other
applications all demand an analog to digital converter that gives substantially better speed.

3.1.1 Flash ADC Architecture

In order to create an n-bit flash Adc, 2N-1 comparators are required. The comparator has two
inputs, like to an op-amp, with analog input supplied to the negative input terminal and
corresponding voltage connected to the positive input terminal. A resistive ladder network is
utilised to split comparators. An N-bit resistive ladder network is created using 2N resistors.
Eight resistors will be needed because we implemented 3-bit, thus that's how much. Between
the reference voltage and ground, a resistive ladder network is used to provide a corresponding
voltage that is evenly distributed and differs by the smallest possible amount. Comparator
generates a logic high signal when the indigenous value is less than the incoming data in analog
form and when the analog incoming data is unbefitting the reciprocal reference voltage, it
output a logic low data. The outcome of comparators generates a thermometer code.
Furthermore, binary code transition into thermometer code is required.

The resolution largely determines the result produced. However, the main drawback is as the
resolution rises, the quantity of comparators required will rise. An instance, 511 comparators
are required to construct a 9-bit flash ADC, which takes up a lot of space on the die and
consumes a lot of power. Therefore, as these are key limitations, we require to lower the power
and size of the flash ADC.

Reliability of a flash ADC is not determined by resolution; resolution just reflects the total
number of bits acquired on the direction of outcome.

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Fig 3.1: Circuit of Flash ADC

3.1.2 Ladder network with resistance

In this project, we construct a resistive ladder network-based 3-bit flash ADC. A consistent
reference voltage may be provided to the comparators using the resistance ladder network. To
create an N-bit Flash ADC, 2N resistors are necessary. This ladders cable network main
objective is to equally distribute reference voltage across all resistors so that the least
significant bit value will result from the reference voltage variations between the two matching
comparators. Currently 1.8 volts has been used as the reference voltage.

Fig: 3.2 Resistive Ladder Network

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3.1.3 Employing an operational amplifier as a comparator

The outcome will appear like what has been displayed below after correlating the supplied
incoming signal to the reference signal.

Fig 3.3: Comparator block diagram

Fig 3.4: Block schematic for a two-stage Op-Amp

A block architecture of the two-stage op-amp can be seen in the previous Figure 3. A common
source gain phase starts after a differential voltage gain stage inside this device. Besides the
M2 transistor, the M1 transistor has been used to connect the differential inputs. To guarantee
that every transistor is in saturation, the transistors M5 and M8 are equipped with biasing. The
transistors M3 and M4 together form a current source that projects Current from transistor M1
is added to transistor M2, then deducted. In the occasion that an adequate gain can indeed be
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attained during the differential phase, we employ a Transistors M6 and M7 work together to
produce a common source amplifier, which is the gain stage.

3.1.4 The design of a thermometer to binary code encoder

Perspective approaches to transfer thermometer code to binary code. The result of the
comparators leads to the identification "thermometer code", including an increase in value, it
seems to be a thermometer reading. Likewise to how well the temperature rises as the
temperature rises, the frequency of ones keeps on growing. To transfer thermometer code into
binary code, there are also several types of encoders, such like Wallace tree encoder, ROM
encoder, xor and multiplexer-based encoder designs are examples of encoders. There are
benefits and drawbacks to all these encoders. The basic logic that governs Mux-designed
encoders is that the MSB in binary format could be peak if partly the thermometer code
represents logic 1. The binary output's MSB is represented by the value 2n-1. In terms of
determining the next binary outcome, this thermometer code is ever more divided into two
codes. a particular moment of the second line The technique is repeated until the last 2:1 mux
is completed, at which point is the less important binary’s bit output is acquired. Effectively
created encoder employing this 2:1 multiplexer with minimal space and power usage, even if
resolution improves.

Fig 3.5: Encoder Configuration Employing 2:1 Multiplexer

Rather than using CMOS logic and pass transistor logic, the MUX in this scenario is
implemented with transmission gates.

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Fig 3.6: Transmission gate utilised for Mux (Switch Logic)

Owing to the CMOS transmission gate used for mux implementation, less transistors were
being used, which yielded in lowered power consumption, fast speed, and lowered area.

Disadvantage:

Here the output is unstable so we are going to use domino logic.

3.2 PROPOSED METHOD

Even though the Domino logic is an improvement beyond dynamic logic, it suffers when gates
are concatenated one after the other. To overcome the flaw of dynamic logic, static inverter is
being used by domino logic in the middle of two phases. Domino logic has a number of benefits
over traditional CMOS logic, including a decreased space need. Since parasitic capacitance is
lower in domino logic, it operates at a high speed and produces error-free results since each
gate only conducts one transition.

Instead of using static logic, the domino logic technique is typically utilised to construct high
performance circuits. Full adders are given a lot of attention by academics since they serve as
a fundamental component for multipliers, comparators, and parity checkers in arithmetic
operations.

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3.2.1 THE DOMINO LOGIC

Fig 3.7: Block diagram of Domino logic

The two levels of operation in Domino logic are pre-charging and evaluation. As demonstrated,
PMOS will switch on when clock 'clk' is equal to low and pre-charged output node to Vdd. The
evaluation phase takes place when the clk switches to the high position, turning off the p-MOS.
The outcome in this segment will be influenced by the setup of the input. Inputs must have a
direct connection to ground in addition for the output node to discharge; otherwise, it will
continue to be high. As a result, the circuit's desired outcome, which was to be used solely
during the assessment phase, is acquired. Due to the usage of an inverter in this logic kind for
splashing the next stage, it will have a low outcome during the pre-charge phase.

3.2.2 Domino Logic-based MUX:

Fig 3.8: 2:1 MUX using domino logic

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Fig 3.9: Schematic of 2:1 MUX using domino logic

Solution obtained from this proposed work is To achieve better performance in this paper, here,
we are implementing flash ADC by designing MUX in Domino logic. In Domino logic, the
circuit is controlled by Clock input.

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CHAPTER 4

SOFTWARE REQUIREMENTS
The software used is EDA TANNER TOOL.

An integrated circuit design toolkit called Tanner EDA is available. Through the use of these
tools, you may enter schematics, run SPICE simulations, create physical designs (such as chip
layouts), and carry out design rule checks (DRC) and layout versus schematic (LVS)
evaluations. Tanner Designer is an instrument for analogue verification that keeps track of
every simulation for a project. The tool allows the team to quickly see which blocks pass or
fail specifications and to track the status of verification by displaying simulation results in an
easy-to-use dashboard. S-Edit, Analog Fast SPICE (AFS), T-Spice, Eldo, and the Tanner
Waveform Viewer are all completely integrated within the programme.

4.1 MODELING APPARATUS

Tanner EDA tool version 13.0 has been utilised throughout the whole study project for
simulation purposes. The following is a description of this tool's attributes and capabilities:

There is a crucial pre-fabrication verification step in the design cycle for creating electronic
circuits. Accurate verification is essential to effective design since the manufacturing process
is expensive and under schedule and budget constraints. By numerically resolving the
differential equations characterising the circuit, an EDA tool aids in the design and operation
verification of a circuit. Before submitting designs for production, circuit designers can validate
and refine them using the results of the simulation. Tanner EDA tool is a full-featured circuit
design and analysis solution that includes:

• S-Edit : A Schematic Editor which helps in capturing robustic design and analysis tool that
produces netlists which used directly in T-Spice simulations.

• T-Spice: A circuit simulator which simulates mixed analog/digital and analog circuits rapidly
and precisely. The simulator features linked line models, the most recent and finest device
models on the market, as well as support for user-defined device models through C functions
or tables. All commercially available SPICE simulation programmes are compatible with T-
enhanced Spice's SPICE input language. Along with analog devices and the whole set of the

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most recent sophisticated semiconductor device models from Berkeley and Philips Labs, all of
the SPICE's device models are included.

• W-Edit: Waveform-Editor shows waveforms produced by T-Spice simulations as they are

generated. Testing, comprehending, and upgrading VLSI circuits depend on the ability to
visualise the intricate numerical data produced by those simulations. A waveform viewer called
W-Edit offers simplicity, strength, and rate in a versatile setting intended to visual information
display.

• L-Edit: A Layout-editor present in the Electronic Design Automation tool which helps in
layout editing, Interactive DRC for in-process design rule verification, Standard DRC for
hierarchical DRC, Standard Extract for netlist extraction, and Standard LVS for layout versus
schematic. In addition to SPR for regular cell place & route, Node Highlighting highlights any
geometry related to a node.

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CHAPTER 5

SIMULATION RESULT

Fig 5.1: Schematic of flash ADC

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Fig 5.2: Mux based encoder using domino Logic

Fig 5.3: Output waveforms of flash ADC

S.No CMOS MUX PTL MUX SL MUX DOMINO

MUX
Power (W) 1.942 X 10-4 1.941 X 10-4 1.9538 X 10-4 1.942 X 10-4
Area 108 68 84 96
Delay 8.976µs 8.689µs 0.4µs 2.613µs

Table 5.1: Comparison of Flash ADC between different MUX based encoders

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Table 5.1 describes the comparison of performance parameters such as Area, Delay and Power
between MUX based encoders for Flash ADC.
• From these results, we can conclude that the power dissipation and area is reduced PTL
MUX but the delay is more. The delay is less in SL MUX but power dissipation is more.
• In DOMINO MUX, the power is approximately similar to CMOS MUX whereas the
area is more compared to PTL and SL based MUX, the delay is less compared to CMOS
as well as PTL based MUX.
• On comparing Flash ADC, with all these MUX based encoder, it is proven that the
Domino Logic MUX based encoder utilizing Flash ADC has achieved better overall
performance than the other Flash ADC.

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CHAPTER 6
ADVANTAGES & APPLICATIONS
Advantages:

• Area reduction due to 2:1 mux implementation with domino logic.

• High speed is being achieved.

Applications

• Circuits with very broad band

• Communications using optics
• Additionally, due to the simplicity of circuit, this project of designed flash Analog to
Digital converter may be enlarged to support medium-to-high resolution applications.

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CHAPTER 7

CONCLUSION
In this project, we employ domino logic to construct flash ADC. Utilizing the Tanner tool and
modelling files for 180nm technology, 3-bit flash ADC design and simulation are
accomplished. Calculations and comparisons are made for variables like converting time and
average power of 3-bit flash ADC. By enhancing the encoder circuitry, we mainly concentrated
on reducing the 3-bit flash ADC propagation time. Utilizing domino logic, we have constructed
a 2:1 multiplexer based encoder. Less latency be offered by a 3-bit Flash ADC that is
constructed by utilizing an encoder and a 2:1 mux.

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REFERENCES
[1] Pabba Sowmya, Mamatha Samson, Mohd Javeed Mehdi. "Design of Two Stage
Operational Amplifier and Implementation of Flash ADC" , 2021 Third International
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(ICICV), 2021
[2] Glyny George, A. V. Jos Prakash, “Design of ultra-low voltage high speed flash ADC in
45nm CMOS Technology”, IEEE Conference on recent trends in electronics, Information
&communication technology, 2018.
[3] Al-Ahsan Talukder, Md. ShamimSarker, “A three-bit threshold inverter quantization
based CMOS flash ADC”, 2017 4th International Conference on Advances in Electrical
Engineering, 2017.
[4] M.P. Ajanya, George Tom, “ Thermometer code to binary code converter for flash ADC
–A Review”, ICCPCCT, 2018.
[5] Sonu Kumar, Anjali Sharma, “Design of CMOS operational amplifier in 180nm
technology", International journal of innovative research in computer and communication
engineering Vol.5, issue 4, April 2017.
[6] MirzaNemath Ali Baig, RakeshRanjan, “ Design and implementation of 3-bit High-speed
flash ADC for wireless LAN Applications”, IJARCCE, Vol 6, 2017.
[7] G. Tretter, M. Khafaji, D. Fritsche, C. Carta and F. Ellinger, "A 24 GS/s single-core flash
ADC with 3 bit resolution in 28 nm low-power digital CMOS," 2015 IEEE Radio
Frequency Integrated Circuits Symposium (RFIC), 2015, pp. 347-350.

Dept of ECE, VLSI and Embedded system

Sharnbasva University, Kalaburagi 21 | P a g e
 Ref : IJSRST/Certificate/Volume 9/Issue 4/9867 20-Jul-2022

This is to certify that Keerti Sangappa has published a research paper entitled 'Design of High-Performance Flash ADC
Using Domino Logic' in the International Journal of Scientific Research in Science and Technology (IJSRST), Volume 9, Issue
4, July-August-2022 .

This Paper can be downloaded from the following IJSRST website link
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IJSRST Team wishes all the best for bright future
 International Journal of Scientific Research in Science and Technology
Print ISSN: 2395-6011 | Online ISSN: 2395-602X (www.ijsrst.com)
doi : https://doi.org/10.32628/IJSRST

Design of High-Performance Flash ADC Using Domino Logic

Keerti Sangappa
M. Tech Scholar, Department of ECE (VLSI & EMBEDDED SYSTEM), Sharnbasva University, Kalaburagi, India

ABSTRACT
Article Info In this paper, Flash Analog to digital converter is implemented. The designed
Volume 9, Issue 4 Flash ADC consists of a resistive ladder network, comparators, the
Page Number : 266-271 thermometer to a binary encoder and the entire design is carried out using
Tanner tools employing 180nm technology. The reference voltage applied to
Publication Issue the resistive ladder network is 1.8V. A two-stage operational amplifier is used
July-August 2022 as a comparator in the flash ADC. Binary code is obtained from the
thermometer code by utilizing a priority encoder. The major problem that
Article History usually appears in flash ADC is as the number of resolution bits increases, the
Accepted : 05 July 2022 Area, as well as the power consumption of the circuit, also increases. In this
Published : 20 July 2022 paper, we principally concentrated to lessen the propagation delay of the ADC
by optimizing encoder circuitry. With the purpose of reducing latency,
Encoder is implemented using 2:1 mux based on domino logic. Performance
parameters of Flash ADC such as delay as well as average power are calculated
and compared.
Keywords: Flash ADC, Domino Logic, Mux Based Encoder.

I. INTRODUCTION In last few years the largest portion of electronics

industry is dominated by MOS market. It becomes a
Digital signal processing has advanced intensely due challenging to design analog circuit reducing its
to the rapid expansion of science and technology. In feature sizes, supply voltages as well as transistor
the majority of the digital domains, signal processing channel length. Op amp can easily trade-off between
offers several advantages such as flexibility in design all performance parameters like gain, phase, phase
and programmability, reduced silicon area, high margin, unity gain bandwidth etc. The design can be
accuracy, as well as a smaller amount of power achieved handling various aspect ratios i.e changing
consumption. The design process is cost-effective and width and length of transistors to be in saturation
faster. Hence it is possible to design a system with a region so that it can give better performance. It is
lesser area along with high speed. It is required to preferred to have digital systems that are portable and
have an analog to digital converter that offers much have prolonged battery life. This can be only possible
higher speed in wireless communication, image by developing applications that consume less power.
processing, etc. [1] Since ADC s act as front-end components in the
majority of mixed-signal systems, we focused to

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 Keerti Sangappa Int J Sci Res Sci & Technol. July-August 2022, 9 (4) : 266-271

design ADC that consumes less power which in turn lesser no. of transistors as if compared to conventional
offers higher speed. We have various types of ADC CMOS logic and provides high performance device.
architectures for instance successive approximation
type ADC, Flash type, sigma-delta, etc. Among these
Flash ADC is preferred since it offers high speed
because of its parallel architecture, the conversion
time is not limited by resolution hence these ADC s
are utilized in those systems where bandwidth with a
wide range and high speed is required[2].

Mirza Nemeth Ali Baig and Rakesh Ranjan have

implemented high-speed flash ADC for wireless LAN
applications. Seven operational transconductance-
based comparators with a reference voltage of 250mV Figure 1: Block diagram of Domino Logic

are used to construct the planned 3-bit flash Analog to

digital converter, and complete adders are used to II. EARLIER WORK
perform the high-speed encoder. Since ADC is
implemented by utilizing a full adder based encoder, To implement N bit flash ADC, we require 2N-1
the area is limited by the resolution[5]. Sarojini comparators are needed. Similar to op-amp, the

Mandal and J.K.das had implemented a 3-bit flash comparator comprises of two inputs where analog
ADC using cascading full adder by using pass input is given to the inverting terminal and reference

transistor logic that makes the circuit much faster. voltage is applied to non-inverting terminal.
They have improved the efficiency of flash ADC by Comparators are divided with the help of the resistive
improving the working of the comparator by scaling ladder network. 2N resistors are utilized to form a

down the length to width ratio of transistors assuming resistive ladder network of N bit. Since we have

transistors operating in the saturation region. A implemented 3-bit, the number of resistors required

complete adder with ten transistors is used to create will be eight. The reference voltage is generated
the encoder circuit. The use of pass transistor logic in across the resistive ladder network between reference

a complete adder circuit reduces the chip s complexity voltage and ground is equally distributed and is
and space. Logic levels will worsen since the entire differed by the least significant bit. The comparator

adder is constructed with a pass transistor [6]. compares the reference voltage signal with the input
analog signal and indicates output as logic high
Domino Logic: whenever analog input exceeds reference voltage and
Domino logic family find a wide variety of application, indicates logic low output when analog input is
where less transistor count and high speed of smaller than reference voltage. The output of

operation such as microprocessor, dynamic memory, comparators forms a thermometer code. Further, we

digital signal processors etc are required. Domino need to translate thermometer code into binary code.

logic is an evolution in CMOS based dynamic logic

techniques which use either p-MOS or n-MOS for the
pull down or pull up network. The methodology of
designing full adder by using Domino logic employs

International Journal of Scientific Research in Science and Technology (www.ijsrst.com) | Volume 9 | Issue 4 267
 Keerti Sangappa Int J Sci Res Sci & Technol. July-August 2022, 9 (4) : 266-271

because the output of the comparators looks like

thermometer reading that is as the value increases the
number of ones goes on increasing same like the
mercury level which increases as temperature
increases. There are different types of encoders to
convert thermometer code into binary code for
instance Wallace tree encoder, encoder design
utilizing mux, and encoder using xor as well as ROM
encoder. Each of these encoders has its own
advantages and disadvantages. Encoder designed using
Figure 2: Circuit of Flash ADC
Mux operates on the simple logic that is if half of the
Operational amplifier as a comparator:
thermometer code represents logic high the most
The applied input signal is compared with the
significant bit in binary code is also high. The value
reference signal and will provide output as shown
corresponding to 2n-1 represents MSB in the binary
below.
output. Again this thermometer code is classified into
two codes to find next binary output. A select line of
the second stage Mux is obtained from the preceding
stage mux output. The procedure is continued till the
end of the last 2:1 mux and the least significant bit of
binary output is obtained. Even if resolution increases
we can implement an encoder using this 2:1 mux
easily with less area and less power consumption.

Figure 3: Block diagram of Two stage Op-Amp

The above fig.3 shows a block diagram of the two-
stage op-amp. It consists of a differential voltage gain
stage followed by a common source gain stage.
Differential inputs are applied through the M1
transistor along with the M2 transistor. Op-amp
Biasing is furnished with the transistors M5 and M8 to
ensure all transistors in saturation. The current mirror
formed by the transistor M3 and M4 mirrors current
from transistor M1 and is subtracted from the Figure 4 Encoder Implementation using 2:1 MUX
transistor M2. If sufficient gain is not obtained during Here, the MUX is designed with Transmission gates
the differential stage then we use a common source instead of Pass Transistor Logic and CMOS Logic.
amplifier as the gain stage which is formed by
transistors M6 and M7.

Thermometer to binary code encoder design:

Thermometer code can be translated to binary code in
different ways. The name thermometer code is given

International Journal of Scientific Research in Science and Technology (www.ijsrst.com) | Volume 9 | Issue 4 268
 Keerti Sangappa Int J Sci Res Sci & Technol. July-August 2022, 9 (4) : 266-271

have a direct conducting path to ground otherwise it

will remain high. So the output of circuit is obtained
by which it has been intended to design in evaluation
phase only. In pre-charge phase, it will provide low
output because we used an inverter in this logic style
for cascading the next stage.

MUX using Domino Logic:

Figure 5: Mux using Transmission Gate (Switch Logic)

Due to the implementation of mux using CMOS
transmission gate, the number of transistors got
reduced which reduced the power consumption, area
and increases speed.

III. PROPOSED WORK

The Domino logic is an improvement in dynamic
logic which has a drawback when one gate is cascaded
to next. In domino logic, A static inverter is used
Figure 6: Schematics of MUX using Domino logic
between the two stages for removing the drawback of
dynamic logic. There are various advantages of
IV. EXPERIMENTAL RESULTS
Domino logic like they have a smaller area unlike
conventional CMOS logic, parasitic capacitance are
smaller in domino logic so it provide high speed of
operation and result is glitch free because each gate
makes only one transition. Domino logic style is
generally used for designing a high performance
circuit, rather than a static logic style. For arithmetic
operations full adder acts as a basic element for parity
checker, comparator and multiplier, hence it receives
a lot of attention by the researchers.

Domino logic consists of two- stages of operation in

which first stage is pre-charging, and another stage is
evaluation. As shown in fig.1, when clock clk is equal
to zero or low pMOS will be on and it pre-charged
the output node to Vdd. When the clk goes to high, Figure 7: Schematic of proposed Flash ADC
p-MOS will be off and the evaluation phase will start.
In this phase output will depend on the input s
configuration. Output node may discharge if inputs

International Journal of Scientific Research in Science and Technology (www.ijsrst.com) | Volume 9 | Issue 4 269
 Keerti Sangappa Int J Sci Res Sci & Technol. July-August 2022, 9 (4) : 266-271

Figure 7 shows Tanner tool diagram of suggested On comparing Flash ADC, with all these MUX based
Flash ADC employing MUX based encoder in which encoder, it is proven that the Domino Logic MUX
MUX is designed using Domino Logic. based encoder utilizing Flash ADC has achieved
better overall performance than the other Flash ADC.

V. CONCLUSION

We used domino logic in this paper to construct flash

ADC. The Tanner tool, which uses 180nm technology
model files, is used to design and simulate a 3-bit flash
ADC. The average power of a 3-bit flash ADC is
determined and compared. By modifying the encoder
circuitry, we were able to reduce the propagation
Fig 8: Simulation results for proposed Flash ADC latency of the 3-bit flash ADC. We used domino logic
to construct a 2:1 mux encoder. Less delay is achieved
Figure 8 shows the results of waveforms for by using a 3-bit Flash ADC with a 2:1 mux in Domino
recommended Flash ADC using Domino logic Logic.
oriented MUX.
VI. REFERENCES
CMOS PTL SL DOMIN
MUX MUX MUX O MUX [1]. Glyny George, A. V. Jos Prakash, Design of
Power ultra-low voltage high speed flash ADC in 45nm
1.942 1.941 1.9538 1.942
((10-4W) CMOS Technology, IEEE Conference on recent
Area 108 68 84 96 trends in electronics, Information
&communication technology, 2018.
Delay 8.976µs 8.689µs 0.4µs 2.613µs
[2]. S. Veeramachanen, A. M. Kumar, V. Tummala
and M. B. Srinivas, Design of a Low Power,
Table 1 : comparison of Flash ADC between different Variable-Resolution Flash ADC, 2009 22nd
MUX based encoders. International Conference on VLSI Design, New
Delhi, 2009
Table1 describes the comparison of performance [3]. Al-Ahsan Talukder, Md. ShamimSarker, A
parameters such as Area, Delay and Power between three-bit threshold inverter quantization based
MUX based encoders for Flash ADC. CMOS flash ADC , 2017 4th International
Conference on Advances in Electrical
From these results, we conclude that the power Engineering, 2017.
dissipation and area is reduced PTL MUX but the [4]. Sonu Kumar, Anjali Sharma, Design of CMOS
delay is more. The delay is less in SL MUX but power operational amplifier in 180nm technology ,
dissipation is more. In DOMINO MUX, the power is International journal of innovative research in
approximately similar to CMOS MUX whereas the computer and communication engineering
area is more compared to PTL and SL based MUX, the Vol.5, issue 4, April 2017.
delay is less compared to CMOS as well as PTL based [5]. MirzaNemath Ali Baig, RakeshRanjan, Design
MUX. and implementation of 3-bit High-speed flash

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ADC for wireless LAN Applications, IJARCCE,

Vol 6, 2017.
[6]. SarojiniMandal, Dr. J.K Das, Design of 3-bit
low power flash ADC, IJARCET, Volume 3 issue
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[7]. Jayesh J. Vyas, Simulation of 3 bit Flash ADC in
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[8]. Piyush. V. Kanodiya, Amisha. P. Naik, Analysis
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Cite this article as :

Keerti Sangappa, "Design of High-Performance

Flash ADC Using Domino Logic", International
Journal of Scientific Research in Science and
Technology (IJSRST), Online ISSN : 2395-602X,
Print ISSN : 2395-6011, Volume 9 Issue 4, pp.
266-271, July-August 2022.
Journal URL : https://ijsrst.com/IJSRST229442

International Journal of Scientific Research in Science and Technology (www.ijsrst.com) | Volume 9 | Issue 4 271