Introduction to Verilog

Introduction to Verilog 1. Introduction

Table of Contents Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit
(IC) designers. The other one is VHDL.
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
HDL’s allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with
2. Lexical Tokens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 different architectures. Designs described in HDL are technology-independent, easy to design and debug, and are
White Space, Comments, Numbers, Identifiers, Operators, Verilog Keywords usually more readable than schematics, particularly for large circuits.
3. Gate-Level Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Basic Gates, buf, not Gates, Three-State Gates; bufif1, bufif0, notif1, notif0 Verilog can be used to describe designs at four levels of abstraction:
4. Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 (i) Algorithmic level (much like c code with if, case and loop statements).
Value Set, Wire, Reg, Input, Output, Inout (ii) Register transfer level (RTL uses registers connected by Boolean equations).
Integer, Supply0, Supply1 (iii) Gate level (interconnected AND, NOR etc.).
Time, Parameter (iv) Switch level (the switches are MOS transistors inside gates).
5. Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 The language also defines constructs that can be used to control the input and output of simulation.
Arithmetic Operators, Relational Operators, Bit-wise Operators, Logical Operators
Reduction Operators, Shift Operators, Concatenation Operator, More recently Verilog is used as an input for synthesis programs which will generate a gate-level description (a
Conditional Operator: “?” Operator Precedence netlist) for the circuit. Some Verilog constructs are not synthesizable. Also the way the code is written will greatly
6. Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 effect the size and speed of the synthesized circuit. Most readers will want to synthesize their circuits, so nonsynthe-
sizable constructs should be used only for test benches. These are program modules used to generate I/O needed to
Literals, Wires, Regs, and Parameters, Bit-Selects “x[3]” and Part-Selects “x[5:3]”
simulate the rest of the design. The words “not synthesizable” will be used for examples and constructs as needed that
Function Calls
do not synthesize.
7. Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Module Declaration, Continuous Assignment, Module Instantiations,
There are two types of code in most HDLs:
Parameterized Modules
Structural, which is a verbal wiring diagram without storage.
8. Behavioral Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
assign a=b & c | d; /* “|” is a OR */
Procedural Assignments, Delay in Assignment, Blocking and Nonblocking Assignments
assign d = e & (~c);
begin ... end, for Loops, while Loops, forever Loops, repeat,
Here the order of the statements does not matter. Changing e will change a.
disable, if ... else if ... else
case, casex, casez Procedural which is used for circuits with storage, or as a convenient way to write conditional logic.
always @(posedge clk) // Execute the next statement on every rising clock edge.
9. Timing Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
count <= count+1;
Delay Control, Event Control, @, Wait Statement, Intra-Assignment Delay
Procedural code is written like c code and assumes every assignment is stored in memory until over written. For syn-
10. Procedures: Always and Initial Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 thesis, with flip-flop storage, this type of thinking generates too much storage. However people prefer procedural
Always Block, Initial Block code because it is usually much easier to write, for example, if and case statements are only allowed in procedural
11. Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 code. As a result, the synthesizers have been constructed which can recognize certain styles of procedural code as
Function Declaration, Function Return Value, Function Call, Function Rules, Example actually combinational. They generate a flip-flop only for left-hand variables which truly need to be stored. However
12. Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 if you stray from this style, beware. Your synthesis will start to fill with superfluous latches.
13. Component Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Registers, Latches, Flip-flops, Counters, Multiplexers, Adders/Subtracters, Tri-State Buffers This manual introduces the basic and most common Verilog behavioral and gate-level modelling constructs, as
Other Component Inferences well as Verilog compiler directives and system functions. Full description of the language can be found in Cadence
14. Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Verilog-XL Reference Manual and Synopsys HDL Compiler for Verilog Reference Manual. The latter emphasizes
Counters, Shift Registers only those Verilog constructs that are supported for synthesis by the Synopsys Design Compiler synthesis tool.
15. Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Time Scale, Macro Definitions, Include Directive In all examples, Verilog keyword are shown in boldface. Comments are shown in italics.
16. System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
$display, $strobe, $monitor; $time, $stime, $realtime; $reset, $stop, $finish; $deposit; $scope, $showscope;
$list; $random; $dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall; $shm_probe, $shm_open, $fopen,
$fdisplay, $fstrobe, $fmonitor.
17. Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Test Benches, Synchronous Test Benches
18. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Two-dimensional arrays, Initializing memory from a file.

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 Introduction to Verilog Introduction to Verilog

2. Lexical Tokens 3. Gate-Level Modelling

Verilog source text files consists of the following lexical tokens: Primitive logic gates are part of the Verilog language. Two properties can be specified, drive_strength and delay.
Drive_strength specifies the strength at the gate outputs. The strongest output is a direct connection to a source, next
2.1. White Space comes a connection through a conducting transistor, then a resistive pull-up/down. The drive strength is usually not
White spaces separate words and can contain spaces, tabs, new-lines and form feeds. Thus a statement can extend specified, in which case the strengths defaults to strong1 and strong0. Refer to Cadence Verilog-XL Reference Man-
over multiple lines without special continuation characters. ual for more details on strengths.
Delays: If no delay is specified, then the gate has no propagation delay; if two delays are specified, the first represent
2.2. Comments the rise delay, the second the fall delay; if only one delay is specified, then rise and fall are equal. Delays are ignored
Comments can be specified in two ways (exactly the same way as in C/C++): in synthesis. This method of specifying delay is a special case of “Parameterized Modules” on page 11. The parame-
- Begin the comment with double slashes (//). All text between these characters and the end of the line will be ters for the primitive gates have been predefined as delays.
ignored by the Verilog compiler.
- Enclose comments between the characters /* and */. Using this method allows you to continue comments on 3.1. Basic Gates
more than one line. This is good for “commenting out” many lines code, or for very brief in-line comments. These implement the basic logic gates. They have one output and one or more inputs. In the gate instantiation syntax
shown below, GATE stands for one of the keywords and, nand, or, nor, xor, xnor.
Example 2 .1
a = c + d; // this is a simple comment Syntax Example 3 .1
/* however, this comment continues on more GATE (drive_strength) # (delays)
than one line */ instance_name1(output, input_1, and c1 (o, a, b, c, d); // 4-input AND called c1 and
assign y = temp_reg; input_2,..., input_N), c2 (p, f g); // a 2-input AND called c2.
assign x=ABC /* plus its compliment*/ + ABC_ instance_name2(outp,in1, in2,..., inN); or #(4, 3) ig (o, a, b); /* or gate called ig (instance name);
Delays is rise time = 4, fall time = 3 */
#(rise, fall) or xor #(5) xor1 (a, b, c); // a = b XOR c after 5 time units
2.3. Numbers # rise_and_fall or xor (pull1, strong0) #5 (a,b,c); /* Identical gate with pull-up
Number storage is defined as a number of bits, but values can be specified in binary, octal, decimal or hexadecimal #(rise_and_fall) strength pull1 and pull-down strength strong0. */
(See Sect. 6.1. for details on number notation).
Examples are 3’b001, a 3-bit number, 5’d30, (=5’b11110), and 16‘h5ED4, (=16’d24276)
3.2. buf, not Gates
2.4. Identifiers These implement buffers and inverters, respectively. They have one input and one or more outputs. In the gate instan-
Identifiers are user-defined words for variables, function names, module names, block names and instance names. tiation syntax shown below, GATE stands for either the keyword buf or not
Identifiers begin with a letter or underscore (Not with a number or $) and can include any number of letters, digits and
underscores. Identifiers in Verilog are case-sensitive. Syntax Example 3 .2
Syntax Example 2 .2 not #(5) not_1 (a, c); // a = NOT c after 5 time units
GATE (drive_strength) # (delays)
allowed symbols buf c1 (o, p, q, r, in); // 5-output and 2-output buffers
adder // use underscores to make your instance_name1(output_1, output_2,
ABCDE . . . abcdef. . . 1234567890 _$ c2 (p, f g);
by_8_shifter // identifiers more meaningful ..., output_n, input),
not allowed: anything else especially _ABC_ /* is not the same as */ _abc_ instance_name2(out1, out2, ..., outN, in);
- &#@ Read_ // is often used for NOT Read

2.5. Operators 3.3. Three-State Gates; bufif1, bufif0, notif1, notif0

Operators are one, two and sometimes three characters used to perform operations on variables. These implement 3-state buffers and inverters. They propagate z (3-state or high-impedance) if their control signal is
Examples include >, +, ~, &, !=. Operators are described in detail in “Operators” on p. 6. deasserted. These can have three delay specifications: a rise time, a fall time, and a time to go into 3-state.
bufif0 notif0 Example 3 .3
A
2.6. Verilog Keywords En
BUS = Z
bufif0 #(5) not_1 (BUS, A, CTRL); /* BUS = A
En
These are words that have special meaning in Verilog. Some examples are assign, case, while, wire, reg, and, or, CTRL=1
5 time units after CTRL goes low. */
nand, and module. They should not be used as identifiers. Refer to Cadence Verilog-XL Reference Manual for a notif1 #(3,4,6) c1 (bus, a, b, cntr); /* bus goes tri-state
complete listing of Verilog keywords. A number of them will be introduced in this manual. Verilog keywords also bufif1 notif1 6 time units after ctrl goes low. */
includes Compiler Directives (Sect. 15. ) and System Tasks and Functions (Sect. 16. ).
En En

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 Introduction to Verilog Introduction to Verilog

4.5. Integer
4. Data Types Integers are general-purpose variables. For synthesois they are used mainly loops-indicies, parameters, and con-
stants. See“Parameter” on p. 5. They are of implicitly of type reg. However they store data as signed numbers
whereas explicitly declared reg types store them as unsigned. If they hold numbers which are not defined at compile
4.1. Value Set time, their size will default to 32-bits. If they hold constants, the synthesizer adjusts them to the minimum width
Verilog consists of only four basic values. Almost all Verilog data types store all these values: needed at compilation.
0 (logic zero, or false condition)
1 (logic one, or true condition)
Syntax Example 4 .4
x (unknown logic value) x and z have limited use for synthesis.
z (high impedance state) integer a; // single 32-bit integer
integer integer_variable_list;
assign b=63; // 63 defaults to a 7-bit variable.
... integer_constant ... ;
4.2. Wire
A wire represents a physical wire in a circuit and is used to connect gates or modules. The value of a wire can be
read, but not assigned to, in a function or block. See “Functions” on p. 19, and “Procedures: Always and Initial
Blocks” on p. 18. A wire does not store its value but must be driven by a continuous assignment statement or by con- 4.6. Supply0, Supply1
necting it to the output of a gate or module. Other specific types of wires include: Supply0 and supply1 define wires tied to logic 0 (ground) and logic 1 (power), respectively.
wand (wired-AND);:the value of a wand depend on logical AND of all the drivers connected to it.
wor (wired-OR);: the value of a wor depend on logical OR of all the drivers connected to it. Syntax Example 4 .5
tri (three-state;): all drivers connected to a tri must be z, except one (which determines the value of the tri).
supply0 logic_0_wires; supply0 my_gnd; // equivalent to a wire assigned 0
Syntax Example 4 .1 supply1 logic_1_wires; supply1 a, b;
wire c // simple wire
wire [msb:lsb] wire_variable_list;
wand d;
wand [msb:lsb] wand_variable_list;
assign d = a; // value of d is the logical AND of
wor [msb:lsb] wor_variable_list; 4.7. Time
assign d = b; // a and b
tri [msb:lsb] tri_variable_list; Time is a 64-bit quantity that can be used in conjunction with the $time system task to hold simulation time. Time is
wire [9:0] A; // a cable (vector) of 10 wires.
not supported for synthesis and hence is used only for simulation purposes.

4.3. Reg Syntax Example 4 .6

A reg (register) is a data object that holds its value from one procedural assignment to the next. They are used only in
functions and procedural blocks. See “Wire” on p. 4 above. A reg is a Verilog variable type and does not necessarily time time_variable_list; time c;
imply a physical register. In multi-bit registers, data is stored as unsigned numbers and no sign extension is done for c = $time; // c = current simulation time
what the user might have thought were two’s complement numbers.

Syntax Example 4 .2 4.8. Parameter

A parameter defines a constant that can be set when you instantiate a module. This allows customization of a mod-
reg a; // single 1-bit register variable
reg [msb:lsb] reg_variable_list; ule during instantiation. See also “Parameterized Modules” on page 11.
reg [7:0] tom; // an 8-bit vector; a bank of 8 registers.
reg [5:0] b, c; // two 6-bit variables
Syntax Example 4 .7
parameter add = 2’b00, sub = 3’b111;
parameter par_1 = value,
4.4. Input, Output, Inout par_2 = value, .....;
parameter n = 4;
These keywords declare input, output and bidirectional ports of a module or task. Input and inout ports are of type parameter n = 4;
parameter [range] parm_3 = value
wire. An output port can be configured to be of type wire, reg, wand, wor or tri. The default is wire. parameter [3:0] param2 = 4’b1010;
...
Syntax Example 4 .3 reg [n-1:0] harry; /* A 4-bit register whose length is
module sample(b, e, c, a); //See “Module Instantiations” on p. 10 set by parameter n above. */
input [msb:lsb] input_port_list; input a; // An input which defaults to wire. always @(x)
output [msb:lsb] output_port_list; output b, e; // Two outputs which default to wire y = {{(add - sub){x}}; // The replication operator Sect. 5.8.
inout [msb:lsb] inout_port_list; output [1:0] c; /* A two-it output. One must declare its if (x) begin
type in a separate statement. */ state = param2[1]; else state = param2[2];
reg [1:0] c; // The above c port is declared as reg. end

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 Introduction to Verilog Introduction to Verilog

5.5. Reduction Operators

5. Operators Reduction operators operate on all the bits of an operand vector and return a single-bit value. These are the unary (one
argument) form of the bit-wise operators above.
5.1. Arithmetic Operators
Operators Example 5 .5
These perform arithmetic operations. The + and - can be used as either unary (-z) or binary (x-y) operators.
module chk_zero (a, z); a(0)
& (reduction AND) a a(1) z
Operators Example 5 .1 input [2:0] a;
| (reduction OR) a(2)
output z; 3
parameter n = 4; ~& (reduction NAND)
+ (addition) assign z = ~| a; // Reduction NOR
reg[3:0] a, c, f, g, count; ~| (reduction NOR)
- (subtraction) endmodule
f = a + c; ^ (reduction XOR)
* (multiplication) ~^ or ^~(reduction XNOR)
g = c - n;
/ (division)
count = (count +1)%16; //Can count 0 thru 15.
% (modulus)

5.6. Shift Operators

5.2. Relational Operators Shift operators shift the first operand by the number of bits specified by the second operand. Vacated positions are
Relational operators compare two operands and return a single bit 1or 0. These operators synthesize into comparators. filled with zeros for both left and right shifts (There is no sign extension).
Wire and reg variables are positive Thus (-3’b001) = = 3’b111 and (-3d001)>3d110. However for integers -1< 6.
Operators Example 5 .6
Operators Example 5 .2 Equivalent Statement
if (x = = y) e = 1; assign c = a << 2; /* c = a shifted left 2 bits;
<< (shift left)
< (less than) else e = 0; e = (x == y); vacant positions are filled with 0’s */
>> (shift right)
<= (less than or equal to)
> (greater than) // Compare in 2’s compliment; a>b
>= (greater than or equal to) reg [3:0] a,b;
== (equal to) if (a[3]= = b[3]) a[2:0] > b[2:0];
!= (not equal to) else b[3]; 5.7. Concatenation Operator
The concatenation operator combines two or more operands to form a larger vector.

5.3. Bit-wise Operators Operators Example 5 .7

Bit-wise operators do a bit-by-bit comparison between two operands. However see“Reduction Operators” on p. 7.
wire [1:0] a, b; wire [2:0] x; wire [3;0] y, Z;
{ } (concatenation) assign x = {1’b0, a}; // x[2]=0, x[1]=a[1], x[0]=a[0]
Operators Example 5 .3
a a(0 assign y = {a, b}; /* y[3]=a[1], y[2]=a[0], y[1]=b[1],
~ (bitwise NOT) module and2 (a, b, c); b(0) c(0 y[0]=b[0] */
2
& (bitwise AND) input [1:0] a, b;
| (bitwise OR) output [1:0] c; a(1)
assign {cout, y} = x + Z; // Concatenation of a result
^ (bitwise XOR) assign c = a & b; b b(1) c(1)
~^ or ^~(bitwise XNOR) endmodule 2
5.8. Replication Operator
The replication operator makes multiple copies of an item.
5.4. Logical Operators
Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for single bit operands. They Operators Example 5 .8
can work on expressions, integers or groups of bits, and treat all values that are nonzero as “1”. Logical operators are wire [1:0] a, b; wire [4:0] x;
typically used in conditional (if ... else) statements since they work with expressions. {n{item}} (n fold replication of an item) assign x = {2{1’b0}, a}; // Equivalent to x = {0,0,a }
Operators assign y = {2{a}, 3{b}}; //Equivalent to y = {a,a,b,b}
Example 5 .4
wire[7:0] x, y, z; // x, y and z are multibit variables.
! (logical NOT) reg a;
&& (logical AND) ... For synthesis, Synopsis did not like a zero replication. For example:-
|| (logical OR) if ((x == y) && (z)) a = 1; // a = 1 if x equals y, and z is nonzero. parameter n=5, m=5;
else a = !x; // a =0 if x is anything but zero. assign x= {(n-m){a}}

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 Introduction to Verilog Introduction to Verilog

5.9. Conditional Operator: “?”

Conditional operator is like those in C/C++. They evaluate one of the two expressions based on a condition. It will 6. Operands
synthesize to a multiplexer (MUX).

Operators
6.1. Literals
Example 5 .9
x y Literals are constant-valued operands that can be used in Verilog expressions. The two common Verilog literals are:
assign a = (g) ? x : y; g
(cond) ? (result if cond true): 1 1 (a) String: A string literal is a one-dimensional array of characters enclosed in double quotes (“ “).
assign a = (inc = = 2) ? a+1 : a-1; (b) Numeric: constant numbers specified in binary, octal, decimal or hexadecimal.
(result if cond false) /* if (inc), a = a+1, else a = a-1 */
Number Syntax Example 6 .1

n’Fddd..., where “time is”// string literal

5.10. Operator Precedence n - integer representing number of bits 267 // 32-bit decimal number
Table 6.1 shows the precedence of operators from highest to lowest. Operators on the same level evaluate from left to F - one of four possible base formats: 2’b01 // 2-bit binary
right. It is strongly recommended to use parentheses to define order of precedence and improve the readability of b (binary), o (octal), d (decimal), 20’hB36F// 20-bit hexadecimal number
your code. h (hexadecimal). Default is d. ‘o62 // 32-bit octal number
dddd - legal digits for the base format
Operator Name
[ ] bit-select or part-select
( ) parenthesis
6.2. Wires, Regs, and Parameters
Wires, regs and parameters can also be used as operands in Verilog expressions. These data objects are described in
!, ~ logical and bit-wise NOT more detail in Sect. 4. .
&, |, ~&, ~|, ^, ~^, ^~ reduction AND, OR, NAND, NOR, XOR, XNOR;
If X=3’B101 and Y=3’B110, then X&Y=3’B100, X^Y=3’B011;
+, - unary (sign) plus, minus; +17, -7 6.3. Bit-Selects “x[3]” and Part-Selects “x[5:3]”
Bit-selects and part-selects are a selection of a single bit and a group of bits, respectively, from a wire, reg or parame-
{ } concatenation; {3’B101, 3’B110} = 6’B101110; ter vector using square brackets “[ ]”. Bit-selects and part-selects can be used as operands in expressions in much the
{{ }} replication; {3{3'B110}} = 9'B110110110 same way that their parent data objects are used.
*, /, % multiply, divide, modulus; / and % not be supported for synthesis
Syntax Example 6 .2
+, - binary add, subtract.
reg [7:0] a, b;
<<, >> shift left, shift right; X<<2 is multiply by 4 variable_name[index]
reg [3:0] ls;
variable_name[msb:lsb]
<, <=, >, >= comparisons. Reg and wire variables are taken as positive numbers. reg c;
c = a[7] & b[7]; // bit-selects
= =, != logical equality, logical inequality
ls = a[7:4] + b[3:0]; // part-selects
= = =, != = case equality, case inequality; not synthesizable
& bit-wise AND; AND together all the bits in a word
^, ~^, ^~ bit-wise XOR, bit-wise XNOR
6.4. Function Calls
The return value of a function can be used directly in an expression without first assigning it to a register or wire var-
| bit-wise OR; AND together all the bits in a word iable. Simply place the function call as one of the operands. Make sure you know the bit width of the return value of
&&, logical AND. Treat all variables as False (zero) or True (nonzero). the function call. Construction of functions is described in “Functions” on page 19
logical OR. (7||0) is (T||F) = 1, (2||-3) is (T||T) =1,
||
(3&&0) is (T&&F) = 0. Syntax Example 6 .3
?: conditional. x=(cond)? T : F; assign a = b & c & chk_bc(c, b);// chk_bc is a function
function_name (argument_list)
Table 5.1: Verilog Operators Precedence . . ./* Definition of the function */
function chk_bc;// function definition
input c,b;
chk_bc = b^c;
endfunction

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 Introduction to Verilog Introduction to Verilog

7. Modules Syntax for Instantiation Example 7 .3 // MODULE INSTANTIATIONS

module_name wire [3:0] in1, in2;
instance_name_1 (port_connection_list), // MODULEDEFINITION wire [3:0] o1, o2;
7.1. Module Declaration instance_name_2 (port_connection_list), /* C1 is an instance of module and4
A module is the principal design entity in Verilog. The first line of a module declaration specifies the name and port ...... module and4(a, b, c); C1 ports referenced by position */
list (arguments). The next few lines specifies the i/o type (input, output or inout, see Sect. 4.4. ) and width of each instance_name_n (port_connection_list); input [3:0] a, b; and4 C1 (in1, in2, o1);
port. The default port width is 1 bit. output [3:0] c; /* C2 is another instance of and4.
Then the port variables must be declared wire, wand,. . ., reg (See Sect. 4. ). The default is wire. Typically inputs are assign c = a & b; C2 ports are referenced to the
wire since their data is latched outside the module. Outputs are type reg if their signals were stored inside an always endmodule declaration by name. */
or initial block (See Sect. 10. ). and4 C2 (.c(o2), .a(in1), .b(in2));

Syntax Example 7 .1 add

Modules may not be instantiated inside procedural blocks. See “Procedures: Always and Initial Blocks” on page 18.
module module_name (port_list); module add_sub(add, in1, in2, oot); in1
input [msb:lsb] input_port_list; input add; // defaults to wire oot 7.4. Parameterized Modules
8 add_sub
output [msb:lsb] output_port_list; input [7:0] in1, in2; wire in1, in2; in2 You can build modules that are parameterized and specify the value of the parameter at each instantiation of the mod-
inout [msb:lsb] inout_port_list; 8
output [7:0] oot; reg oot; ule. See “Parameter” on page 5 for the use of parameters inside a module. Primitive gates have parameters which
... statements ... 8
... statements ... have been predefined as delays. See “Basic Gates” on page 3.
endmodule endmodule
Syntax Example 7 .4
// MODULE DEFINITION
7.2. Continuous Assignment module_name #(parameter_values) module shift_n (it, ot); // used in module test_shift.
The continuous assignment is used to assign a value onto a wire in a module. It is the normal assignment outside of instance_name(port_connection_list); input [7:0] it; output [7:0] ot;
always or initial blocks (See Sect. 10. ). Continuous assignment is done with an explicit assign statement or by parameter n = 2;‘ // default value of n is 2
assigning a value to a wire during its declaration. Note that continuous assignment statements are concurrent and are assign ot = (it << n); // it shifted left n times
continuously executed during simulation. The order of assign statements does not matter. Any change in any of the endmodule
right-hand-side inputs will immediately change a left-hand-side output.
// PARAMETERIZED INSTANTIATIONS
Syntax Example 7 .2 wire [7:0] in1, ot1, ot2, ot3;
wire [1:0] a = 2’b01; // assigned on declaration shift_n shft2(in1, ot1), // shift by 2; default
wire wire_variable = value; shift_n #(3) shft3(in1, ot2); // shift by 3; override parameter 2.
assign wire_variable = expression; assign b = c & d; // using assign statement
assign d = x | y; c shift_n #(5) shft5(in1, ot3); // shift by 5; override parameter 2.
b
/* The order of the assign statements x d
y
does not matter. */
Synthesis does not support the defparam keyword which is an alternate way of changing parameters.

7.3. Module Instantiations

Module declarations are templates from which one creates actual objects (instantiations). Modules are instantiated
inside other modules, and each instantiation creates a unique object from the template. The exception is the top-level
module which is its own instantiation.

The instantiated module’s ports must be matched to those defined in the template. This is specified:
(i) by name, using a dot(.) “ .template_port_name (name_of_wire_connected_to_port)”.
or(ii) by position, placing the ports in exactly the same positions in the port lists of both the template and the instance.

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 Introduction to Verilog Introduction to Verilog

c
8.4. Nonblocking (RTL) Assignments (see below for synthesis)
8. Behavioral Modeling RTL (nonblocking) assignments (<=), which follow each other in the code, are started in parallel. The right hand
side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none,
Verilog has four levels of modelling: the start of the procedure. The transfer to the left hand side is made according to the delays. An intra-assignment
1) The switch level which includes MOS transistors modelled as switches. This is not discussed here. delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking.
2) The gate level. See “Gate-Level Modelling” on p. 3 However a normal delays will are cummulative and will delay the output.
3) The Data-Flow level. See Example 7 .4 on page 11 For synthesis
4) The Behavioral or procedural level described below. • One must not mix “<=” or “=” in the same procedure.
Verilog procedural statements are used to model a design at a higher level of abstraction than the other levels. They
• “<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk ..) type procedures.
provide powerful ways of doing complex designs. However small changes n coding methods can cause large changes
in the hardware generated. Procedural statements can only be used in procedures. Verilog procedures are described • “=” best corresponds to what c/c++ code would do; use it for combinational procedures.
later in “Procedures: Always and Initial Blocks” on page 18,“Functions” on page 19, and “Tasks, Not Synthesizable” :
on page 21. Syntax Example 8 .3. For simulation
Non-Blocking initial
8.1. Procedural Assignments variable <= expression; begin
variable <= #Δt expression; #3 b <= a; /* grab a at t=0 Deliver b at t=3.
Procedural assignments are assignment statements used within Verilog procedures (always and initial blocks). Only
#Δt variable <= expression; #6 x <= b + c; // grab b+c at t=0, wait and assign x at t=6.
reg variables and integers (and their bit/part-selects and concatenations) can be placed left of the “=” in procedures.
x is unaffected by b’s change. */
The right hand side of the assignment is an expression which may use any of the operator types described in Sect. 5.
Example 8 .4. For synthesis X Y Z
8.2. Delay in Assignment (not for synthesis) always @( posedge clk) 1D 1D
In a delayed assignment Δt time units pass before the statement is executed and the left-hand assignment is made. C1 C1
begin
With intra-assignment delay, the right side is evaluated immediately but there is a delay of Δt before the result is Z<=Y; Y<=X; // shift register x y z
place in the left hand assignment. If another procedure changes a right-hand side signal during Δt, it does not effect 1D 1D
y<=x; z<=y; //also a shift register.
C1 C1
the output. Delays are not supported by synthesis tools.
Syntax for Procedural Assignment Example 8 .1 Example 8 .3. Use <= to transform a variable into itself.
variable = expression reg G[7:0];
Delayed assignment reg [6:0] sum; reg h, ziltch;
sum[7] = b[7] ^ c[7]; // execute now. always @( posedge clk)
#Δt variable = expression; G <= { G[6:0], G[7]}; // End around rotate 8-bit register.
Intra-assignment delay ziltch = #15 ckz&h; /* ckz&a evaluated now; ziltch changed
variable = #Δt expression; after 15 time units. */
#10 hat = b&c; /* 10 units after ziltch changes, b&c is
evaluated and hat changes. */ The following example shows interactions between blocking and non-blocking for simulation. Do not mix the two
types in one procedure for synthesis.

8.3. Blocking Assignments Syntax Example 8 .4 for simulation only

Procedural (blocking) assignments (=) are done sequentially in the order the statements are written. A second initial begin
assignment is not started until the preceding one is complete. See also Sect. 9.4. Non-Blocking a=1; b=2; c=3; x=4;
variable <= expression; #5 a = b + c; // wait for 5 units, then grab b,c and execute a=2+3.
Syntax Example 8 .2. For simulation variable <= #Δt expression; d = a; // Time continues from last line, d=5 = b+c at t=5.
Blocking initial #Δt variable <=expression; x <= #6 b + c;// grab b+c now at t=5, don’t stop, make x=5 at t=11.
variable = expression; begin Blocking b <= #2 a; /* grab a at t=5 (end of last blocking statement).
variable = #Δt expression; a=1; b=2; c=3; variable = expression; Deliver b=5 at t=7. previous x is unaffected by b change. */
grab inputs now, deliver ans. #5 a = b + c; // wait for 5 units, and execute a= b + c =5. variable = #Δt expression; y <= #1 b + c;// grab b+c at t=5, don’t stop, make x=5 at t=6.
later. d = a; // Time continues from last line, d=5 = b+c at t=5. #Δt variable = expression; #3 z = b + c; // grab b+c at t=8 (#5+#3), make z=5 at t=8.
#Δt variable = expression; w <= x // make w=4 at t=8. Starting at last blocking assignm.
grab inputs later, deliver ans. Example 8 .2. For synthesis X Y Z
later 1D 1D
always @( posedge clk)
begin
C1 C1 8.5. begin ... end
Z=Y; Y=X; // shift register begin ... end block statements are used to group several statements for use where one statement is syntactically
x y
y=x; z=y; //parallel ff. 1D 1D z allowed. Such places include functions, always and initial blocks, if, case and for statements. Blocks can optionally
C1 C1 be named. See “disable” on page 15) and can include register, integer and parameter declarations.

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 Introduction to Verilog Introduction to Verilog

Syntax Example 8 .5 Syntax Example 8 .9

begin : block_name function trivial_one; // The block name is “trivial_one.” repeat (number_of_times) repeat (2) begin // after 50, a = 00,
reg [msb:lsb] reg_variable_list; input a; begin #50 a = 2’b00; // after 100, a = 01,
integer [msb:lsb] integer_list; begin: adder_blk; // block named adder, with ... statements ... #50 a = 2’b01; // after 150, a = 00,
parameter [msb:lsb] parameter_list; integer i; // local integer i end end// after 200, a = 01
... statements ... ... statements ...
end end
8.10. disable
8.6. for Loops Execution of a disable statement terminates a block and passes control to the next statement after the block. It is like
Similar to for loops in C/C++, they are used to repeatedly execute a statement or block of statements. If the loop con- the C break statement except it can terminate any loop, not just the one in which it appears.
tains only one statement, the begin ... end statements may be omitted. Disable statements can only be used with named blocks.
Syntax Example 8 .10
Syntax Example 8 .6
disable block_name; begin: accumulate
for (count = value1; for (j = 0; j <= 7; j = j + 1) forever
count </<=/>/>= value2; begin begin
count = count +/- step) c[j] = a[j] & b[j]; @(posedge clk);
begin d[j] = a[j] | b[j]; a = a + 1;
... statements ... end if (a == 2’b0111) disable accumulate;
end end
end
8.7. while Loops
The while loop repeatedly executes a statement or block of statements until the expression in the while statement
evaluates to false. To avoid combinational feedback during synthesis, a while loop must be broken with an
8.11. if ... else if ... else
@(posedge/negedge clock) statement (Section 9.2). For simulation a delay inside the loop will suffice. If the loop The if ... else if ... else statements execute a statement or block of statements depending on the result of the expression
contains only one statement, the begin ... end statements may be omitted. following the if. If the conditional expressions in all the if’s evaluate to false, then the statements in the else block, if
present, are executed.
Syntax There can be as many else if statements as required, but only one if block and one else block. If there is one statement
Example 8 .7
in a block, then the begin .. end statements may be omitted.
while (expression) Both the else if and else statements are optional. However if all possibilities are not specifically covered, synthesis
while (!overflow) begin
begin will generated extra latches.
@(posedge clk);
... statements ... a = a + 1;
end Syntax Example 8 .11
end
if (expression) if (alu_func == 2’b00)
8.8. forever Loops begin aluout = a + b;
The forever statement executes an infinite loop of a statement or block of statements. To avoid combinational feed- ... statements ... else if (alu_func == 2’b01)
back during synthesis, a forever loop must be broken with an @(posedge/negedge clock) statement (Section 9.2). For end aluout = a - b;
simulation a delay inside the loop will suffice. If the loop contains only one statement, the begin ... end statements else if (expression) else if (alu_func == 2’b10)
may be omitted. It is begin aluout = a & b;
Syntax ... statements ... else // alu_func == 2’b11
Example 8 .8
end aluout = a | b;
forever begin
forever ... more else if blocks ...
@(posedge clk); // or use a= #9 a+1;
begin else if (a == b) // This if with no else will generate
a = a + 1;
... statements ... begin begin // a latch for x and ot. This is so they
end
end ... statements ... x = 1; // will hold there old value if (a != b).
end ot = 4’b1111;
end

8.9. repeat Not synthesizable

The repeat statement executes a statement or block of statements a fixed number of times.

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 Introduction to Verilog Introduction to Verilog

8.12. case
The case statement allows a multipath branch based on comparing the expression with a list of case choices. 9. Timing Controls
Statements in the default block executes when none of the case choice comparisons are true (similar to the else block
in the if ... else if ... else). If no comparisons , including delault, are true, synthesizers will generate unwanted latches. 9.1. Delay Control, Not synthesizable
Good practice says to make a habit of puting in a default whether you need it or not.
This specifies the delay time units before a statement is executed during simulation. A delay time of zero can also be
If the defaults are dont cares, define them as ‘x’ and the logic minimizer will treat them as don’t cares.
specified to force the statement to the end of the list of statements to be evaluated at the current simulation time. See
Case choices may be a simple constant or expression, or a comma-separated list of same.
also “Intra-Assignment Delay, Not synthesizable” on p. 17

Syntax Example 8 .12 Syntax Example 9 .1

case (alu_ctr) #delay statement; #5 a = b + c; // evaluated and assigned after 5 time units
case (expression) 2’b00: aluout = a + b; #0 a = b + c; // very last statement to be evaluated
case_choice1: 2’b01: aluout = a - b;
begin 2’b10: aluout = a & b;
... statements ... default: aluout = 1’bx; // Treated as don’t cares for
end endcase // minimum logic generation.
9.2. Event Control, @
case_choice2: This causes a statement or begin-end block to be executed only after specified events occur. An event is a change in
begin a variable. and the change may be: a positive edge, a negative edge, or either (a level change), and is specified by the
... statements ... Example 8 .13 keyword posedge, negedge, or no keyword respectively. Several events can be combined with the or keyword. Event
end specification begins with the character @and are usually used in always statements. See page 18.
case (x, y, z)
... more case choices blocks ... 2’b00: aluout = a + b; //case if x or y or z is 2’b00. For synthesis one cannot combine level and edge changes in the same list.
default: 2’b01: aluout = a - b; For flip-flop and register synthesis the standard list contains only a clock and an optional reset.
begin 2’b10: aluout = a & b; For synthesis to give combinational logic, the list must specify only level changes and must contain all the variables
... statements ... default: aluout = a | b; appearing in the right-hand-side of statements in the block.
end endcase
endcase Syntax Example 9 .2
@ (posedge variable or always
negedge variable) statement; @(posedge clk or negedge rst)
8.13. casex
if (rst) Q=0; else Q=D; // Definition for a D flip-flop.
In casex(a) the case choices constant “a” may contain z, x or ? which are used as don’t cares for comparison. With @ (variable or variable . . .) statement;
case the corresponding simulation variable would have to match a tri-state, unknown, or either signal. In short, case @(a or b or e); // re-evaluate if a or b or e changes.
uses x to compare with an unknown signal. Casex uses x as a don’t care which can be used to minimize logic. sum = a + b + e; // Will synthesize to a combinational adder.

Syntax Example 8 .12

casex (a)
same as for case statement 2’b1x: msb = 1; // msb = 1 if a = 10 or a = 11 9.3. Wait Statement Not synthesizable
(Section 8.10) // If this were case(a) then only a=1x would match. Delay executing the statement(s) following the wait until the specified condition evaluates to true.
default: msb = 0; Syntax Example 9 .3
endcase
wait (condition_expression) statement; wait (!c) a = b; // wait until c=0, then assign b to a

8.14. casez 9.4. Intra-Assignment Delay, Not synthesizable

Casez is the same as casex except only ? and z (not x) are used in the case choice constants as don’t cares. Casez is This delay #Δ is placed after the equal sign. The left-hand assignment is delayed by the specified time units, but the
favored over casex since in simulation, an inadvertent x signal, will not be matched by a 0 or 1 in the case choice. right-hand side of the assignment is evaluated before the delay instead of after the delay. This is important when a
variable may be changed in a concurrent procedure. See also “Delay in Assignment (not for synthesis)” on page 12.
Syntax Example 8 .13
Syntax Example 9 .4
same as for case statement casez (d) assign a=1; assign b=0;
(Section 8.10) 3’b1??: b = 2’b11; // b = 11 if d = 100 or greater variable = #Δt expression; always @(posedge clk)
3’b01?: b = 2’b10; // b = 10 if d = 010 or 011 b = #5 a; // a = b after 5 time units.
default: b = 2’b00; always @(posedge clk)
endcase c = #5 b; /* b was grabbed in this parallel proce-
dure before the first procedure changed it. */

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 Introduction to Verilog Introduction to Verilog

10. Procedures: Always and Initial Blocks 11. Functions

10.1. Always Block Functions are declared within a module, and can be called from continuous assignments, always blocks, or other
The always block is the primary construct in RTL modeling. Like the continuous assignment, it is a concurrent functions. In a continuous assignment, they are evaluated when any of its declared inputs change. In a procedure, they
statement that is continuously executed during simulation. This also means that all always blocks in a module execute are evaluated when invoked.
simultaneously. This is very unlike conventional programming languages, in which all statements execute sequen- Functions describe combinational logic, and by do not generate latches. Thus an if without an else will simulate as
tially. The always block can be used to imply latches, flip-flops or combinational logic. If the statements in the though it had a latch but synthesize without one. This is a particularly bad case of synthesis not following the simula-
always block are enclosed within begin ... end, the statements are executed sequentially. If enclosed within the fork tion. It is a good idea to code functions so they would not generate latches if the code were used in a procedure.
... join, they are executed concurrently (simulation only). Functions are a good way to reuse procedural code, since modules cannot be invoked from within a procedure.
The always block is triggered to execute by the level, positive edge or negative edge of one or more signals (sepa-
rate signals by the keyword or). A double-edge trigger is implied if you include a signal in the event list of the always 11.1. Function Declaration
statement. The single edge-triggers are specified by posedge and negedge keywords. A function declaration specifies the name of the function, the width of the function return value, the function input
arguments, the variables (reg) used within the function, and the function local parameters and integers.
Procedures can be named. In simulation one can disable named blocks. For synthesis it is mainly used as a com-
ment.
Syntax, Function Declaration Example 11 .1
Syntax 1 Example 10 .1 function [msb:lsb] function_name; function [7:0] my_func; // function return 8-bit value
input [msb:lsb] input_arguments; input [7:0] i;
always @(event_1 or event_2 or ...) always @(a or b) // level-triggered; if a or b changes levels reg [msb:lsb] reg_variable_list; reg [4:0] temp;
begin always @(posedge clk); // edge-triggered: on +ve edge of clk parameter [msb:lsb] parameter_list; integer n;
... statements ...
integer [msb:lsb] integer_list; temp= i[7:4] | ( i[3:0]);
end see previous sections for complete examples ... statements ... my_func = {temp, i[[1:0]};
endfunction endfunction
Syntax 2

always @(event_1 or event_2 or ...)

begin: name_for_block
... statements ... 11.2. Function Return Value
end When you declare a function, a variable is also implicitly declared with the same name as the function name, and with
the width specified for the function name (The default width is 1-bit). This variable is “my_func” in Example 11 .1 on
page 19. At least one statement in the function must assign the function return value to this variable.

10.2. Initial Block

The initial block is like the always block except that it is executed only once at the beginning of the simulation. It is 11.3. Function Call
typically used to initialize variables and specify signal waveforms during simulation. Initial blocks are not supported As mentioned in Sect. 6.4. , a function call is an operand in an expression. A function call must specify in its terminal
for synthesis. list all the input parameters.

Syntax Example 10 .2

initial
11.4. Function Rules
inital
begin The following are some of the general rules for functions:
begin
... statements ... - Functions must contain at least one input argument.
clr = 0; // variables initialized at
end - Functions cannot contain an inout or output declaration.
clk = 1; // beginning of the simulation
- Functions cannot contain time controlled statements (#, @, wait).
end
- Functions cannot enable tasks.
- Functions must contain a statement that assigns the return value to the implicit function name register.
inital // specify simulation waveforms
begin
a = 2’b00; // at time = 0, a = 00
#50 a = 2’b01; // at time = 50, a = 01
#50 a = 2’b10; // at time = 100, a = 10
end

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 Introduction to Verilog Introduction to Verilog

11.5. Function Example

A Function has only one output. If more than one return value is required, the outputs should be concatenated into 12. Tasks, Not Synthesizable
one vector before assigning it to the function name. The calling module program can then extract (unbundle) the indi-
vidual outputs from the concatenated form. Example 11.2 shows how this is done, and also illustrates the general use A task is similar to a function, but unlike a function it has both input and output ports. Therefore tasks do not return
and syntax of functions in Verilog modeling. values. Tasks are similar to procedures in most programming languages. The syntax and statements allowed in tasks
Syntax Example 11 .2 are those specified for functions (Sections 11).
module simple_processor (instruction, outp);
function_name = expression input [31:0] instruction;
Syntax Example 12 .1
output [7:0] outp;
reg [7:0] outp;; // so it can be assigned in always block
task task_name; module alu (func, a, b, c);
reg func;
input [msb:lsb] input_port_list; input [1:0] func;
reg [7:0] opr1, opr2;
output [msb:lsb] output_port_list; input [3:0] a, b;
reg [msb:lsb] reg_variable_list; output [3:0] c;
function [16:0] decode_add (instr) // returns 1 1-bit plus 2 8-bits
parameter [msb:lsb] parameter_list; reg [3:0] c; // so it can be assigned in always block
input [31:0] instr;
integer [msb:lsb] integer_list;
reg add_func;
... statements ... task my_and;
reg [7:0] opcode, opr1, opr2;
endtask input[3:0] a, b;
begin
opcode = instr[31:24]; output [3:0] andout;
opr1 = instr[7:0]; integer i;
case (opcode) begin
8’b10001000: begin // add two operands for (i = 3; i >= 0; i = i - 1)
add_func = 1; andout[i] = a[i] & b[i];
opr2 = instr[15:8]; end
end endtask
8’b10001001: begin // subtract two operands
add_func = 0; always @(func or a or b) begin
opr2 = instr[15:8]; case (func)
end 2’b00: my_and (a, b, c);
8’b10001010: begin // increment operand 2’b01: c = a | b;
add_func = 1; 2’b10: c = a - b;
opr2 = 8’b00000001; default: c = a + b;
end endcase
default: begin; // decrement operand end
add_func = 0; endmodule
opr2 = 8’b00000001;
end
endcase
decode_add = {add_func, opr2, opr1}; // concatenated into 17-bits
end
endfunction
// ----------------------------------------- ---------------------------------
always @(instruction) begin
{func, op2, op1} = decode_add (instruction); // outputs unbundled
if (func == 1)
outp = op1 + op2;
else
outp = op1 - op2;
end
endmodule

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 Introduction to Verilog Introduction to Verilog

13.3. Multiplexers
13. Component Inference A multiplexer is inferred by assigning a variable to different variables/values in each branch of an if or case state-
ment. You can avoid specifying each and every possible branch by using the else and default branches. Note that a
latch will be inferred if a variable is not assigned to for all the possible branch conditions.
13.1. Latches To improve readability of your code, use the case statement to model large multiplexers.
A latch is inferred (put into the synthesized circuit) if a variable, or one of its bits, is not assigned in all branch of an
if statement. A latch is also inferred in a case statement if a variable is assigned to in only some of the branches.
Syntax Example 13 .5
To improve code readability, use the if statement to synthesize a latch because it is difficult to explicitly specify
sel
the latch enable signal using a case statement.
See Sections 8.9 and 8.10 for if (sel == 1)
While in theory, a proper reset should be infered from the Verilog code shown, Synopsys will not do a proper job
if ... else if ... else and case statements y = a; a
without adding the //Synopsys comments shown. y
else
b
y = b;
Syntax Example 13 .1
See Sect. 8.11. and Sect. 8.12. for always @(clk,d); begin d D
Q q case (sel) sel[1:0]
if ... else if ... else and case statements if (clk)
2’b00: y = a; a
q <=d;
clk EN 2’b01: y = b; b
//Synopsys statement end
2’b10: y = c; y
These are treated as comments by all sim- c
Example 13 .2 default: y = d;
ulators. For synthesis using Synopsys, d
//Synopsys async_set_reset “rst” d endcase
they direct the synthesizer as to what par- D
q
Q
ticular inference is wanted. always @(clk or rst or d); begin
if (rst) q<=0; clk EN

else if (clk) q<=d; R

end rst 13.4. Adders/Subtracters

The +/- operators infer an adder/subtracter whose width depend on the width of the larger operand.

13.2. Edge-Triggered Registers, Flip-flops, Counters Syntax Example 13 .6

A register (flip-flop) is inferred by using posedge or negedge clause for the clock in the event list of an always sel
block. To add an asynchronous reset, include a second posedge/negedge for the reset and use the if (reset) ... else a
See Section 7 for operators if (sel == 1)
statement. Note that when you use the negedge for the reset (active low reset), the if condition is (!reset). c
y = a + b; sel + y
Syntax else b
Example 13 .3 b CLR y = c + d; d
always @(posedge clk or always @(posedge clk); c D
posedge reset_1 or begin; Q a
negedge reset_2) a <= b & c; clk CLK
begin end
if (reset_1) begin 13.5. Tri-State Buffers
... reset assignments always @(posedge clk or rst A tristate buffer is inferred if a variable is conditionally assigned a value of z using an if, case or conditional operator.
end negedge rst);
CLR
else if (!reset_2) begin begin; b D
Syntax Example 13 .7
... reset assignments if (! rst) a< = 0; a
Q
end else a <= b; See Sections 8.9 and 8.10 for if (en == 1)
clk CLK en
else begin end if ... else if ... else and case statements y = a;
a y
...register assignments else
end y = 1’bz;
end Example 13 .4 An Enabled Counter
reg [7:0] count;
wire enable;
always @(posedge clk or posedge rst) // Do not include enable. 13.6. Other Component Inferences
begin;
Most logic gates are inferred by the use of their corresponding operators. Alternatively a gate or component may be
if (rst) count<=0;
explicitly instantiated by using the primitive gates (and, or, nor, inv ...) provided in the Verilog language.
else if (enable) count <= count+1;
end; // 8 flip-flops will be generated.

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 Introduction to Verilog Introduction to Verilog

14.1.

14. Finite State Machines. For synthesis 14.2. Counters

Counters are a simple type of finite-state machine where separation of the flip-flop generation code and the next-state
generation code is not worth the effort. In such code, use the nonblocking “<=” assignment operator.
When modeling finite state machines, it is recommended to separate the sequential current-state logic from the com-
binational next-state and output logic. Binary Counter Example 14 .2
Using toggle flip-flops reg [3:0] count; wire TC; // Terminal count (Carry out)
State Diagram Example 14 .1 always @(posedge clk or posedge rset)
TC
begin
for lack of space the outputs are not module my_fsm (clk, rst, start, skip3, wait3, Zot); if (rset) count <= 0;
1T 1T 1T 1T
shown on the state diagram, but are: input clk, rst, start, skip3, wait3; C1 C1 C1 C1 else count <= count+1;
in state0: Zot = 000, output [2:0] Zot; // Zot is declared reg so that it can count[3] count[2] end
in state1: Zot = 101, count[1] count[0]
reg [2:0] Zot; // be assigned in an always block. CLK
assign TC = & count; // See “Reduction Operators” on page 7
in state2: Zot = 111, parameter state0=0, state1=1, state2=2, state3=3;
in state3: Zot = 001. reg [1:0] state, nxt_st;
14.3. Shift Registers
always @ (state or start or skip3 or wait3) Shift registers are also best done completely in the flip-flop generation code. Use the nonblocking “<=” assignment
start=0
begin : next_state_logic //Name of always procedure. operator so the operators “<< N” shifts left N bits. The operator “>>N” shifts right N bits. See also Example 8 .3 on
reset=1 case (state) page 13.
state0: begin
state0 if (start) nxt_st = state1; Shift Register Example 14 .3
wait3=0 start=1 else nxt_st = state0; reg [3:0] Q;
end always @(posedge clk or posedge rset)
state1: begin Q[3] Q[2] Q[1] Q[0]
1D 1D 1D 1D begin
nxt_st = state2; C1 C1 C1 C1 if (rset) Q <= 0;
state3
skip3=1 state1 end else begin
CLK
state2: begin Q <=Q << 1; // Left shift 1 position
wait3=1
if (skip3) nxt_st = state0; Q[0] <= Q[3]; /* Nonblocking means the old Q[3] is sent
skip3=0
else nxt_st = state3; to Q[0]. Not the revised Q[3] from the previous line.
end end
state2 state3: begin
if (wait3) nxt_st = state3;
else nxt_st = state0; Linear-Feedback Shift Register Example 14 .4
end reg [3:0] Q;
default: nxt_st = state0; always @(posedge clk or posedge rset)
Using Macros for state definition Q[3] Q[2] Q[1] Q[0]
endcase // default is optional since all 4 cases are 1D 1D 1D 1D begin
As an alternative for-
end // covered specifically. Good practice says uses it. C1 C1 C1 C1 if (rset) Q <= 0;
parameter state0=0, state1=1,
else begin
state2=2, state3=3; always @(posedge clk or posedge rst) CLK
Q <= {Q[2:1]: Q[3]^Q[2]; /* The concatenation operators
one can use macros. For example after the begin : register_generation “{...}” form the new Q from elements of the old Q. */
definition below 2'd0 will be textually if (rst) state = state0; end
substituted whenever `state0 is used. else state = nxt_st; end
`define state0 2'd0 end
`define state1 2'd1
`define state2 2'd always @(state) begin : output_logic
`define state3 2'd3; case (state)
state0: Zot = 3’b000;
When using macro definitions one must state1: Zot = 3’b101;
put a back quote in front. For example: state2: Zot = 3’b111;
case (state) state3: Zot = 3’b001;
`state0: Zot = 3’b000; default: Zot = 3’b000;// default avoids latches
`state1: Zot = 3’b101; endcase
`state2: Zot = 3’b111; end
`state3: Zot = 3’b001; endmodule

Thursday, October 11, 2001 9:39 pm 24 Peter M. Nyasulu Thursday, October 11, 2001 9:39 pm 25 Peter M. Nyasulu
 Introduction to Verilog Introduction to Verilog

15. Compiler Directives 16. System Tasks and Functions

Compiler directives are special commands, beginning with ‘, that affect the operation of the Verilog simulator. The These are tasks and functions that are used to generate input and output during simulation. Their names begin with a
Synopsys Verilog HDL Compiler/Design Compiler and many other synthesis tools parse and ignore compiler direc- dollar sign ($). The Synopsys Verilog HDL Compiler/Design Compiler and many other synthesis tools parse and
tives, and hence can be included even in synthesizable models. Refer to Cadence Verilog-XL Reference Manual for a ignore system functions, and hence can be included even in synthesizable models. Refer to Cadence Verilog-XL Ref-
complete listing of these directives. A few are briefly described here. erence Manual for a complete listing of system functions. A few are briefly described here.
System tasks that extract data, like $monitor need to be in an initial or always block.
15.1. Time Scale
`timescale specifies the time unit and time precision. A time unit of 10 ns means a time expressed as say #2.3 will 16.1. Display Selected Variables; $display, $strobe, $monitor
have a delay of 23.0 ns. Time precision specifies how delay values are to be rounded off during simulation. Valid These commands have the same syntax, and display text on the screen during simulation. They are much less conven-
time units include s, ms, us (μs), ns, ps, fs. ient than waveform display tools like cwaves® or Signalscan®. $display and $strobe display once every time they
Only 1, 10 or 100 are valid integers for specifying time units or precision. It also determines the displayed time units are executed, whereas $monitor displays every time one of its parameters changes. The difference between $display
in display commands like $display and $strobe is that $strobe displays the parameters at the very end of the current simulation time unit rather than
exactly where it is executed. The format string is like that in C/C++, and may contain format characters. Format char-
Syntax Example 15 .1 acters include %d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t (time), %m (hierar-
`timescale 1 ns/1 ps // unit =1ns, precision=1/1000ns chy level). %5d, %5b etc. would give exactly 5 spaces for the number instead of the space needed. Append b, h, o to
`timescale time_unit / time_precision; `timescale 1 ns /100 ps // time unit = 1ns; precision = 1/ the task name to change default format to binary, octal or hexadecimal.
10ns;
Syntax Example 16 .1
$display (“format_string”, par_1, par_2, ... ); initial begin // c below is in submodule submod1.
$strobe (“format_string”, par_1, par_2, ... ); $displayh (b, d, submod1.c); //No format, display in hex.
15.2. Macro Definitions $monitor (“format_string”, par_1, par_2, ... ); $monitor (“time=%t, d=%h, c=%b”,
A macro is an identifier that represents a string of text. Macros are defined with the directive `define, and are invoked $displayb ( as above but defaults to binary.. $time, a, submod1.c);
with the quoted macro name as shown in the example. $strobeh (as above but defaults to hex.. end
$monitoro (as above but defaults to octal..
Syntax Example 15 .2

`define macro_name text_string; `define add_lsb a[7:0] + b[7:0]

16.2. $time, $stime, $realtime
. . . `macro_name . . . These return the current simulation time as a 64-bit integer, a 32-bit integer, and a real number, respectively. Their
assign 0 = 'add_lsb; // assign o = a[7:0] + b[7:0];
use is illustrated in Examples 4.7. and 15 .1.

16.3. $reset, $stop, $finish

15.3. Include Directive $reset resets the simulation back to time 0; $stop halts the simulator and puts it in the interactive mode where the
Include is used to include the contents of a text file at the point in the current file where the include directive is. The user can enter commands; $finish exits the simulator back to the operating system.
include directive is similar to the C/C++ include directive.

Syntax Example 15 .3
16.4. $deposit
$deposit sets a net to a particular value.
`include file_name; module x;
'include “dclr.v”; // contents of file “dclr,v” are put here Syntax Example 16 .2

$deposit (net_name, value); $deposit (b, 1’b0);

$deposit (outp, 4’b001x);// outp is a 4-bit bus

16.5. $scope, $showscope

$scope(hierarchy_name) sets the current hierarchical scope to hierarchy_name. $showscopes(n) lists all modules,
tasks and block names in (and below, if n is set to 1) the current scope.

16.6. $list
$list (hierarchical_name) lists line-numbered source code of the named module, task, function or named-block.

Thursday, October 11, 2001 9:39 pm 26 Peter M. Nyasulu Thursday, October 11, 2001 9:39 pm 27 Peter M. Nyasulu
 Introduction to Verilog Introduction to Verilog

16.10. Writing to a File; $fopen, $fdisplay, $fstrobe $fmonitor and $fwrite

16.7. $random These commands write more selectively to files.
$random generates a random integer every time it is called. If the sequence is to be repeatable, the first time one $fopen opens an output file and gives the open file a handle for use by the other commands.
invokes random give it a numerical argument (a seed). Otherwise the seed is derived from the computer clock. $fclose closes the file and lets other programs access it.
$fdisplay and $fwrite write formated data to a file whenever they are executed. They are the same except $fdisplay
Syntax Example 16 .3 inserts a new line after every execution and $write does not.
reg [3:0] xyz; $strobe also writes to a file when executed, but it waits until all other operations in the timestep are complete before
xzz = $random[(integer)]; initial begin writing. Thus initial #1 a=1; b=0; $fstrobe(hand1, a,b); b=1; will write write 1 1 for a and b.
xyz= $random (7); // Seed the generator so number $monitor writes to a file whenever any one of its arguments changes.
// sequence will repeat if simulation is restarted. See “Display Selected Variables; $display, $strobe, $monitor” on page 27 for the meaning of %h, %b etc in the
forever xyz = #20 $random; example.
// The 4 lsb bits of the random integers will transfer into the
// xyz. Thus xyz will be a random integer 0 ≤ xyz ≤ 15. Syntax Example 16 .6 Output values every clock cycle
// Test Bench
handle1=$fopen(“filenam1.suffix”) module testbench:
handle2=$fopen(“filenam2.suffix”)
16.8. $dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall reg [15:0]a; reg clk; integer hand1;
These can dump variable changes to a simulation viewer like cwaves®. The dump files are capable of dumping all the $fstrobe(handle1, format, variable list)
initial begin;
variables in a simulation. This is convenient for debugging, but can be very slow. hand1=$fopen(“datastuff.txt”);
//strobe data into filenam1.suffix forever @(posedge clk) begin
Syntax $fdisplay((handle2, format, variable list) $fstrobe (hand1, “time=%5t, a=%h, c=%b”,
Example 16 .4 //write data into filenam2.suffix $time, a, submod1.c);.
$dumpfile(“filename.dmp”) $fwrite((handle2, format, variable list) end // Never put statements after a forever block.
// Test Bench //write data into filenam2.suffix all on
$dumpvar dumps all variables in the module testbench: end
design. // one line. Put \n in the format string
reg a, b; wire c; initial begin
$dumpvar(1, top) dumps all the varia- // where a new line is desired.
initial begin; clk=0; a=8’h2b;
bles in module top and below, but not $dumpfile(“cwave_data.dmp”); forever #5 clk=~clk;
modules instantiated in top. See Sect 16.1.for examples of format.
$dumpvar //Dump all the variables end // Never put statements after a forever block
$dumpvar(2, top) dumps all the varia- // Alternately instead of $dumpvar, one could use initial begin
bles in module top and 1 level below. $dumpvar(1, top) //Dump variables in the top module. a=a+8;
$dumpvar(n, top) dumps all the varia- // Ready to turn on the dump. #3000 $fclose (hand1); // Close the file
bles in module top and n-1 levels below. $dumpon $finish;
$dumpvar(0, top) dumps all the varia- a=1; b=0; end
bles in module top and all level below. topmodule top(a, b, c); submod submod1(a, clk); // with internal variable c.
$dumpon initiates the dump. end endmodule
$dumpoff stop dumping. -------------------------------- Output ---------------------------
time= 5, a=2b, c=0
16.9. $shm_probe, $shm_open time= 10, a=2c, c=1
These are special commands for the Simulation History Manager for Cadence cwaves® only. They will save variable
changes for later display.

Syntax Example 16 .5

$shm_open (“cwave_dump.dm”) // Test Bench

$shm_probe (var1,var2, var3); module testbench:
/* Dump all changes in the above 3 varia- reg a, b; wire c;
bles. */ initial begin;
$shm_probe(a, b, inst1.var1, inst1.var2); $shm_open(“cwave_data.dmp”);
/* Use the qualifier inst1. to look inside $shm_probe(a, b, c)
the hierarchy. Here inside module
instance “inst1” the variables var1 and /* See also the testbench example in “Test Benches” on p. 30
var2 will be dumped.*/

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 Introduction to Verilog Introduction to Verilog

17.1. Synchronous Test Bench

17. Test Benches In synchronous designs, one changes the data during certain clock cycles. In the previous test bench one had to keep
counting delays to be sure the data came in the right cycle. With a synchronous test bench the input data is stored in a
A test bench supplies the signals and dumps the outputs to simulate a Verilog design (module(s)). It invokes the vector or array and one part injected in each clock cycle. The Verilog array is defined in Section 18.
design under test, generates the simulation input vectors, and implements the system tasks to view/format the results The disable statement, Sect. 16.1. can be useful in synchronous test benches.
of the simulation. It is never synthesized so it can use all Verilog commands. Synchronous test benches are essential for cycle based simulators which do not use any delays smaller than a clock
To view the waveforms when using Cadence Verilog XL Simulator, use the Cadence-specific Simulation History cycle.
Manager (SHM) tasks of $shm_open to open the file to store the waveforms, and $shm_probe to specify the varia- Things to note:
bles to be included in the waveforms list. You can then use the Cadence cwaves waveform viewer by typing cwaves Example 17 .2
data[8:1]=8'b1010_1101;
& at the UNIX prompt.
The underscore visually separates the // Synchronous test bench
bits. It is ignored by the simulator. module SynchTstBch:
Syntax Example 17 .1
reg [8:1] data;
‘timescale 1 ns /100 ps // time unit = 1ns; precision = 1/10 ns;
if (I==9) $finish; reg x,clk;
$shm_open(filename); module my_fsm_tb; // Test Bench of FSM Design of Example 14.1 When the data is used up, finish integer I;
$shm_probe(var1, var2, ...) /* ports of the design under test are variables in the test bench */
reg clk, rst, start, skip3, wait3; x<=data[I]; I<=I+1; initial begin
Note also wire Button; When synthesizing to flip-flops as in an In data[8:1]=8'b1010_1101; // Underscore spaces bits.
var=$random
an @(posedge... procedure, I=1;
wait(condition) statement /**** DESIGN TO SIMULATE (my_fsm) INSTANTIATION ****/ always use nonblocking. Without that x=0;
my_fsm dut1 (clk, rst, start, skip3, wait3, Button); you will be racing with the flip-flops in clk=0;
/**** SECTION TO DISPLAY VARIABLES ****/ the other modules. forever #5 clk= ~clk;
initial begin // Any statements placed after forever will never be reached!
$shm_open(“sim.db”); //Open the SHM database file end
/* Specify the variables to be included in the waveforms to be
viewed by Cadence cwaves */ /*** Send in a new value of x every 3rd clock cycle***/
$shm_probe(clk, reset, start); always
// Use the qualifier dut1. to look at variables inside the instance dut1. begin: data_in_proc
$shm_probe(skip3, wait3, Button, dut1.state, dut1.nxt_st); @(posedge clk)
end if (I= =9) $finish; // End simulation
@(posedge clk) // Wait here for the 2nd clock edge.
/**** RESET AND CLOCK SECTION ****/ @(posedge clk) // After the 3rd edge execute begin ...
initial begin begin
clk = 0; rst=0; #1; // Keeps data from changing on clock edge.
#1 rst = 1; // The delay gives rst a posedge for sure. x<=data[I];
#200 rst = 0; // Deactivate reset after two clock cycles +1 ns*/ I<=I+1;
end end
always #50 clk = ~clk; // 10 MHz clock (50*1 ns*2) with 50% duty-cycle end // data_in_proc
topmod top1(clk, x);
/**** SPECIFY THE INPUT WAVEFORMS skip3 & wait3 ****/
initial begin endmodule
skip3 = 0; wait3 = 0; // at time 0, wait3=0, skip3=0
#1; // Delay to keep inputs from changing on clock edge.
#600 skip3 = 1; // at time 601, wait3=0, skip3=1
#400 wait3 = 1; // at time 1001, wait3=1, skip3=0
skip3= 0;
#400 skip3 = 1; // at time 1401, wait3=1, skip3=1
wait(Button) skip3 = 0; // Wait until Button=1, then make skip3 zero.
wait3 = $random; //Generate a random number, transfer lsb into wait3
$finish; // stop simulation. Without this it will not stop.
end
endmodule

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 Introduction to Verilog

18. Memorys
18.1. Two-Dimensional Arrays
Two dimensional arrays can be declared and accessed by word. To get at a bit(s) one must equate the output to a
register or wire and select the bits from this new variable. See Example 18 .1
18.1.1 Initializing Memory From a File
The command $readmemb will read a file of binary numbers into the array. The data file consists of addresses and
data. An address written in hex as @hhh...and indicates the address of the first word in a block of data. It is followed
by binary data words separated by blanks. Legal binary bits are “0 1 x X z Z _”. Data not included in the file will be
given xxx... values. The data may be given in noncontiguous blocks if an address proceeds each block. If no initial
address is given, @000 is assumed for the first data word. Comments are allowed in data files.
If start_addr is given the memory array will be filled starting at that address and continue until finish_addr (or the
end of the array) is reached. One must have start address ≤ @hhh..., the initial address in the file.
The command $readmemh is similar except the data must contain hexadecimal numbers.
Syntax Example 18 .1
reg [wordsize:0] array [0:arraysize] reg [7:0] memry [0:31]; // 32 byte memory.
wire [7:0] memwrd;
readmemb(“file_name”, array_name); wire x;
readmemb(“file_name”, array_name, initial begin
start_addr); // Initialize memory contents from file.
readmemb(“file_name”, array_name, $readmemb(“init.dat”, memry, 8);
start_addr, finish_addrs); // words 8 and 9 are not in the file and will default to x.
end
readmemh(“file_name”, array_name); ---
// start_addr and finish addr are optional // Extract last word in memory.
assign memwrd= memry[31];
// Extract most sig bit in word 31
assign x= memwrd[7];

------------------------------- file init.dat-------------------------------

// Since start_addr =8 memry[0:9] will all be stored as xxxxxxxx.
@00A //
10101100 11110000 1x000x11 11110101 01011010 01001100
XxxxZzzz 00000000
@01E // 5'h1E = 5'd30. Underscore gives readability.
1100_1010 00011_0001

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