Master1: Electronique des systèmes embarqués UEF1.1.
1 : Electronique numérique avancée : FPGA et VHDL
Corrigé TD2 : Programmation VHDL
Exercice 1
1. Formalisme flot de données avec when-else
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
entity MUX is port(
entity exo2 is
E0, E1, E2, E3, SEL0, SEL1: in
std_logic; port(
S: out std_logic); E0, E1, E2, E3: in std_logic;
end; SEL: in std_logic_vector(1 downto 0);
S: out std_logic);
architecture FLOT_MUX of MUX is end exo2;
begin
S <= E0 when (SEL0='0' and SEL1='0') architecture FLOT_MUX of exo2 is
else begin
E1 when (SEL0='1' and SEL1='0') S <= E0 when SEL="00" else
else E1 when SEL="01" else
E2 when (SEL0='0' and SEL1='1') E2 when SEL="10" else
else E3;
E3; end FLOT_MUX;
end FLOT_MUX;
2. comportemental avec IF
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
entity exo5 is entity exo6 is
port( port(
E0, E1, E2, E3, SEL0, SEL1: in std_logic; E0, E1, E2, E3: in std_logic;
S: out std_logic); SEL: in std_logic_vector(1 downto 0);
end exo5; S: out std_logic);
end exo6;
architecture FLOT_MUX of exo5 is architecture FLOT_MUX of exo6 is
begin begin
process(SEL0, SEL1) process(SEL)
begin begin
if (SEL0='0' and SEL1='0') then S <= E0; if SEL="00" then S <= E0;
elsif (SEL0='1' and SEL1='0') then S <= E1; elsif SEL="01" then S <= E1;
elsif (SEL0='0' and SEL1='1') then S <= E2; elsif SEL="01" then S <= E2;
elsif (SEL0='1' and SEL1='1') then S <= E3; elsif SEL="11" then S <= E3;
end if; end if;
end process; end process;
end FLOT_MUX; end FLOT_MUX;
1 Corrigé TD2 : Programmation VHDL F.H
3. Structurel
-- This is the AND gate
library ieee;
use ieee.std_logic_1164.all;
entity andGate is
port( A, B, C : in std_logic;
F : out std_logic);
end andGate;
architecture func of andGate is
begin
F <= A and B and C;
end func;
--*============================
-- This is the OR gate
library ieee;
use ieee.std_logic_1164.all;
entity orGate is
port( A, B : in std_logic;
F : out std_logic);
end orGate;
architecture func of orGate is
begin
F <= A or B;
end func;
--*============================
-- This is the NOT gate
library ieee;
use ieee.std_logic_1164.all;
entity notGate is
port( inPort : in std_logic;
outPort : out std_logic);
end notGate;
--
architecture func of notGate is
begin
outPort <= not inPort;
end func;
--
*==========================*===================
======
-- Now we write the RTL definition for the 4-
to-1 Mux
library ieee;
use ieee.std_logic_1164.all;
entity Mux_4_to_1 is
port( D0, D1, D2, D3: in std_logic; -- the
data lines
S0, S1 : in std_logic; -- the selector
switches
F : out std_logic);-- the output
end Mux_4_to_1;
2 Corrigé TD2 : Programmation VHDL F.H
--
architecture Func of Mux_4_to_1 is
component andGate is --import AND
Gate entity
port( A, B, C : in std_logic;
F : out std_logic);
end component;
component orGate is --import OR
Gate entity
port( A, B : in std_logic;
F : out std_logic);
end component;
component notGate is --import NOT
Gate entity
port( inPort : in std_logic;
outPort : out std_logic);
end component;
signal invOut0, invOut1 : std_logic;
signal andOut1, andOut2, andOut3, andOut4 :
std_logic;
signal orTop, orBot, orOut : std_logic;
begin
-- Just like the real circuit, there are
-- four components: G1 to G4
GI1: notGate port map(S0, invOut0);
GI2: notGate port map(S1, invOut1);
GA1: andGate port map(invOut1, invOut0, D0,
andOut1);
GA2: andGate port map(invOut1, S0, D1,
andOut2);
GA3: andGate port map(S1, invOut0, D2,
andOut3);
GA4: andGate port map(S1, S0, D3, andOut4);
GO1: orGate port map(andOut1, andOut2,
orTop);
GO2: orGate port map(andOut3, andOut4,
orBot);
GO3: orGate port map(orTop, orBot, F);
-- F
end Func;
Deuxième méthode :
3 Corrigé TD2 : Programmation VHDL F.H
Exercice 2
Formalisme flot de données avec with-select
La table de vérité de l’équation booléenne suivante : Y A2 A1 A0 1,5,6
4 Corrigé TD2 : Programmation VHDL F.H
A2 A1 A0 Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Exercice 3
Code VHDL en utilisant génération d’instructions (FOR-GENERTE)
Méthode 2
5 Corrigé TD2 : Programmation VHDL F.H
Exercice 4
Formalisme structurel pour décrire le fonctionnement d’un registre à décalage 8 bits.
6 Corrigé TD2 : Programmation VHDL F.H
7 Corrigé TD2 : Programmation VHDL F.H
Exercice 5
Formalisme comportemental pour décrire le fonctionnement d’un compteur synchrone 3 bits
avec des bascules D
On établit un tableau de fonctionnement du compteur
Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0
Table de transition de la bascule JK
Q Q D
0 0 0
0 1 1
1 0 0
1 1 1
Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10
Q2 Q2 Q2
0 1 0 0 1 0 0 1 0 1 0 0 0 1 0
1 1 0 0 1 1 0 1 0 1 1 1 1 0 1
D0 Q0 D1 Q0 Q1 Q1 Q0 D2 Q0Q2 Q1Q2 Q2Q1Q0
8 Corrigé TD2 : Programmation VHDL F.H
Méthode 2
9 Corrigé TD2 : Programmation VHDL F.H
