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Lab Report #1

This lab report summarizes an introduction to basic logic gates and their implementation using Proteus simulation software. The document defines the logic functions of AND, OR, XOR, NAND, NOR and XNOR gates. It includes truth tables showing the output for all input combinations for each gate. The lab report describes verifying the logic gates in Proteus and presenting the simulation results to the instructor. It also gives post-lab tasks of designing NAND and NOR gates using only NOT gates.

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Muhammad Ehtisham
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88 views

Lab Report #1

This lab report summarizes an introduction to basic logic gates and their implementation using Proteus simulation software. The document defines the logic functions of AND, OR, XOR, NAND, NOR and XNOR gates. It includes truth tables showing the output for all input combinations for each gate. The lab report describes verifying the logic gates in Proteus and presenting the simulation results to the instructor. It also gives post-lab tasks of designing NAND and NOR gates using only NOT gates.

Uploaded by

Muhammad Ehtisham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Digital Logic Design

EEE241
Lab Report

Name MUHAMMAD EHTISHAM UR REHMAN

REG NO SP22-BDS-032

Class BDS-2A

Instructor’s Name Sir Asad Ali Malik


LAB # 01

Introduction to Basic Logic Gate ICs and practice on


Proteus Simulation:
Part 1: Verifying basic logic gates on proteus
AND Gate:
AND gate gives high output only when both inputs are 1, otherwise gives 0. It is
clear from the name “and”. If both a and b are true, then output is true.
Functionally: AND = a.b

A B F = A. B

0 0 0

0 1 0

1 0 0
1 1 1

OR Gate:
OR gate gives high output if any one of its inputs is 1 and even if both inputs are 1.
Only condition for or gate to give low output is when both inputs are low. As the
name “or” suggests. Input is 1 when either a or b is 1.
Functionally OR = a+b

A B F=A+B

0 0 0

0 1 1

1 0 1

1 1 1

NAND Gate:
NAND gate is negation of and gate. It gives 0 output when both of its inputs are 1
and give 1 output in all other cases.
Functionally NAND = ~(a.b)

A B F = A. B ~F

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

NOR gate:
NOR gate is negation of OR gate. It gives 1 output only when both inputs are 0,
otherwise gives 0.
Functionally NOR = ~(a+b)
A B F=A+B F’

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

XOR Gate:
XOR gate gives 1 as output when either one of the inputs is 1 and other is 0. It
gives 0 if inputs are same. In case of inputs more than 2, even 1’s make output 0
and odd 1’s make output 1.
Functionally XOR = (a.~b) + (~a.b)
A B F = AB’ + A’B

0 0 0

0 1 1

1 0 1

1 1 0

XNOR Gate:
XNOR gate is negation of XOR gate. It gives high output when both inputs are 1 or
in case of more than 2 inputs, even inputs are 1.
Functionally XNOR = ~((a.~b) +(~a.b))
A B F = AB’ + A’B ~F

0 0 0 1

0 1 1 0

1 0 1 0

1 1 0 1

Part 2:
Verify all the basic logic gates using the Proteus simulation tool and note down the
values in the Tables 1.10 & 1.11 with the corresponding logic symbol and Boolean
function. Then show the simulated logic circuit diagrams to your Lab Instructor.

Truth Table:
A B AND OR XOR NAND NOR XNOR

0 0 0 0 0 1 1 1

0 1 0 1 1 1 0 0

1 0 0 1 1 1 0 0

1 1 1 1 0 0 0 1

Observation table for not gate:


INPUT OUTPUT

𝑨 𝑩

0 1

1 0

Post lab task:


Part 1: Design NAND gate using NOT gate
A B F = A. B ~F

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

Part 2: Design NOR gate using NOT gate


A B F=A+B ~F

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

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