Module 1- Chapter 1: Questions

1. Explain the Functions of Processor Register with a block diagram? (8M)

 OR
1. Explain the functions of following processor registers with respect to a
computer? (12M)
(i) MAR ii) MDR iii) IR iv) PC V) ALU
• The processor contains ALU, control-circuitry and many registers.
• The instruction-register(IR) holds the instruction that is currently being
executed.
• The instruction is then passed to the control-unit, which generates the timing-
signals that determine when a given action is to take place
• The PC(Program Counter) contains the memory-address of the next-instruction
to be fetched & executed. It keeps track execution of the program.
• During the execution of an instruction, the contents of PC are updated to point
to next instruction.
• The processor also contains „n‟ general-purpose registers R0 through Rn-1.
• The MAR (Memory Address Register) holds the address of the memory-
location to be accessed.
• The MDR (Memory Data Register) contains the data to be written into or read
out of the addressed location.
• In computing, an arithmetic logic unit (ALU) is a combinational digital
circuit that performs arithmetic and bitwise operations on integer binary
numbers
2. What is a Bus? Explain single bus and multiple Bus structures used to
interconnect functional units in a computer system. (8M)
• To achieve a reasonable speed of operation, a computer must be organized so
that all its units can handle one full word of data at a given time. A bus is a
group of lines that serves as a connecting path for several devices.
• A bus may be lines or wires.
• The lines carry data or address or control signal.
• There are 2 types of Bus structures: 1) Single Bus Structure and 2) Multiple Bus
Structure.
1) Single Bus Structure
➢ Because the bus can be used for only one transfer at a time, only 2 units can
actively use the bus at any given time.
➢ Bus control lines are used to arbitrate multiple requests for use of the bus.
➢ Advantages:
1) Low cost &
2) Flexibility for attaching peripheral devices.
2) Multiple Bus Structure
➢ Systems that contain multiple buses achieve more concurrency in operations.
➢ Two or more transfers can be carried out at the same time.
➢ Advantage: Better performance.
 ➢ Disadvantage: Increased cost.

• The devices connected to a bus vary widely in their speed of operation.

• To synchronize their operational-speed, buffer-registers can be used.
• Buffer Registers
→ are included with the devices to hold the information during transfers.
→ prevent a high-speed processor from being locked to a slow I/O device
during data transfers.

3. How to prevent high speed processor from being locked to a slow input/output
device during data transfer? (6M)

4. What are the factors used to judge the performance of a computer? Explain any
3 of them.(10M)
PROCESSOR CLOCK
• The processor circuits are controlled by timing signals called as Clock.
• It defines constant time intervals and are called as Clock Cycles.
• To execute one instruction there are 3 basic steps namely (fetch, decode and
execute).
• The performance of the processor depends on the length of the clock cycle. To
obtain high performance reduce the length of the clock cycle. Let ‘ P ’ be the
number of clock cycles generated by the Processor and ‘ R ‘ be the Clock rate .
• The Clock rate is inversely proportional to the number of clock cycles.i.e R =
1/P.

BASIC PERFORMANCE EQUATION

• Let ‘ T ‘ be total time required to execute the program.
‘N ‘ be the number of instructions contained in the program.
S ‘ be the average number of steps required to one instruction.
R’ be number of clock cycles per second generated by the processor to execute one
program. T=N*S/R
This equation is called as Basic Performance Equation.
• For the programmer the value of T is important. To obtain high performance it
is necessary to reduce the values of N and S and to increase the value of R.
 CLOCK RATE
There are 2 possibilities for increasing the clock rate R.
i)Improving the integrated circuit technology(IC) makes logic circuit faster ,
which reduce the time needed to complete basic step. This allows clock period P
to be reduced and clock rate R to be R to be increased.
ii) Reducing the amount of processing done in one basic step , also makes it
possible to reduce the clock period P.
• In the presence of a cache , the percentage of accesses to the main memory is
small.Hence , much of the performance gain expected from the use of faster
technology can be realized. The value of T will be reduced by the same factor as
R is increased because S and N are not affected.
PERFORMANCE MEASUREMENT
• The performance measure is the time taken by the computer to execute a given
bench mark.
• A non profit organization called SPEC( system performance evaluation
corporation) selects and publishes bench marks.

If the SPEC rating = 50 Means that the computer under test is 50 times as fast as
the ultra sparc 10
• The SPEC repeated for all the programs in the SPEC suit, and the geometric
mean of the result is computed.
• Let SPECi be the rating for program ‘i’ in the suite. The overall SPEC rating for
the computer is given by

(Where ‘n’ = number of programs in suite.

5. Define the following: (8M)
i) Processor clock ii) Clock rate iii) Elapsed time iv) Processor time
The total time required to execute the program is elapsed time is a
measure of the performance of the entire computer system. It is affected by the
speed of the processor, the disk and the printer. The time needed to execute a
instruction is called the processor time.

Module -1 (Chapter 2) Question Bank

1. Explain memory locations and addresses?

• Memory consists of many millions of storage cells (flip-flops).
• Each cell can store a bit of information i.e. 0 or 1 (Figure).
• Each group of n bits is referred to as a word of information, and n is called
the word length.
• The word length can vary from 8 to 64 bits.
• A unit of 8 bits is called a byte.
• Accessing the memory to store or retrieve a single item of information
(word/byte) requires distinct addresses for each item location. (It is
customary to use numbers from 0 through 2ˆk-1 as the addresses of
successive-locations in the memory).
• If 2ˆk = no. of addressable locations;
then 2ˆk addresses constitute the address-space of the computer.
For example, a 24-bit address generates an address-space of 2ˆ24 locations
(16 MB).
2.
3. Explain the following
BYTE-ADDRESSABILITY
A byte is always 8 bits, but the word length typically ranges from 16 to 64 bits.
• In byte-addressable memory, successive addresses refer to successive byte
locations in the memory.
• Byte locations have addresses 0, 1, 2. . . . .
• If the word-length is 32 bits, successive words are located at addresses 0, 4,
8. . with each word having 4 bytes.
There are two ways in which byte addresses are arranged
1) BIG-ENDIAN: lower byte addresses are used for the more significant
bytes (the leftmost bytes) of the word.
2) LITTLE-ENDIAN: lower byte addresses are used for the less significant
bytes (the rightmost bytes) of the word.
The same ordering is also used for labeling bits within a byte, that is, b7, b6,
…., b0, from left to right.

• Consider a 32-bit integer (in hex): 0x12345678 which consists of 4 bytes:

12, 34, 56, and 78.
➢ Hence this integer will occupy 4 bytes in memory.
➢ Assume, we store it at memory address starting 1000.
➢ On little-endian, memory will look like
 Addre Valu
ss e
1000 78
1001 56
1002 34
1003 12

➢ On big-endian, memory will look like

Addre Valu
ss e
1000 12
1001 34
1002 56
1003 78

Byte and word addressing

4. With a memory layout starting at address ‘i’ represent how “ABCD” data is
stored in Big- Endian and Little - Endian Assignment scheme in a system of
word length 16 bits.
5. Explain two Basic Memory Operations?
Two basic operations involving the memory are needed:
• LOAD(Read or Fetch): The load operation transfers a copy of the
contents of a specific memory location to the processor. The memory
contents remain unchanged.
• STEPS
(1) Processor sends the address of the desired location to the memory
(2) Processor issues “read‟ signal to memory to fetch the data .
(3) Memory reads the data stored at that address.
 (4) Memory sends the read data to the processor. Processor sends the
address of the desired location to the memory and requests that its
contents be read.
(5) The memory reads the data stored at that address and sends them
to the processor.
• STORE(Write): The store operation transfers an item of information
from the processor to a specific memory location, destroying the former
contents of that location.
• STEPS
(a) Processor sends the address of the memory location where it
wants to store data.
(b) Processor issues „write‟ signal to memory to store the data.
(c) Content of register(MDR) is written into the specified memory
location The processor sends the address of the desired location
to the memory.

6. Explain Register Transfer Notation and Assembly Language Notation?

REGISTER TRANSFER NOTATION (RTN)
• Possible locations which transfers of information occurs memory
locations, processor registers, or registers in the I/O subsystem.
• We identify a memory location by a symbolic name (in uppercase
alphabets).
For example, LOC, PLACE, NUM etc indicate memory
locations.R0, R5 etc indicate processor register. DATAIN,
OUTSTATUS etc indicate I/O registers.
• For example,
R<-[LOC] means that the contents of memory location LOC are transferred
into processor register R1 (The contents of a location are denoted by placing
square brackets around the name of the location). R3<-[R1]+[R2] indicates the
operation that adds the contents of registers R1 and R2 ,and then places their
sum into register R3.
• This type of notation is known as RTN(Register Transfer Notation).
ASSEMBLY LANGUAGE NOTATION
To represent machine instructions and programs, assembly language format can
be used.
• For example,
i) Move LOC, R1;
This instruction transfers data from memory-location LOC to
processor-register R1. The contents of LOC are unchanged by the
 execution of this instruction, but the old contents of register R1 are
overwritten.
ii) Add R1, R2, R3;
This instruction adds 2 numbers contained in processor-registers R1 and
R2, and places their sum in R3.
• A computer performs its task according to the program stored in memory.
A program is a collection of instructions which tell the processor to
perform a basic operation like addition, reading from keyboard etc.
• Possible locations that may be involved in data transfers are memory
locations, processor registers or registers in the I/O subsystem.

7. Write a Program to Evaluate the Arithmetic Statement using Three-Address,

Two-Address, One-Address and Zero-Address Instructions.
i) Y= (A+B) *(C+D) ii) C=A+B iii) X = A*B + C*D
8. Explain Instruction Execution and Straight-line Sequencing?
The program is executed as follows:
1) Initially, the address of the first instruction is loaded into PC (Program
counter is a register which holds the address of the next instruction to be
executed)
2)Then, the processor control circuits use the information in the PC to
fetch and execute instructions, one at a time, in the order of increasing
addresses. This is called straight-line sequencing (Figure)
3) During the execution of each instruction, the PC is incremented by 4 to
point to the next instruction.

✓ Executing given instruction is a two-phase procedure

 i)In fetch phase, the instruction is fetched from the memory location
(whose address is in the PC) and placed in the IR of the processor
ii) In execute phase, the contents of IR is examined to determine
which operation is to be performed. The specified operation is then
performed by the processor.
BRANCHING
• Consider the task of adding a list of n numbers.
• The number of entries in the list n is stored in memory location N.
(Figure 2.10).
• Register R1 is used as a counter to determine the number of time the loop
is executed.
• The contents of location N are loaded into register R1 at the beginning of
the program.
• The loop is a straight line sequence of instructions executed as many
times as needed. It starts at location LOOP and ends at the instruction
Branch>0.
• During each pass through this loop,
▪ the address of the next list
entry is determined
• entry is fetched and added
to R0.
• The instruction Decrement R1 reduces the contents of R1 by 1 each time
through the loop. Then Branch instruction loads a new value into the
program counter. As a result, the processor fetches and executes the
instruction at this new address called the branch target.
✓ A conditional branch instruction causes a branch only if a specified
condition is satisfied. If the condition is not satisfied, the PC is
incremented in the normal way, and the next instruction in sequential
address order is fetched and executed.
9. What are Condition Code Flags? Explain four commonly used Flags.
The processor keeps track of information about the results of various operations. This is
accomplished by recording the required information in individual bits, called condition
code flags.
✓ These flags are grouped together in a special processor-register called the condition
code register (or statue register).
✓ Four commonly used flags are
→ N (negative) set to 1 if the result is negative, otherwise cleared to 0
→ Z (zero) set to 1 if the result is 0; otherwise, cleared to 0
→ V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0
→ C (carry) set to 1 if a carry-out results from the operation; otherwise cleared to 0
10. What is an Addressing Mode? Explain different Generic addressing mode with
an example for each.

IMPLEMENTATION OF VARIABLE AND CONSTANTS

• Variable is represented by allocating a register or memory location to hold its value.
 • The value can be changed as needed using appropriate instructions.
• There are 2 accessing modes to access the variables.
Register mode
✓ The operand is the contents of a register.
✓ The name (or address) of the register is given in the instruction.
✓ Registers are used as temporary storage locations where the data in a register are
accessed.
✓ For example, the instruction,
Move R1, R2 Copy content of register R1 into register R2
Absolute mode
✓ The operand is in a memory-location.
✓ The address of memory-location is given explicitly in the instruction.
✓ For example, the instruction,
Move LOC, R2 ; Copy content of memory-location LOC into register R2
Immediate Mode
✓ The operand is given explicitly in the instruction.
✓ For example, the instruction,
Move #200, R0 ;Place the value 200 in register R0
✓ Clearly, the immediate mode is only used to specify the value of a
source-operand.
INDIRECTION AND POINTERS
✓ The instruction does not give the operand or its address explicitly.
✓ It provides information from which the memory-address of the operand can be
determined.
✓ This address as the effective address(EA) of the operand.
Indirect Mode
✓ The EA of the operand is the contents of a register(or memory-location) whose
address appears in the instruction.
✓ The register (or memory-location) that contains the address of an operand is called a
pointer. {The indirection s denoted by ( ) sign around the register or memory-
location.
E.g: Add (R1),R0;The operand is in memory. Register R1 gives the effective-
address(B) of the operand. The data is read from location B and added to contents of
register R0
 ✓ To execute the Add instruction in fig (a), the processor uses the value which is in
register R1, as the EA of the operand.
✓ It requests a read operation from the memory to read the contents of location B. The
value read is the desired operand, which the processor adds to the contents of register
R0.
✓ Indirect addressing through a memory location is also possible as shown in fig (b). In
this case, the processor first reads the contents of memory location A, then requests a
second read operation using the value B as an address to obtain the operand.

➢ In above program, Register R2 is used as a pointer to the numbers in the list, and the
operands are accessed indirectly through R2.
➢ The initialization-section of the program loads the counter-value n from memory-
location N into R1 and uses the immediate addressing-mode to place the address
value NUM1, which is the address of the first number in the list, into R2. Then it
clears R0 to 0.
➢ The first two instructions in the loop implement the unspecified instruction block
starting at LOOP.
➢ The first time through the loop, the instruction Add (R2), R0 fetches the operand at
location NUM1 and adds it to R0.
➢ The second Add instruction adds 4 to the contents of the pointer R2, so that it will
contain the address value NUM2 when the above instruction is executed in the second
pass through the loop.
INDEXING AND ARRAYS
✓ A different kind of flexibility for accessing operands is useful in dealing with lists and
arrays.
Index mode
✓ The operation is indicated as X(Ri) where X=the constant value contained in the
instruction Ri=the name of the index register
✓ The effective-address of the operand is given by EA=X+[Ri].
✓ The contents of the index-register are not changed in the process of generating the
effective address.
✓ In an assembly language program, the constant X may be given either → as an
explicit number or
→ as a symbolic-name representing a numerical value.

✓ Fig(a) illustrates two ways of using the Index mode. In fig(a), the index register, R1,
contains the address of a memory location, and the value X defines an offset(also
called a displacement) from this address to the location where the operand is found.
✓ An alternative use is illustrated in fig(b). Here, the constant X corresponds to a
memory address, and the contents of the index register define the offset to the
operand. In either case, the effective address is the sum of two values; one is given
explicitly in the instruction, and the other is stored in a register.

Base with Index Mode

➢ Another version of the Index mode uses 2 registers which can be denoted as (Ri, Rj)
➢ Here, a second register may be used to contain the offset X.
 ➢ The second register is usually called the base register.
➢ The effective-address of the operand is given by EA=[Ri]+[Rj]
➢ This form of indexed addressing provides more flexibility in accessing operands,
because both components of the effective address can be changed.
Base with Index & Offset Mode
➢ Another version of the Index mode uses 2 registers plus a constant, which can be
denoted as X(Ri, Rj)
➢ The effective-address of the operand is given by EA=X+[Ri]+[Rj]
➢ This added flexibility is useful in accessing multiple components inside each item in a
record, where the beginning of an item is specified by the (Ri, Rj) part of the
addressing-mode. In other words, this mode implements a 3-dimensional array.

RELATIVE ADDRESSING MODE

➢ This is similar to index-mode with an exception: The effective address is determined
using the PC in place of the general purpose register Ri. ➢ The operation is indicated
as X(PC).
➢ X(PC) denotes an effective-address of the operand which is X locations above or
below the current contents of PC.
➢ Since the addressed-location is identified "relative" to the PC, the name Relative
mode is associated with this type of addressing.
➢ This mode is used commonly in conditional branch instructions.
➢ An instruction such as Branch > 0 LOOP ; Causes program execution to go to
the branch target location identified by name LOOP if branch condition
is satisfied.

ADDITIONAL ADDRESSING MODES

The following 2 modes are useful for accessing data items in successive locations in the
memory. Auto-increment Mode
➢ The effective-address of operand is the contents of a register specified in the
instruction (Fig:
2.16).
➢ After accessing the operand, the contents of this register are automatically
incremented to point to the next item in a list.
➢ Implicitly, the increment amount is 1.
➢ This mode is denoted as
(Ri)+ ;where Ri=pointer register
 Auto-decrement Mode
➢ The contents of a register specified in the instruction are first automatically
decremented and are then used as the effective address of the operand.
➢ This mode is denoted as
-(Ri) ;where Ri=pointer register ➢ These 2 modes can be
used together to implement an important data structure called a stack.

11. What are Assembler Directives? Point out and explain the various directives
with example.

12. Write an Assembly program that reads a line of characters and display it.
13. Explain Basic I/O Operations performed by the processor, with the help of neat
diagram.
14. Explain Memory Mapped I/O and Program Controlled I/O Operation?
15. Explain Stack and Queue? Differentiate between them? Write the line of code to
implement the same.
16. Define Subroutine and Subroutine Linkage? Explain Subroutine Linkage using
Link Register.
A subtask consisting of a set of instructions which is executed many times is called a
subroutine.
The program branches to a subroutine with a Call instruction (Figure: 2.24).

Once the subroutine is executed, the calling-program must resume execution starting
from the instruction immediately following the Call instructions i.e. control is to be
transferred back to the calling-program. This is done by executing a Return instruction at
the end of the subroutine.

The way in which a computer makes it possible to call and return from subroutines is
referred to as its subroutine linkage method.

The simplest subroutine linkage method is to save the return-address in a specific

location, which may be a register dedicated to this function. Such a register is called the
link register.
 When the subroutine completes its task, the Return instruction returns to the calling-
program by branching indirectly through the link-register.

The Call instruction is a special branch instruction that performs the following
operations:
→ Store the contents of PC into link-register.

→ Branch to the target-address specified by the instruction.

17. The Return instruction is a special branch instruction that performs the operation:
→ Branch to the address contained in the link-register.

18. What is Subroutine? How to pass parameters to subroutines? Illustrate with an

Example.
 The exchange of information between a calling-program and a subroutine is referred
to as parameter passing (Figure: 2.25).
• The parameters may be placed in registers or in memory-location, where they can be
accessed by the subroutine.
• Alternatively, parameters may be placed on the processor-stack used for saving the
return-address
• Following is a program for adding a list of numbers using subroutine with the parameters
passed through registers.
19. Explain Subroutine Nesting?
• Subroutine nesting means one subroutine calls another subroutine.
• In this case, the return-address of the second call is also stored in the link-register,
destroying its previous contents.

• Hence, it is essential to save the contents of the link-register in some other location before
calling another subroutine. Otherwise, the return-address of the first subroutine will be lost.

• Subroutine nesting can be carried out to any depth. Eventually, the last subroutine called
completes its computations and returns to the subroutine that called it.

• The return-address needed for this first return is the last one generated in the nested call
sequence. That is, return-addresses are generated and used in a LIFO order.

• This suggests that the return-addresses associated with subroutine calls should be pushed
onto a stack. A particular register is designated as the SP(Stack Pointer) to be used in this
operation.

• SP is used to point to the processor-stack.

• Call instruction pushes the contents of the PC onto the processor-stack. Return instruction
pops the return-address from the processor-stack into the PC.

20. Explain the concept of Stack Frames, when subroutines are nested.
• Stack frame refers to locations that constitute a private work-space for the subroutine
(Figure:2.26).

•The work-space is
→ created at the time the subroutine is entered &
→ freed up when the subroutine returns control to the calling-program.

• Following is a program for adding a list of numbers using subroutine with the parameters
passed to stack.

• Fig: 2.27 show an example of a commonly used layout for information in a stack-frame.

•Frame pointer(FP) is used to access the parameters passed → to the subroutine &
→ to the local memory-variables

• The contents of FP remains fixed throughout the execution of the subroutine, unlike stack-
pointer SP, which must always point to the current top element in the stack.
Operation on Stack Frame
• Initially SP is pointing to the address of old TOS.

• The calling-program saves 4 parameters on the stack (Figure 2.27).

• The Call instruction is now executed, pushing the return-address onto the stack.
• Now, SP points to this return-address, and the first instruction of the subroutine is executed.

• Now, FP is to be initialized and its old contents have to be stored. Hence, the first 2
instructions in the subroutine are:
Move
FP,-
(SP)
Move
SP,FP
• The FP is initialized to the value of SP i.e. both FP and SP point to the saved FP address.
 •The 3 local variables may now be pushed onto the stack. Space for local variables is
allocated by executing the instruction
Subtract #12,SP

• Finally, the contents of processor-registers R0 and R1 are saved in the stack. At this point,
the stackframe has been set up as shown in the fig 2.27.

•The subroutine now executes its task. When the task is completed, the subroutine pops the
saved values of R1 and R0 back into those registers, removes the local variables from the
stack frame by executing the instruction.
Add #12,SP

• And subroutine pops saved old value of FP back into FP. At this point, SP points to return-
address, so the Return instruction can be executed, transferring control back to the calling
program.

21.
22. What is the need of Processor Stack? Explain a commonly used layout for
information in a subroutine stack frame.
23. Interpret the Subroutine Stack frame with example.
24. How Parameters are passed to subroutine?
25. What is Stack Frame? Explain Subroutine stack frame.
26. Explain the use of Stack Frame in the implementation of Nesting of Subroutine?
27. Stack is very useful data structure for holding return-addresses when subroutines are
nested.
 28. When nested subroutines are used; the stack-frames are built up in the processor-
stack.
29. Consider the following program to illustrate stack frames for nested subroutines (refer
fig no. 2.28 from text book).

The Flow of Execution is as follows:

30. Main program pushes the 2 parameters param2 and param1 onto the stack and then
calls SUB1.
31. SUB1 has to perform an operation & send result to the main-program on the stack
(Fig:2.28& 29).
 32. During the process, SUB1 calls the second subroutine SUB2 (in order to perform
some subtask).
33. After SUB2 executes its Return instruction; the result is stored in register R2 by
SUB1.

34. SUB1 then continues its computations & eventually passes required answer back to
main-program on the stack.
When SUB1 executes return statement, the main-program stores this answers in memory-
location RESULT and continues its execution.

35. Point out various Shifts and Rotate Instruction and example, with a neat
diagram.
36. Explain Shift, Rotate and Logical operation with an example?
37. How to Encode Assembly Instructions into 32-bit words? Explain with
examples.
38. With relevant examples briefly explain about any 2 Encoding types of Machine
Instruction.
39. With the help of suitable example, illustrate Encoding of Machine Instructions
40. What is the effective address of the source operand in each of the following
instruction.
When the Register R1 and R2 of computer contain the decimal value 1200 and

4600? i) Load 20(R1), R5 ii) Move #3000, R5 iii) Store R5,

30(R1, R2) iv) Add – (R2), R5 v) Subtract (R1)+, R5

41. Write a program to add N numbers using indirect addressing mode and auto
increment mode?
42. Write a routine to compare whether the most significant char is Z or not.
43. Write a routine to pack 2 BCD digits and explain with an example.