Lecture 3 & 4 - Data Link Layer in CAN - Recessive and Dominant Bits, Arbitration, Frame Structure
Lecture 3 & 4 - Data Link Layer in CAN - Recessive and Dominant Bits, Arbitration, Frame Structure
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Lecture 3.
Data Link Layer in CAN: Recessive and
Dominant bits, Arbitration, Frame Structure:
standard and extended frames (CAN 2.0A and
CAN 2.0 B), Bit Stuffing, Error Detection, Error
Management (Error passive, error active and
bus-off states)
General Setting: Distributed Control System (DCS)
Desired features:
Communication is message oriented
and not target oriented (the same
message is likely to be of interest for
multiple endpoints)
Supports broadcast, multicast: a
controller can use the sensors from
other controller as its own
Real-time: rapidly changing information
has to be transmitted faster than other
(e.g. engine load changes rapidly than
temperature)
Entire bus capacity is used to sent the
most relevant information at some point
(DoS due to traffic overload is not
possible)
Does not require physical destination addresses
Easy to add nodes without hardware or software modifications to existing nodes2
With respect to these, the CAN
Standard from Bosch specifies
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Comparison of CAN architecture
with the OSI/ISO
Application (can implement in software absent layers)
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Bit representation: dominant and
recessive bits
Dominant bits can overwrite recessive bits
In CAN: 0 – dominant, 1 – recessive
Some physical examples:
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Bit Stuffing
CAN bit stuffing rule: after 5 consecutive bits of identical value 1
bit of the opposite value is added
De-stuffing has to be done at reception
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Arbitration Field
Identifier 11 bit:
Lower the value higher the priority
The first 7 bits must not be all recessive => 2032 maximum combinations
Remote Transmission Request RTR bit:
dominant in data frames
recessive in remote frames
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Control Field
The first 2 bits reserved for upward compatibility
Identifier Extension bit – dominant is Standard CAN frame is used
r0 bit - reserved
The last 4 bits indicate the data length
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Note that 4 bits indicate 16 possible data
lengths and only 9 lengths are used in CAN
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Data Field
At most 8 bytes of actual data
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CRC Field
15 bits with Hamming distance 6
1 bit CRC delimiter (always recessive)
Must detect:
up to 5 randomly distributed (independent) errors in a message are detected
burst errors of length less than 15 in a message are detected
errors of any odd number in a message are detected
Total residual error probability for undetected corrupted messages: less than
message error rate 4.7 * 10-11
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BCH (Bose and Ray-Chaudhuri)
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ACK Field
1 ACK slot recessive, overwritten by a dominant bit
1 ACK delimiter, always recessive
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End of Frame Field (EOF)
Just 7 recessive bits
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See the big picture
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Remote Frame
RTR bit is recessive
Data is 0 bytes
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CAN 2.0 B frame
Extended CAN, uses 29 bit identifiers
SRR – substitute remote request bit
IDE is recessive
Remark: Since the SRR bit is received before the IDE bit, a receiver cannot decide
instantly whether it receives a RTR or a SRR bit. That means only the IDE bit
decides whether the frame is a Standard Frame or an Extended Frame.
… see pictures below
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CAN 2.0 A – CAN 2.0 B interoperability
CAN 2.0 B controllers must support standard CAN frames
CAN 2.0 B Active – can read/write CAN 2.0B frames
CAN 2.0 B Passive – can read CANB 2.0 frames
CAN 2.0 B can work with standard or extended frames at the same time
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CAN bit stuffing Revisited
The maximum size of the stuffing area: 98 bits => maximum 19 stuff bits
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CAN frame overhead
Overhead: Data size / Frame size (consider also bit stuffing)
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60
50
40
30
20
10
0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
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… and another example
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Arbitration: Standard Frame vs.
Extended Frame
Standard frame wins
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Arbitration type
ND + CSMA/CA + AMP
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Timing Considerations
Can we compute the maximum delay at which a particular
message will arrive ?
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Timing Considerations
Can we compute the maximum delay at which a particular
message will arrive ?
Only for the highest priority message
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Questions
Which is the worst time interval at which
an interrupt for a receive routine is
triggered ?
How fast will the highest priority message
arrive ?
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Data rate revisited
Data rate = useful data rate from the entire frame at 1Mbps
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Error Detection
Five types of errors are defined on CAN Standard:
1) BIT ERROR - A unit that is sending a bit on the bus also monitors the bus. A
BIT ERROR has to be detected at that bit time, when the bit value that is
monitored is different from the bit value that is sent. An exception is the
sending of a ’recessive’ bit during the stuffed bit stream of the ARBITRATION
FIELD or during the ACK SLOT. Then no BIT ERROR occurs when a
’dominant’ bit is monitored. A TRANSMITTER sending a PASSIVE ERROR
FLAG and detecting a ’dominant’ bit does not interpret this as a BIT ERROR.
2) STUFF ERROR - A STUFF ERROR has to be detected at the bit time of the
6th consecutive equal bit level in a message field that should be coded by the
method of bit stuffing.
3) CRC ERROR - The CRC sequence consists of the result of the CRC
calculation by the transmitter The receivers calculate the CRC in the same way
as the transmitter. A CRC ERROR has to be detected, if the calculated result is
not the same as that received in the CRC sequence.
4) FORM ERROR - A FORM ERROR has to be detected when a fixed-form bit
field contains one or more illegal bits.
5) ACKNOWLEDGMENT ERROR - An ACKNOWLEDGMENT ERROR has to be
detected by a transmitter whenever it does not monitor a ’dominant’ bit during
the ACK SLOT.
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When is a message valid ?
The point of time at which a message is taken to be valid, is
different for the transmitter and the receivers of the message:
Transmitter:
The message is valid for the transmitter, if there is no error until the end
of END OF FRAME. If a message is corrupted, retransmission will follow
automatically and according to prioritization. In order to be able to
compete for bus access with other messages, retransmission has to start
as soon as the bus is idle.
Receivers:
The message is valid for the receivers, if there is no error until the last
but one bit of END OF FRAME.
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Error Limitation
To prevent a permanently disturbed bus each CAN
controller has 3 states:
1) Error active - an ’error active’ unit can normally take part in
bus communication and sends an ACTIVE ERROR FLAG
when an error has been detected.
2) Error passive - an ’error passive’ unit must not send an
ACTIVE ERROR FLAG. It takes part in bus communication
but when an error has been detected only a PASSIVE
ERROR FLAG is sent. Also after a transmission, an ’error
passive’ unit will wait before initiating a further transmission.
(See SUSPEND TRANSMISSION)
3) Bus off - a ’bus off’ unit is not allowed to have any influence
on the bus. (E.g. output drivers switched off.)
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CAN node states
Error passive and error active
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Evolution of error counters (example)
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Tx Error counter modifications
(brief and incomplete)
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Rx error counter modifications (in
brief)
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Efficiency of Error Management
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Error Counters Modification Rules
According to CAN Spec (note that more than 1 rule can be applied)
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Example 1
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Example 1
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Example 2
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Example 2
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Lecture 4.
Physical Layer in CAN: Implementation
aspects and bit timing procedures, hardware
synchronization and resynchronization, high
speed and fault tolerant CAN, theoretical
limitations of CAN speed, oscillator tolerance
for CAN networks
ISO 11898-5 specifies the CAN
physical layer
Recessive condition: if CAN-H is not higher than CAN-L plus
0.5 V
Dominant condition: if CAN-H is at least 0.9 V higher than
CAN-L
Each node must be capable to produce output voltage between
1.5V and 3.0V
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Parret, 2007:
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The ZK-S12-B Starter Kit
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Fault-tolerant CAN transceiver
Philips Double Wire TJA1054 CAN Transceiver
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Fault tolerant transceivers specifications
Low speed, data rates up to 125 kbit/s and uo to 32 nodes
Detect and handle the following bus error conditions:
Interruption on CAN-H
Interruption on CAN-L
Short circuit of CAN-H with VCC
Short circuit of CAN-H with GND
Short circuit of CAN-L with VCC
Short circuit of CAN-L with GND
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Bus wiring
120 ohm termination resistor (not needed for
TJA1054)
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CAN Connector according to CIA recommendation
Can-in-Automation (CIA) DS-102 – CAN physical layer for
industrial applications
9 pin D-SUB connector
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Bit Time and Nominal Bit Time
Bits are encoded with NRZ – main issue: lack of
synchronization
Bit Time = the period of time for which the bit is present on the
bus
Nominal Bit Time = the theoretical period of time for which the
bit is present on the bus
1
NominalBitTime=
NominalBitRate
Nominal bit time is divided in 4 parts
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Synchronization segment
Used to synchronize all nodes, the leading edge of an
incoming bit should appear within this segment
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Propagation Time Segment
Used to compensate the delays on the network (twice the
transmission plus propagation time)
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Phase Buffer Segment 1 and 2
Used to compensate for edge phase errors (mostly due to small frequency
variations in the oscilators)
Designed to be extended or shortened by resynchronization procedure
Sample Point = the point at which the bus level is read (located at the
boundary between TSGE1 and TSEG2), two relevant issues:
Must be as late as possible - to overcome delays and have maximum
confidence on the value
Must not be too late – time is also needed to compute the actual value
=> The Sampling Point must be towards the end of a bit period
Information Processing Time = the time segment starting with the Sample
Point (TSEG 2)
Multiple sampling is available on some circuits: a but can be sampled more
than once (e.g., odd number of time and use majority logic)
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Computing the Nominal Bit Time
Minimum Time Quantum – generally derived from the
station’s clock
Time Quantum of the Bit Time – derived from the minimum
time quantum by the use of dividers (division in the range
from 1 to 32)
TimeQuantum=m MinimumTimeQuantum
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Length of Time Segments
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An example from [Parret, 2007]
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And another example …
Note that on some microcontrollers one can set only TSEG1
and TSEG2, in this case TSEG1 must include the
propagation time
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Exact computation for time segments
length
Synchronization Segment – 1 time quanta
Propagation Speed Segment – depends on the transmission delay caused
by:
Medium
Topology
Electrical parameters
Quality of signal
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Detailed computation of propagation time
The following delays must be added:
The delay required by the controller to output the signal
The delay required by the transceiver to generate the signal
The time to transport the signal
The time required by the reception transceiver to send the signal to the controller
The time required by the controller to process the signal
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Can be further synthesized in two types of delays
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The delayed caused by the electronic components has the
following components:
Tsd – the delay caused by the CAN controller
Trx, Ttx – the delay caused by the transceiver
Tqual – the delay caused by imperfections in the signal
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The delayed caused by the medium is determined by the
length of the medium and the propagation speed:
L
Tmed
v prop
seg
prop min 2 Tmed Tsd Ttx Trx Tqual
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Relations between maximum bit-
rate and length of the network
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We now that the propagation segment must be at least twice the delay,
assume that this segment is only x percents of the bit time, then we have:
seg
prop min xTbit 2Tprop 2 Tmed Tsd Ttx Trx Tqual
L 0.2mns 1 x
2 BaudRate
Telec
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Bit Synchronization
Hardware Synchronization
Internal bit-time started in SYNC_SEG
Forces the edge that caused Hard Synchronization
to lie in SYNC_SEG
Resynchronization
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Synchronization rules
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Resynchronization
PHASE_SEG1 may be lengthen or PHASE_SEG1 may be
shortened
The amount of lengthening/shortening is given by
RESYNCHRONIZATION JUMP WIDTH
RESYNCHRONIZATION JUMP WIDTH = min(4,
PHASE_SEG1)
The maximum length between 2 transitions that can be used for
resynchronization is 29 bit times
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Phase Error
Phase Error of an Edge = difference in
time quanta between the position of the
edge and SYNC_SEG:
e=0 lies in SYNC_SEG
e>0 lies before the SAMPLEPOINT
e<0 lies after the SAMPLEPOINT
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Resynchronization Rules
Two cases
i) If PHASE ERROR is smaller (or equal) then
RSJW the effect is the same of a HARD
Synchronization
ii) If PHASE ERROR greater then RSJW then
If PE > 0 then PHASE_SEG1 lengthened by RSJW
If PE < 0 then PHASE_SEG2 is shortened by RSJW
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Effects of the oscillator frequencies
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Estimation of RJW
If x is the oscillator tolerance then for one bit the
synchronization jump must be (explain why 2):
x
RJW 2 Tbit
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CAN standard specifies that resynchronization must be feasible
after 29 bits, therefore we have:
x
RJW 58 Tbit
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The minimum bit-time is:
Tbit min 1 segProp 1tq RJWmax
Therefore we have
58 58
RJWmax 1 x x 2tq segProp
100 100
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Question
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