High Level Data Link

Control (HDLC) Interface

NORSK DATA A.S

 High Level Data Link
Control (HDLC) Interface
 1

REVISION RECORD
Revision Notes
11/78 Original Printing

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HDLC - High Level Data Link Control Interface

Publication No. ND-12.018.01

NORSK DATA A.S.

F'ostboks 163 0ker-n, Oslo Norway

 MAIN CONTENTS
+ + +

Section:

PART I - HDLC INTERFACE

lntroduction
HDLC Configuration, ND No.720 and ND No.723
HDLC Interface Versus Communication Standards

PART II - FUNCTIONAL DESCRIPTION

lntroduction
HDLC Data
HDLC DMA Control

APPENDIX A

HDLC 1/0 CONFIGURATION

Detailed Description of the MultiProtocol Communication Controller

HDLC Line Connection and Driver Specifications

HDLC DATA - HDLC DMA Control Interconnection
Programming Specifications
HDLC Logical Diagrams
HDLC INTERFACE
PART I
 DETAILED CONTENTS
+ + +

Section: Page:

1.1 INTRODUCTION 1-1-1

1.2 HDLC CONFIGURATION, ND N0.720AND ND N0.723 1-2-1

1.2.1 HDLC I10 Interface ND No.723 Module 1141 1-2-1

1.2.2 HDLC Interface (DMA) ND No.720 Modules 1141 and
1151 1-2-2

1.3 HDLC INTERFACEVERSUS COMMUNICATION

STANDARDS 1-3-1

1.3.1 Introduction 1-3-1

1.3.2 Standards 1-3-2
1.3.2.1 Hardware Protocols Electrical and Mechanical Standards 1-3-3
1.3.2.2 Data Link Control Procedures (Link Access Procedures,
LAP) 1-3-3
1.3.2.2.1 Frame Format Standards 1-3-3
1.3.2.2.2 Communication Procedures 1-3-4

1.3.3 HDLC Frame Format 1-3-4

1.3.4 Standards Implemented on HDLC Interface 1-3-6
1.3.4.1 Electrical and Mechanical 1-3-6
1.3.4.2 Communication Protocols 1-3-6
1.3.4.3 Transmitting and Receiving Frames in Accordance With
HDLC Frame Format Using HDLC Interface 1-3-7
1.1 INTRODUCTION

High Level Data Link Control (HDLC) INTERFACE is a synchronous modem

interface, however, is also well suited as an intercomputer link interface (See
Figure 1.1 .I).

NORD 101s

LlNE
SYNCH
HDLC c ) MODEM 4
*
(DCE)
SPEED DETERMINED
BY LlNE

NORD 10/S NORD 101s

-
HDLC 4 * HDLC
MAX 307.2 Kbps

Figure I. 1.1: APPLICA TIONS OF HDLC INTERFACE

Used as a synchronous modem controller HDLC INTERFACE includes several
features by means of communication standards implemented in hardware.

Used as an intercomputer link, HDLC INTERFACE contains internal timing. A

strap switches from external timing (from modem) to internal timing which allows
transfer rates from 2.4 kbps (kilo bits per second) up to 307.2 kbps.

Independent of the use, dependent of the maximum required speed, HDLC could
be delivered as two different products serving the same functions as observed in
the external device (modem line, connected computer).

- NDNo.723: CPU controlled inputloutput transfer (PI01

Maximum speed 19.2 kbps

- ND No. 720: Direct Memory Access (DMA) transfer including

a DMA controller
Maximum speed 307.2 kbps
 HDLC CONFIGURATION, ND No.720 AND ND No.723

HDLC may consist of two modules both located in the I10 rack.
- 1181 HDLC DATA (ND NO.723)
ND No. 720
- 1151 HDLC DMA CONTROL

Physical configuration in 110-rack given in Appendix A l .

1.2.1 HDLC 1 / 0 INTERFACE ND No. 723 MODULE 7787

The DATA module may be used as an ordinary Programmed Input/Output (PI01

interface.

The data flow will be as indicated in Figure 1.2.1.

TO ONE
SLOT IN
I10 - SYSTEM

Figure 1.2.1: ND No. 723 DATA FL 0W

 I

HDL C INTERFACE (DMA) NO No. 720 MODULES 1181 AND 1151 =i

As indicated in Figure 1.2.1, the maximum speed when using HDLC DATA alone
is 19.2 kbps due to heavy CPU load on programmed inputloutput transfers. In
order to increase speed and reduce CPU load to a minimum, the HDLC DMA
CONTROL module ( 1 151) could be used together with the DATA module.

The two modules are connected with special wiring in the plug field in the
I/O-rack and occupy two slots in the I10 system.

HDLC DMA CONTROL and HDLC DATA working together allows DMA transfer
of data from computer memory to the line and vice versa at a maximum speed of
307.2 kbps.

The data flow is shown in Figure 1.2.2.

I10 - DATA BUS

a
DMA TO/FROM MEMORY

I
2 #J

HDLC MPCC SERIAL DATA

"CPU" G t
MAX SPEED 307.2 Kbps
"IOX" READ/
{HDLC DMA CONTROL WRITE DATA \ HDLC DATA

ND No. 720 occupies two slots In I/O -System

Figure 1.2.2: ND No. 720 DA TA FL 0W ' a

HDLC INTERFACE VERSUS COMMUNICATION
STANDARDS

INTRODUCTION

As a communication adaptor HDLC contains more communication standards

implemented in hardware than any other designed at NORSK DATA. This is a
consequence of advances in integrated circuit technology and international
standardization work.

All hardware related to communication standards is designed on HDLC DATA.

That means that there is no difference between ND No. 720 (DMA version) and
ND No. 723 (PI0 version) observed from the network. The difference is seen on
the CPU load. (See Functional Description Part 11).
1.3.2 STANDARDS

The involvement of two or more users and equipment from more than one
manufacturer in data communication systems gives an increased need of a
compatible method for connecting all of it together, an interface protocol.

These protocols may be divided into levels (See Figure 1.3.1.)

MTA LINK DA TA L /MY

CONTROL [ONTROL
C0MMU_N/c_A_r/o_NN
--
r - - - - - - -PRC
- TOCOLS --1 j
\ I I /
HDLC\ II/HDLC
I\
-
D
/ I
/I

PHYSICAL/ &' 1! PHYSICAL/

ELECTRICAL I L
E
i
I
I
ELEC TR/CAL

x. z//l x 2//1
V. 24 1 PUBLIC NETWORK VZ4
I I

------+ : PHYS/CAL PATH

--- + : LOrS/CAL PATH

Figure 1.3.1: INTERFACESTANDARDS

1.3.2.1 Hardware Protocols Electrical and Mechanical Standards)

These interfaces apply to the physical connection between user equipment (DTE)
and data communication equipment (DCE,modem).

Possible interface standards are as follows:

a) - CClTT V.24lV.28 and EIA RS-232c

- V.35 (wide band transmission)

For connection to the telephone network

b) - CClTT X.21 bis (V.28 signal levels)

- X.21 (X.27 signal levels)

For connection to the public data network

1.3.2.2 Data Link Control Procedures

(Link Access Procedures, LAP)

These protocols which have the purpose of controlling the exchange of data are
again divided up into the following levels:

- Frame format standards

- Communication procedures

1.3.2.2.1 Frame Format Standards

Most existing communication procedures transport data in blocks. However,

each communication procedure (Byte Control Procedures - BCP) has its own
block format, i.e., its own way of signaling "start of b l o c k , "end of block",
checksum, etc.

One of the first steps in communication standardization is the definition of a

uniform transmission format to be used for data and control information.

A transmission block is called a frame and a frame contains beginning and ending
markers, control information, optional data and a checksum.

The internationally accepted HDLC frame format is fully defined in I S 0 lS3309.2

standard. This procedure allows full bit sequency transparent data transmission
and is referred to as a Bit Oriented Procedure (BOP) (See Section 3.3).

At frame level HDLC (High Level Data Link Control) is fully compatible with SDLC
(Synchronous Data Link Control) and with ADCCP (Advanced Data
Communication Control Procedure).
1.3.2.2.2 Communication Procedures

The standardization of communication procedures is not as easy as the

standardization of a frame format. However, new standard procedures are
emerging. SDLC procedures have existed for some time, HDLC procedures are
being defined by CClTT and the X25 recommendation describes a procedure to be
used in public packet switching networks.

All the new procedures will, however, use the HDLC frame format.

1.3.3 HDLC FRAME FORMAT

The HDLC frame format is depicted below.

FLAG FLAG

01111110 A C
I I FCS 01111110

The frame consists of:

1. A special bit sequence call, "flag", that marks the beginning of the frame.
The end of the frame is also marked by such a flag.

The flag sequence consists of one zero bit, six one-bits and a zero bit.

The contents of the frame between the opening and the closing flag shall
not contain a flag sequence. To guarantee this, the transmitter inserts an
extra zero-bit following five consecutive one-bits. These inserted zero-bits
are removed by the receiver. These extra bits are called "transparency bits".

2. An 8-bit byte called Address-Byte

This field is meant as a station address, but the contents or use are not
prescribed in the frame standard.

3. An &bit byte called Control-Byte

This field is intended for link management information, but the frame
standard does not describe its use or contents.

4. An Information field

The information field may be any length, and may also be absent. The
contents of the information field are not prescribed.

5. A 16bit Frame Check Sequence (FCS)

This field contains a 16-bit Cyclic Redundancy Check computed over the
bits between the last bit of the opening flag and the first bit of FCS.

Transparency bits are removed before the FCS is computed.

6. The closing flag that signals frame end

The closing flag of one frame may be identical t o the opening flag of the
next frame.

Frame Size:

A valid frame shall contain at least 48 bits (Flag A, C, FCS).

There is n o prescribed upper limit t o the frame size. However, frame size is limited
by the properties of transmission channels and the 16-bit FCS computation.
1.3.4 STANDARDS IMPLEMENTED ON HDL C INTERFACE

On HDLC DATA the follbwing communication standards are hardware

implemented.

1.3-4.1 Electrical and Mechanical

Strap selectable:

- V.24/V.28,RS-232C

v.35 I Telephone Network

(V.series modem)

-
or
X.21-bis (V.28-signal levels)
I
- X.21 (X.27 signal levels)
I public data
network

1.3.4.2 Communication Protocols

Selectable From Program:

- Byte Oriented Procedures

Including automatic SYN character detection1generation

- Bit Oriented Procedures (BOP); HDLC (ISO-IS 33091, SDLC (IBM), ADCCP
(ANSI) including:
- automatic bit stuffinglstripping
- automatic frame character detectionlgeneration
- valid frame protection
- residue handling
- selectable:
- byte length 1-8 bits
- error checking CRC (CRC-16,CCITT-0,CCITT-1)
NONE
- primarylsecondary address mode
- idle mode
- point to point,multi-drop,loop configuration
1.3.4.3 Transmitttng and Receiving Frames in Accordance With HDL C
Frame Format Using HDL C Interface

The reason for calling the interface HDLC is related to the fact that frames in
accordance with HDLC frame format are generated automatically in hardware
when activated from driver software.

TRANSMISSION

When transmitting, software only has to know what should be in the address,
control and information field. Observed from the frame format, these fields could
contain any user defined information.

In order to pack the information into HDLC frame format before transmitting it on
the line, HDLC DATA (which handles the procedure) must be activated by some
control signals.

The control function is to first give the command Transmit Start Of Message
(TSOM, i.e. send opening flag) and when all information in the frame is
transmitted give the command Transmit End Of Message (TEOM, i.e. send
closing flag).

The Cyclic Redundancy Checksum (CRC) is generated automatically and put into
the frame when command TEOM is given.

RECEIVING

When receiving HDLC DATA will give status on Received Start Of Message
(RSOM, i.e. opening flag received) and Received End Of Message (REOM, i.e.
end marker of the frame is received).

Then software knows that all information received between RSOM and REOM
has the sequence; address, control, information and CRC; that means, in
accordance with HDLC frame format.

Therefore, successful communication against the line is related to successful

control of HDLC DATA.

In the data phase, that is:

- Load X bits bytes ( 1<X<8) on output
- Read X bits bytes ( l d X d 8 ) on input
- Control of frame formatting functions (TSOM,TEOM and RSOM,REOM)

This could be done by NORD 101s (HDLC in PI0 version ND No. 723) introducing
some overhead or by the DMA module (HDLC DMA, ND No. 720) reducing
overhead to a minimum (See Part 11).
 PART I1
FUNCTIONAL DESCRIPTION
 DETAILED CONTENTS
+ + +
Section: Page:

11.1 INTRODUCTION 11-1-1

11.2 HDLC DATA 11-2-1

11.2.1 Control of HDLC Data 11-2-4

11.2.1.1 lntialization of HDLC DATA, i.e. Loading of Mode Selection
Registers 11-2-6

11.2.1.2 HDLC DATA in the Data Phase

11.2.1.2.1 Receive (Input) Channel
11.2.1.2.2 Transmit (Output) Channel

11.3 HDLC DMA CONTROL 11-3-1

lntroducton
Control of the DMA Processor (The Commands)
lnitializaton
Data Transfer
Maintenace
HDLC DMA Structure
The List Structure
Receiver List
Transmitter List
11.1 INTRODUCTION

As mentioned HDLC INTERFACE may consist of the following two modules:

-
t
HDLC DATA ( P I 0 Version)
D M A Version
- HDLC DMA CONTROL

HDLC DATA may be used alone asa Programmed InputIOutput interface.

HDLC DMA CONTROL can only operate together with HDLC DATA.
HDLC DATA

The HDLC DATA module is designed after the same basic principles as other
parallel to serial (output to line), serial to parallel (input from line) interfaces
designed at NORSK DATA (See Figure 11.2.11.
The module contains the following:
- a device identification part including switches for setting of DEVICE NO. and
IDENT CODE

- receivers for local 110-address bus and receiversltransrnitters for local

I10-data bus
- a 40 pins LSI chip, the MultiProtocol Communication Controller - MPCC,
which performs:

- parallel to serial convertion on output data

- serial to parallel convertion on input data
- selectable protocol
- byte oriented (BCP) including automatic generationldetection of
SYN character. (Block formatting must be done by driver
software)

- bit protocols (BOP): HDLC,SDLC,ADCCP including automatic

frame format generation
- automatic bit stuffinglstripping
- automatic frame character detectionlgeneration
- valid frame protection
- residue handling
- selectable:
- byte length 1-8 bits
- error checking CRC (CRC-16,CCITT-0,CCITT-1)
NONE
- primarylsecondary address mode
- idle mode
- point to point,multi-drop,loop configuration

For detailed description of the MPCC see Appendix A2.

- line adapter for connection to Data Communication Equipment
(DCE, Modem) in accordance to standards

- V.24lV.28, RS 2 3 2 ~
telephone network
- v.35

OR

- X.21 bis (V.28 signal levels) public data

-- X.21 (X.27 signal levels) network

For detailed description of line connection, pin configurations etc., see

Appendix A3.
- special timing circuitry for inter-computer link connection, see also
Appendix A3.

In addition HDLC DATA contains circuitry for connection to the DMA CONTROL
module.
The DMA module contains a microprocessor to control the data transfer tolfrom
computer memory and HDLC DATA.

Therefore, HDLC DATA, in fact is designed to interface two processors:

- The NORD 101s CPU (through standard 110-system)

- The processor on the DMA module (through special inter-module

connection; see Appendix A4)

Observed from the DATA module it makes no difference what processor is active.

That means that the control of HDLC DATA could be done either by NORD 101s
or the DMA processor.

The most effective solution of course is to leave the inputloutput handling to the
DMA processor. Then NORD 101S CPU will have more time for data processing
which is the computers purpose.

CONTROL OF HDLC DATA

As mentioned in PART I, Section 3.4.3, successful communication between line

and computer is related t o successful control of HDLC DATA.

Including input and output data register there are 12 eight bits registers to control
the DATA module. All registers could be accessed by IOX instructions
(IOX<deviceno.> +0-1%).

Instructions 0-7, operate directly on 8 eight bits registers internally in the MPCC.

The instructions 10,-13, operate on single line indicators tolfrom the MPCC,
interrupt enabling and modem status information. See Figure 11.2.2 and the
following description.
 EROM REC CONT RxEN --+ MPCC 2652
FROM LINE
FROM TIMING
FROM REC CONT MAINT
ks1
RxC
-
+
+
COM 5025 TO R E C E l V t R
STATUS

1
l o x X+O

FROM TR CONT
FROM TIMING
TxtN
TxC
-)

_+
-
-
---
---
l o x x+7 2 TxU
zk

TSO
TO TRANSMITTER
STATUS

TO LINE

8833

RtCE IVER CONTROL

8
f- .-)

74LS
RECELVER S T A T U S
175

MUX - 8
IOXX+11 t
TRANSMITTER STATUE

74 LS
257
TRANSMITTFR CONTROL
8
lox X + 10 I 4

lox X + 12
74LS
175
1
8
-
IOX X+13

8835 8833

8 blts 8 blts

I10 DATA BUS

v TOIFROM
DMA MODULE

Figure 11.2.2: HDLC DATA - BLOCK DIAGRAM

There are five registers related to the output channel, four registers related to the
input channel and three registers common for operation mode control.
11.2.1.1 Initialization of HDLC DATA, i. e. Loading of Mode Selection
Registers

Before enabling inputloutput transfers t o HDLC DATA the module has t o be

initialized.That means after a MASTER CLEAR or DEVICE CLEAR, to load the
mode selection registers.

The mode selection register is held internally in the MPCC to control the operation
mode of the chip.

Remember that the MPCC performs the necessary frame formatting functions.
Therefore, both a local and remote HDLC interface should be put in the same
mode of operation given in the mode registers.

Loading of the mode registers is performed by IOX <device no.> + 1,3,4.

The format and function of the registers is given below:

IOX <DEVICE NO.> +1

WRITE PARAMETER CONTROL REGISTER (PCR)

FORMAT:
8 7 6 5 4 3 2 1 0
PROTSTRIP SEL IDLE CRC QEL
SEL GA AMOOM3DE Z Y X

BITO-2 ERROR CHECK SELECTION

0-2 CRC BOP Error Control Mode 2 1 0 Mode Char.Length

SEL BCP

CRC-CCITT present to 1's 0 0 0 BOP 1-8

CRC-CCITTpresent too's 0 0 1 BOP 1-8
Not used 0 1 0 ---
CRC-16 present too's 0 1 1 BCP 8
VRC odd 1 0 0 BCP 5-7
VRC even 1 0 1 BCP 5-7
Not used 1 1 0 ---
No error control 1 1 1 BCP 5-8
ECM should be loaded by the processor during
initialization or when both data paths are idle.
BIT 3 IDLE MODE SELECTION

3 IDLE Determines line fill character to be used if transmitter

underrun occurs (TxU asserted and TERR set) and
transmission of special characters for BOP/ BCP.

BOP IDLE=O, transmit ABORT characters during underrun and

when TABORT= 1.
IDLE= 1, transmit FLAG characters during underrun and
when TABORT= 1.
BCP IDLE= 0 transmit initial SYNC characters and underrun line fill
characters from the SIAR.
IDLE= 1 transmit initial SYNC characters from TxDR
(transmitter Data Register) and marks TxSO (transmitter
serial output) during underrun.

BIT 4 SELECT SECONDARY ADDRESS MODE

Used in ring networks to select secondary station (remote site) dependent of

received address compared with syncladdress register (See IOX <device no.>
3).

4 SAM BOP Secondary Address Mode = 1 if the MPCC is a secondary

station. This facilitates automatic recognition of the received
secondary station address. When transmitting, the processor
must load the secondary address into TxDR (Output Data
Register).
SAM = 0 inhibits the received secondary address comparison
which serves to activate the receiver after the first non-FLAG
character has been received.

BIT 5 STRIP GO AHEADISYNC

Used in ring networks ( BOP) to terminate message (frame).

5 SSIGA BOP Strip SYNCIGo Ahead. Operation depends on mode. For

loop mode only. SS/GA= 1 permits GA character to
terminate a received message. When a GA is detected REOM
and RABIGA will be set and the processor should terminate
the repeater function. SS/GA=O permits only a FLAG or
ABORT character to terminate a message.
BCP SS/GA= 1, causes the receiver to strip SYNC's immediately
following the first two SYNC's detected. SYNC's in the
middle of a message will not be stripped. SS/GA=O,
presents any SYNC's after the initial two SYNC's to the
processor.

BIT 6 PROTOCOL SELECTION

6 PROTO Determines MPCC Protocol mode

BOP PROTO = 0 BOP
BCP PROTO = 1 BCP
BIT 7 ALL PARTIES ADDRESS

Used in ring networks t o enable all connected computers as receivers, i.e. a

broadcast function.

7 APA BOP All Parties Address. If this bit is set, the receiver data path is
enabled by an address field of '1 1111111' as well as the
normal secondary station address.

IOX <DEVICE NO.> +3

WRITE SYNC/ADDRESS REGISTER (SARI

FORMA T:
8 7, 6 5 4 1 3 0

Pi-
BIT
- - ----
NAME MODE
I I I
8 bits SYNCH/SEC. ADDRESS
I

FUNCTION
I 1 I 1

0@07 S/AR BOP SYNCtADDRESS Register. Contains the secondary station

address if the MPCC is a secondary station. The contents of
this register are compared with the first received non-FLAG
character to determine if the message is meant for this
station.
BCP SYNC character is loaded into this register by the processor.
It is used for receive and transmit bit synchronization with bit
length specified by RxCL and TxCL.

IOX <DEVICE NO.> +4

WRITE CHARACTER LENGTH (CL)

FORMA T:
15 8 7 6 5 4 3 2
1
1
I
0
I

TRANSM. 0 0 REC.
CHAR.LENGTH CHAR.LENGTH

BIT NAME MODE FUNCTION

08-10 RxCL BOP/

BCP

0-2 2 1 0 Char.length (bits)

0 0 0 8
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
5-7 TxCL BOP/ Character bit length specification format is identical to RxCL.
BCP
11.2.1.2 HDL C Data in the Data Phase

After the initialization (See Section 11.2.1.I),

the DATA module is ready t o be
turned into the data phase.

As mentioned in Section 11.2.1 there are five registers to control the transmitted
(output) channel and four t o control the receive (input) channel.
11.2.1.2.1 Receive (Input) Channel

The control of the input channel is used to:

- write receiver control word to enable the input transfer (interrupt enable,
etc.)

- read receiver status register to check the transfer quality (valid data
available, error, etc.)
- read x bit bytes ( 1 6 x d 8) from input data register (seethe following details)

The input channel on HDLC DATA is connected to interrupt level 13 (normally

input is connected to level 12).

This is done in order t o reduce possibility of receiver overrun at high transfer rates.

RECEIVER TRANSFER CONTROL REGISTER

Receiver control word is loaded by IOX <device no.> + 11.

Format and description of the bits are given in the programming specifications
(See Appendix A5).

Special attention is drawn to control word bits 0, 1, 3, 4 and 7. Remember that

HDLC DATA is designed t o meet two processors.

The above mentioned bits decide what processor should be active controlling the
input channel.

CASE 1 DMA Module Not Installed

Bit 3 and 4 in input control word should be " 0 disabling the connection to the
DMA module.

Bit 0, 1 and 7 should be "1" enabling changes on the input channel to be reported
t o NORD 101S through interrupt on level 13.

The three following different "changes" can appear at the input channel:

- Receiver Data Available (RxDA)

signifies that input data register contains a valid data byte to be read
- Receiver Status Available ( RxSA)
coming from MPCC indicating a change in status has occured. Further
information is found by reading MPCC status register (See 10X
<device no. > 2)+
- Modem Status Change ( RMSC)
signifies status change on the line

All "changes" mentioned will interrupt NORD 101s to level 13. See Figure 11.2.3
for illustration and Figure 11.2.4for detaiisfrom HDLC DATA.
 RRQ
REN nn: RECEIVER ENABLE BIT
nn IN IOX <device n o . > + l l
REQUEST TO
DMA MODULE

1 RxDA
1
1
REN 0 N
I
- ,RxSA - D
1 V
A 0
RECEIVER REN I N
I RxDMA 0 .EV 13
A
REN 4 N R
ADAPTOR I R@N7 A
RMSC I N
-. - - - - - - - - - -- --p-
1 I RECEIVER PART
--------------- --------I------

7
TRANSMITTER PART
I -I -TxBE A
I I TEN 0 N
TMSC I I - TxU
A
I I V TEN 1 '
I TRANSMITTER D
I I TxDMA A
I I INTREQ TEN 4 N R
D
I I A
1 I TEN 7 N
I I
L--, - - -M,
-PCC
- -J

TEN 3 TRQ
TEN nn: TRANSMITTER ENABLE BIT
TxU D TRANSMIT REQUEST
nn IN I O X a e v i c e no.
> + 13
TO DMA MODULE
Figure 11.2.4: HDL C DATA. DETAILS FROM MODULE
CASE 2 D M A Module Installed

Refer to Figure 11.2.3. The idea is that NORD-101s should not be disturbed by
RxDA and RxSA, thus being interrupted for every received character/status.
(This effect is illustrated in the following example).

This is done by disabling interrupt generation on RxDA and RxSA. That means,
setting bit 0-1 in input control word to zero. Instead RxDA and RxSA is routed to
the DMA processor as a Receiver Request (RRQ). That is accomplished by
turning bit 3 on.

Then the DMA processor will read input status and data. The DMA module may
have information to NORD 101s (driver-software) related t o the input transfer.

The DMA processor then generates a Receiver DMA Interrupt Request (RDIR)
which gives interrupt on level 13 (enabled for in ICW bit 4).

Status change on the line (RMSC) is always reported directly to NORD 101s.

EXAMPLE:

Transfer RATE 19200 bits per second

8 bits per character
Characters per second: 1920018 = 2400 chis

That means2400 interrupts to handle every second just to the input channel.

RECEIVE S TA TUS REGISTERS

It should be noted that HDLC contains two status registersfor the input channel.

One of the registers is held internally in the MPCC. This register is accessed by
IOX <device no.> + 2 and contains information about the frame formatting
functions (See description below).

The other status register (Receiver Transfer Status) holds information about line
status, feedback from the control register and single line status from the MPCC.
This register is accessed by IOX <device no.> + 10 and is described in the
programming specifications (See Appendix A5).

IOX <DEVICE NO.> +2

READ RECEIVER STATUS - RxSR (FRAME INFORMATION)

This register is dynamically set and located internally in the MPCC. A change in
the register will activate RxSA which is reset when the status is read.

The format of the register and description of the bits is given below.

FORMAT:

I I
I
RSCLO - ROUF RAB REOM RSOM
RERR
--- -
Bit Name Mode Function

0 RSOM BOP Receiver Start of Message = 1 when a FLAG followed by a

non-FLAG has been received and the latter character matches
the secondary station address if SAM = 1.
RxA will be asserted when RSOM = 1. RSOM resets itself
after one character time and has no effect on RxSA.

1 REOM BOP Receiver End of Message = 1 when the closing FLAG is

detected and the last data character is loaded into RxDB or
when an ABORTIGA character is received. REOM is cleared
on reading RSR (Receive Status Register) reset operation, or
dropping of RxE.

2 RABIGA BOP Received ABORT or GA character = 1 when the receiver

senses an ABORT character if SSIGA = 0 or a GA character
if SSIGA = 1. RABIGA is cleared on reading RxSR
operation or dropping of RxE. A received ABORT inhibits
RxDA.

3 ROR BOP/ Receiver Overrun = 1 indicates the processor has not read
BCP the last character in the RxDR (Receiver Data Register) within
one character time. Subsequent characters will be lost. ROR
is cleared on reading RSR, reset operation, or dropping or
RxE (receiver enable).

4-6 ABC BOP Assembled Bit Count. Specifies the number of bits in the last
received data character of a message and should be examined
by the processor when REOM = 1 (RxDA and RxSA
asserted). ABC = 0 indicates the message was terminated
(by a FLAG or GA) on a character boundary as specified by
WCLR (write character length register bit 0-2). Otherwise
ABC = number of bits in the last data character. ABC is
cleared when RDSR, is read, reset operation, or dropping
RxE.

RERR Receiver Error indicator should be examined by the processor

when REOM = 1 in BOP, or when the processor determines
the last data character of the message in BCP with CRC or
when RxSA is set in BCP with VRC.

BOP CRC-CCITT preset to 1's should be specified by PCSAR,.,,:

RERR = 1 indicates FCS error (CRC # FOB81
RERR = 0 indicates FCS received correctly (CRC = FOB81

BCP CRC-16 preset 0's on &bit data characters specified by

PCSAR8.,,:
RERR = 1 indicates CRC-16 received correctly (CRC-0)
RERR = 0 indicates CRC-16 error (CRC #O)
VRC specified by PCSAR,.,,:
RERR = 1 indicates VRC error
RERR = 0 indicatesVRC is correct

READ RECEIVER DATA REGISTER (RxDR)

FORMAT:
15 8 7 6 5 4 3 2 1 0

pi--- - --- W E
1
I I

RECEIVED DATA
1
1
I I

LSB
B
11.2.12.2 Transmit (Output) Channel

The control of the output channel is to:

- write x bits bytes (16 x 6 8 ) to output data register
- load transmitter control registers to control the frame formatting functions
(MPCC) and activate the output transfer
- read transmitter status registers to check end of transfer and error indicators
(transmitter underrun)

Details follows.

The output channel on HDLC DATA is connected to interrupt level 12 (normally

output is connected to level 10). This is done to reduce the possibility of
transmitter underrun at high tranfer rates.

TRANSMITTER DA TA REGISTER 1TxDR)

This register is held internally in the transmitter part of the MPCC and loaded by
IOX <device no.> + 5.

FORMAT:

15 8 7 6 5 4 3 2 1 0
I , I 1

OUTPUT DATA

MSB LSB

TRANSMITTER CONTROL REGISTERS

There are two registers to control the transmit channel. One of the registers is
loaded directly into the MPCC to control the frame formatting functions (See
below).

The other control register (Transmitter Transfer Control Register - IOX <device
no.> + 13) is used on the module and serves the same function for the output
channel as the receiver control register for the input channel.

That is, to connect or disconnect NORD 1OIS CPU or the DMA processor to the
output channel of the DATA module.

The format and bit definitionsare given in the programming specifications.

For a better understanding, refer to Figure 11.2.3 and Figure 11.2.5 for details from
HDLC DATA.
Figure I/.2.5: HDL C Data, Details from Module
WRITE TRANSMITTER CONTROL REGISTER (TxCW)

In this register the frame formatting function on output data is controlled. By

loading the MPCC with one of the four least significant bits set to one in this
register, either an opening flag (TSOM), closing flag (TEOM), go-ahead, or abort
character automatically will be transmitted on the line (See details below).

FORMAT:
15 8 7 6 5 4 3 2 1 0
I I I ?
1 I I
Tx Tx TEOM TSOM
O O O O
GA AB

Bit Name Mode Function

0 TSOM Transmitter Start of Message. Set by the processor to initiate

message transmission provided TxE = 1.
BOP TSOM = 1 generates FLAGs. When TSOM = 0 transmission
is from TxDB and FCS generation begins. FCS, as specified
by PCR,., should be CRC-CCITT preset to 1's.
BCP TSOM = 1 generates SYNCs from PCSAR, or transmits from
TxDB for IDLE = 0 or 1 respectively. When TSOM = 0
transmission is from TxDB and CRC generation (if specified)
begins.

1 TEOM BOP Transmit End of Message. Used to terminate a transmitted

message when CRC error checking is used.
TEOM = 1 causes the FCS and the closing FLAG to be trans-
mitted following the transmission of the data character in
TxSR. FLAGs are transmitted until TEOM = 0. ABORT or GA
are transmitted if TABORT or TGA are set when TEOM = 1.
BCP TEOM = 1 causes CRC-16 to be transmitted (if selected)
followed by SYNCs from SAR, or TxDB (IDLE = 0 or 1).
Clearing TEOM prior to the end of CRC-16 transmission
(when TxBE = 1) causes TxSO to be marked following the
CRC-16. TxE must be dropped before a new message can be
initiated. If CRC is not selected, TEOM should not be set.

3 TABORT BOP Transmitter Abort = 1 will cause ABORT or FLAG to be sent

(IDLE = 0 or 1) after the current character is transmitted.
(ABORT = 11111111)

4 TGA BOP Transmit Go Ahead (GA) instead of FLAG when TEOM = 1.

This facilitates repeater termination in loop mode.
(GA = 01111111)

Bit 5-7: Not Used.

TRANSMITTER STATUS REGISTERS (TxSR)

Feedback from the output channel is carried through two status-registers.

One of the registers is held internally in the MPCC and reached by:

IOX <device no.> + 6.

This register holds the copy of transmitter control register (IOX <device no.>+7)
except from bit 7 which signifies transmitter underrun. Transmitter underrun TxU
will generate interrupt if enabled for.

FORMAT:
15

ITXU:TRANSMITTER UNDERRUN

The other status register for the output channel contains information about line
status and enabling done in output control register. The register (RECEIVER
TRANSFER STATUS) is accessed by (IOX <device no.> + 12).

The format and bit definitions are given in the programming specifications.
 HDLC DMA CONTROL

11.3.1 INTRODUCTION

In this chapter we will look at how the DMA module functions together with the
DATA module and NORD 101s.

We assume that the DATA module and DMA module are enabled to work
together (See inputtoutput transfer control words).

The DMA control is controlled by a microprocessor located on the module. The

main functions of the processor are to:

ON INPUT
- read characters from HDLC DATA, group them into 16 bits words and place
them in computer memory through Direct Memory Access IDMA)
- take care of status change in input channel

ON OUTPUT
- "DMA r e a d 16 bits words in computer memory, split them up into bytes
transferred to output data register on the DATA module
- take care of status change in output channel

To do this the DMA processor has all IOX-instructions operating on the DATA
module implemented in its microprogram.

NORD 101S and the DMA processor communicates through a common memory
area (the list structure).

NORD 101S controls the DMA processor by means of commands given in IOX-
instructions. The manner in which this is accomplished will be described in the
following sections.

r+3-ik
Data and
Transmitter Memory
Status

Bus

m
,-
4 I
Receiver
J

Commands
Control
V V c I10 Bus
I and
4 P Status
Line x r u p t
Adapter
Status

Figurell.3. I : BLOCK DIAGRAM OVER HDLC INTERFACE IDMAI

ND-12.018.01
CONTROL OF THE DMA PROCESSOR (THE COMMANDS)

Driver software controls the HDLC INTERFACE by means of 8 different

commands given in IOX-instructions. All commands (with the exception of
DEVICE CLEAR) need an 18 bits physical memory address due to reasons
explained in the following sections.

The 16 least significant bits of the address are transferred to the interface by IOX
<device no.> + 15.

The most significant address bits(Bank bits) are given in IOX <device no.> + 17.
In the format of IOX <device no.> + 17, three bits are left to specify command
no. (See format).

FORMAT:

15 11 10, 9, 8 7, 61 5, 4, 3 2 1, 0
1 I I 1 I I I

COMMAND BANK
CODE 0 0 0 0 0 0 BITS
A

--T-

The commands may be divided up into the three following groups:

a) INITIALIZATION
- DEVICE CLEAR
- INITIALIZE

b) DATA TRANSFER
- RECEIVER START
- RECEIVER CONTINUE
- TRANSMITTER START

C) MAINTENANCE
- DUMP DATA MODULE
- DUMP REGISTERS
- LOAD REGISTERS
11.3.2.1 Initialization

DEVICE CLEAR (Command 0)

Before operating HDLC INTERFACE (DMA), a DEVICE CLEAR should be

performed to ensure safe operation.

Recommended program for Device Clear is:

SAAO % A reg. = 0
IOX GP + 11 (octal) % Write Receiver Transfer Control
BSET ONE 50 DA % A reg. = 40 (octal)
IOX GP + 11 (octal) % Device Clear to Data Module
+
IOX GP 17 (octal) % Device Clear to DMA Module

The Device Clear sequence as described above will stop all data transfers t o and
from the interface, and it can be used anytime. Device Clear will clear all interrupts
from the interface, and a dialed up modem connection will be broken.

INITIALIZE (Command 1 )

The command INITIALIZE should be used after a Device Clear.

The command will initialize the DATA module (See Section 11.2.1.1) and load the
DMA module with necessary parameters related to the DMA structure (see
Section 11.3.3).

To obtain the necessary information to perform the initialization; the command

requires 7 locations in memory (parameter buffer).

These locations should be set by driver software prior to execution of the

command.

The contents of the parameter buffer are:

1 Parameter Control Register

2 Sync1Address Register
3 Character Length
4 Displacement 1
5 Displacement2
6 Max.Receiver Block Length
7 Checksum

The contents of the three first locations are written into the DATA module. The
bit mapping of locations is described in Section 11.2.1.1.

Displacement 1 is the number of free bytes reserved at the beginning of each

buffer containing the start of a message (Frame). Displacement2 is the number of
free bytes reserved at the beginning of each buffer which do not contain the start
of a message (Frame). Max. Receiver Block Length is the total number of bytes in
a receiver buffer, including displacement. Long frames may be divided into blocks
and stored in two or more buffers.

The use of these parameters will be illustrated in the next section, i.e. data
transfer.

The checksum is set to 0 by driver software and set to 102164 by the DMA
processor when INITIAL!ZE is finished. The interface should not be used in DMA
mode if this checksum is wrong.
When started the DMA processor with Direct Memory Access will read the
parameter buffer. To accomplish this an address pointer to the parameter buffer is
needed. The address is given in the start INITIALIZE sequence which consists of
the following:

- LDA <least address>

% write DMA address
IOX <device no.> + 15
Write least address to HDLC INTERFACE

- LDA00040B
% write DMA command register
IOX <device no.> + 17
Write most address and start INITIALIZE

Refer t o Figure 11.3.2 for illustration.

DRIVER SOFTWARE COMPUTER MEMORY

LDA <LEAST ADDR>

IOX <device no. >+15
LDA <00040B>
IOX <device no. >+17 /I I SAR I
CL
DlSP 1 I

L - - - - - - - - - -- - - -I,
HDLC DMA module

Figure 11.3.2:COMMAND INITIALIZE lL L US TRATlON

11.3.2.2 Data Transfer

After initialization (See Section 11.3.2.1 the commands:

RECEIVER START
RECEIVER CONTINUE
TRANSMllTER START

may be used.

Under this label only a description of how to use the command will be given. To
understand how they operate, the reader is advised t o study Section 11.3.3 (HDLC
DMA STRUCTURE).

RECEIVER START (Command 21

The RECEIVER START command will as the name suggests, start the
microprogrammed receiver on H DLC INTERFACE.

Three IOX-instructions are used to activate RECEIVER START

LDA <least address> Write 18 bits DMA

IOX <device no.> + 15 address to interface
LDA 001006 and start Receiver
IOX <device no.> + 17

LDA (3334 Enable receivechannel

IOX <device no.> + 11 to DMA module. (See Appendix A5
IOX <device no.> + 11)

The address written to the interface in a Receiver Start sequence is denoted a

"List Pointer". This address is the first address of a list containing "Buffer
Descriptors" (See HDLC DMA Structure). This command also selects Displace-
ment 1 for the first buffer, and should therefore be used the first time the receiver
is started after a power up or receiver disable.

The receiver should normally run. A Receiver Request from the DATA module will
then automatically be handled.

RECEIVER CONTINUE (Command 31

This command is used to write a new List Pointer to an enabled and working
interface. It should only be used as a response to a "List Empty" interrupt.

TRANSMITTER START (Command 41

This command is always used to start transmission of data. As for RECEIVER

START, an address is written to the interface when the transmitter is started. To
enable the transfer, the Transmitter Control register (IOX <device no.> + 13) has
to be loaded.
11.3.2.3 MAINTENANCE

DUMP DATA MODULE (Command 5)

This command is mainly for maintenance purpose. It requires 5 locations in

memory, where the contents of the following registers are stored:

1. Parameter Control Register (8 least sign. bits)

2. Syncl Address Register (8 least sign. bits)
3. Character Length (8 least sign. bits)
4. Receiver Status Register (8 least sign. bits, not accumulated)
5. Transmitter Status Register ( 8 least sign. bits, not accumulated)

The contents of the registers in the Multi Protocol Communication Controller

(MPCC) are transferred to memory. The Receiver Status Register is also OR-ed
into the Receiver Dataflow Status Register t o prevent loss of information.

DUMP REGISTER (Command 6)

This command can be used to dump the contents of any number of the 256
random access memory registers in the DMA module. Required space in memory
is 2 locations plus one location for each register to be dumped. The contents of
the two locations are:

1. First Register Address

2. Number of Registers

If both values are zero, the contents of the 16 registers in the Bit Slice are written
into memory.

The meaning of the different values is illustrated by the figure below.

DMA COMPUTER
MODULE MEMORY

ADDRESS WRITTEN
BY IOX GP+15, IOX GP+l
 LOAD REGISTER (Command 7)

This command can be used to load any number of the 256 random access
memory registers in the DMA module. Required space in memory is 2 locations
plus one location for each register to be loaded. The contents of the two locations
are:

1. First register address

2. Number of Registers

The Load Register command is simular to Dump Register, except that data is
moved in the opposite direction. It is not possible t o load the registers in the Bit
Slice by this command.

The commands, how to activate them and use them in some simple debugging
programs are given in Appendix A5.

11.3.3 HDLC DMA STRUCTURE

The DMA structure is organized around lists which contain the necessary control
and status information t o connect "driver" software and DMA processor
together.

The lists which reside in the computer memory could be accessed directly from
driver software and through DMA requeststolfrom HDLC interface.

The receiver and the transmitter works from separate lists, with the same
structure and format. The information exchange between driver software and
DMA processor through the list structure provides dynamic allocation and linking
of data buffers.

11.3.3.1 The Liststructure

The list contains a number of entries of four words each. Each list entry describes
a data block. In the receiver lists, each entry describes a receive data buffer where
the received data is to be stored.

I n the transmitter list, each entry describes a block of data that is to be

transmitted.

The four words of each entry contain the following information:

WORD 1 Block status and key

WORD2 Amount of information in the data block

(Byte Count)

WORD 3-4 18 bits physical memory address of data block

More detailed description is given below.

11.3.3.1.1 Receiver List

In this section the operation of the receiver list is described.

After proper initialization (See Section 11.3.2.11, the DMA processor is given a list
pointer and the "RECEIVER START" command.

The liste pointer points to one of the entries in the receiver list (See Figure 11.3.4).

DATA BUFFER
4
LIST POINTER
BYTE COUNT DISPLACEMENT (D)
Most Address (D =NUMBER OF FREE
Least Address
BYTES)
BUFFER DESCRIPTOR
r-------
I
-
--------,

BYTE COUNT
NUMBER OF INFOR-
-
MATION BYTES
I I
I I
I I
I

Figure 11.3.4: LIST STRUCTURE

The DMA processor will now generate a DMA request using the list pointer as
address and fetch the first entry from the list beginning with the status word.
 FORMAT OF THE STATUS WORD

2 1 0
15 - -- 1 1 1 0
BLOCK
9 8 7
I
6
I
5 4
I
3
i

- - 0 KEY RCOST
DONE
- --
Y
J
RECEIVER DATAFLOW STATUS
DESCRIPTION BE LOW

BITS 10 9 8
0 1 0 Empty Receiver Block
0 1 1 Full Receiver Block
1 0 0 Block to be Transmitted
1 0 1 Already Transmitted Block
1 1 0 New List Pointer

The status word should be all zero except for the key.

The BLOCK DONE bit signifies used block. That is, to prevent overwriting on
input or duplicated transmission on output.

Legal keys for the receiver are 10008(Bit 9 set) or 3004 (Bit9 and 10 set).

CASE 1. Key is 70008

The key is legal saying empty receiver block. The DMA processor will now read
the block address (word 3&4), add Displacement 1 and incoming data will be
stored in the block.

When the block is filled (MAX.RECEIVER BLOCK) or the interface recognizes

"frame end" (REOM), the DMA processor updates the list entry.

Updating the list entry includes updating the status word and writing the number
of bytes received into the byte count.

Updating Status Word.

Updating the status word is to change the key and update RCOST

The key is changed by setting the BLOCK DONE bit signifying Full Receiver
Block.

Updating RCOST, let us first see what RCOST contains.

-- I
Rx R{CLO ;) - 2 Rx Rx
BLOCK
-- 0 KEY
DONE ERR OVR SNA8
- -
\
See Descr i p t x o f
IOX <device no. >+2 READ RECEIVER
STATUS
RCOST is identical to Receiver Status Register in the MPCC.

Suppose both bit 0 and 1 are set, that means the status word is updated to
1 m 8 . Then the list entry describes a Full Receiver Block which contains a whole
frame because both RSOM and REOM are received within the block.

If only bit 0 is set (1401, in status word) the list entry describes a full receiver block
which only contains the first part of a frame. That means that "MAX. RECEIVER
BLOCK" was recognized before frame end (REOM). In other words, the frame
contains more information than the receive block could store. In this case the
DMA processor automatically will increment its list pointer by four and read next
list entry describing next data buffer.

Suppose now that the new data block could store the last part of the frame. Than
the status word of this list entry will be updated to 1402, signifiying full receive
block and only closing flag received. This block change is accomplished fast
enough to maintain continuous handling of incoming data. It is assumed possible
togive BLOCK END interrupt (See Receive Transfer Control Register).

That means, when "driver" software should take care of the incoming
information it looks at the statusword of the list entries.

If status is 1403,, it knows there are no errors and a whole frame of valid data is in
the data block.

If status is 1401,, it knows that the block contains the first part of a frame and the
next list entry with status 1402, contains the last part.

This is illustrated in the receiver list illustrations (See Figures 11.3.5, 11.3.6, and
11.3.7).

CASE2. KEY is 3000,

The key is legal, however it does not define a data block. Instead the list entry in
word 3 and 4 contains the address to a new list.

That means, word 3 and 4 are taken as a new list pointer and the receive
procedure continues as in Case 1.

NOTE:

If this list change occurs during input data, it takes too much time to
maintain continuously input handling. Therefore, this situation will give List
End interrupt (See Receiver Transfer Controll Status registers).
 RECEIVER LIST If L USTRA TIONS.

Example: Frame Size.

-
FLAG ADDRESS CONTROL INFORMATION C RC C LAG

DATA FOR SOFTWARE

100, BYTES
USER DE FINED INFORMATION
OBSERVED FROM FRAME FORMAT

Case 1. RECEIVER BLOCK SIZE: 1560 bytes

LlST STRUCTURE

IN INTERFACE IN COMPUTER MEMORY

DATA BLOCK

I LlST
POINTER
CONTAINING A
WHOLE FRAME

--------- #Q OF FREE
BYTES DlSP 1

Figure 3.5: CASE 7 ILLUSTRATION

 Case 1. RECEIVER BLOCK SIZE: 75 bytes

LIST STRUCTURE

IN INTERFACE IN COMPUTER MEMORY

LIST
POINTER I L

14018
75

-------- +DISP 1 NO OF FREE

BYTES DlSP 1

1 3 I ( 1 'st Part I

+ DlSP 2

BYTES DlSP 2

Figure 3.6: CASE 7 ILL US TRA TION

NO TE:

If a frame is stored in more than two data Mocks "middle" blocks are
marked by "not start of frame" and "not end of frame" (i.e. 1400,).

The data stored in a receiver block is now "taken care o f ' by driver software
which also resets the list entry of the block.

The resetting is to change the status word to "Empty Receiver Block", i.e. 10008
or 3000,.

Typical use of data blocks and list entries is illustrated below.

Driver Software Operating on Already

- Received Frame.

*
DMA processor
storing incoming
data in this

Figure 11.3.7: TYPICAL LIST OPERA TlON

This looping in receiver list requires that driver software is fast enough t o reset the
list entries. If the DMA processor reaches the NEW LlST POINTER and than Full
Receiver Block, a LlST EMPTY interrupt is generated. (See Receiver Transfer
Status Register).
11 .3.3.1.2 Transmitter List

The transmitter list is identical in structure to the receive list.

After initialization, the DMA processor is given a list pointer and the
"TRANSMITTER START" command. The DMA processor will than process the
transmitter list entries as described in Section 11.3.3.1 .l.

Note the following differences:

The transmitter list is updated by driver software and describes blocks of

data to be transmitted.

The DMA processor outputs data and sets the Block Done bit in the list
entry signifying Already transmitted block.

As for the receiver list there are special cases also for the tramsmitter list.

The key could be either 2000, or 3000,. This situation is treated identically
as for the receiver list and will not be discussed again.

Data belonging to one frame could be placed in one, two or more data
blocks. The case is set by driver software in the status word of the list entry.

FORMAT OF THE STATUS WORD

---- I I
I
-

,
BLOCK TX NO b~ BITS Tx Tx
KEY TEOM TSOM
DONE ERR IN LAST BYTE GA AB
----
L
SEE EARLIER
A
SET BY DMA
v A .
SET BY DRIVER
DESCRIPTION PROCESSOR WHEN SOFTWARE PRIOR
BLOCK IS TRANSM. TO TRANSMISSION
 CASE 1. A Hole Frame In One Block

Suppose the frame contains 100 bytes. Then the list entry set by driver software
will be as shown below.

IN COMPUTER MEMORY

LIST
POINTER
- 2003,
100A +DISP 1
Tx DATA BUFFER
----
BLOCK
-------,
ADDRESS
h
-
>

The DMA processor will read the status word of the list entry. The status word
contains legal key (Bit 10 set). Both TEOM and TSOM are set to 1.

That means for the DMA processor:

- first transmit TSOM (opening flag)
- when 1008bytes are transmitted, send TEOM (closing flag)
- update the list entry by setting the Block Done bit (in special cases also one
of the bits 2-71
 CASE 2. A Hole Frame In Two Blocks

The list entries will now be as indicated below.

IN INTERFACE IN COMPUTER MEMORY

"
508 + DlSP 1
BLOCK
- - - - --------
ADDRESS 1 'st
2002,
Part
30, of Frame
3

--------
BLOCK ---
ADDRESS

2'nd
Part
of Frame

The first list entry, which contains the first part of the frame, contains legal key
and only TSOM set.

The second list entry has also legal key and only TEOM set.

NOTE:

If a frame is held in more than two data blocks, the middle "blocks are
marked by not start of frame " and "not end o'f frame" (i.e. 2000,).

Use of data blocks and transmitter list is typically organized as for receiver list.
APPENDIX A
 HDLC I10 INTERFACE ND NO. 723 6
F
MODULE NUMBER 1141 * 0
2
0
SPECIAL WIRING FOR
r-BUS RECEIVER -
y- LOCAL I10 BUS - DMA DEVICES --
, 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 116 1 17 118 I19 120 121 122 I23 124 25 126 1 27128 129 130 1 31 132
zp
1 1 1 1*+ (2
o ~ I o I
9 0 DMA
83
o 8
d
rQ 3 3 1 1
:IB
9
*
(

1
Due to unreliable components many ECO's (Engineering Chanw Orders) on HDLC DATA ( 1 141) the module is redesigned and the n9rnh.r is changed to 1181.
1181 contains all ECO's done on 1141.The module number change do not imply any change in functions of the module.

t
Any position in Local I10 Bus. There should be modules in all positions from position 9 t c HDLC DATA.
HDLC INTERFACE (DMA) ND NO. 720
DATA TO MEMORY VIACPU MODULE NUMBERS 1141 (1181),1151,1932*

r- BUS RECEIVER -v- LOCAL I10 BUS DMA -

-
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15116 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 I 2 2 1 2 3 1 2 4 2 5 P 6 127128129130(31132

1 1 1 1 1 1 c
0
9
3
'
0
9
3
1
0
1
1
8
1
1
5
1
9
3
2
-
Module number 1932 i s called HDLC DMA SHADOW. HDLC DMA CONTROL is designed with 256 x 8 bits RAM locations.
The memory chips used are not yet available from the semi-conductor manufacturer. HDLC DMA SHADOW is used to simulate
the memory chips and will be removed when they are available.

HDLC INTERFACE (DMA) should be placed behind unbuffered DMA devices and in front of bufferred DMA devices (Big Disk).
HDLC INTERFACE (DMA) ND NO. 720
DMA DIRECT TO MULTIPORT MEMORY

BUS RECEIVER
p-, & BRANCHER - v LOCAL I10 BUS - DMA

Same placement philosophy as under * * on the previous page.

A .2 DETAILED DESCRIPTION OF THE MUL TIPROTOCOL COMMUN-
ICATION CONTROLLER
 COM 5025 0
P P C FAMILY I
Prellmlnary Spec~ftcat~ons

Multi-Protocol
Universal Synchronous Receiverrrransmitter
USYNRIT
PIN CONFIGURATION
FEATURES
0 Selectable Protocol-Bit or Byte oriented
Direct TTL Compatibility
Tri-state InputIOutput Bus
Processor Compatible-8 or 16 bit
High Speed Operation-2.0M Baud-typical
Fully Double Buffered-Data, Status, and Control Registers
Full or Half Duplex Operation-independent Transmitter and
Receiver Clocks
-individually selectable data
length for Receiver and
Transmitter
Master Reset-resets all Data, Status, and Control Registers
Maintenance Select-built-in self checking

BIT ORIENTED PROTOCOLS-SDLC, HDLC, ADCCP BYTE ORIENTED PROTOCOLS-Bisync, DDCMP

C 1 Automat~cb ~stufflng
t and strrpplng LJ Automatlc detect~or~
and generat~onof SYNC characters
Automatlc frame character detect~onand generat~on
Valld message protect~on-a valld recelved message IS SELECTABLE OPTIONS:
protected from overrun I I Varlable Length Data-1 to 8 b ~bytes
t
Resldue Handltng-for messages whlch termlnate w ~ t ha L1 Varlable SYNC character-5,6, 7 , or 8 brts
parllal data byte, the number of valld L I crror Checking-CRC (CRC16, CCITT-0, or CCITT-1)
data bits 1s available -VRC (oddieven panty)
-None
SELECTABLE OPTIONS: rl Strlp Sync-deletlon of leadlng SYNC characters after
U Varlable Length Data-1 to 8 btt bytes synchronlzatlon
0 Error Checking-CRC (CRC16, CCITT-0, or CCITT-1) O ldle Mode-idle SYNC characters or MARK the l ~ n e
-None
Primary or Secondary Statlon Address Mode
All Parties Address-APA
L11 Extendable Address Fleld-to any number of bytes
Extendable Control Fleld-to 2 bytes
ldle Mode-idle FLAG characters or MARK the l ~ n e
0 Potnt to Polnt, Multl-drop, or Loop Conflguratlon

APPLICATIONS
Computer to Modem lnterface O Peripheral to Modem lnterface
Ci Modem to Computer lnterface Modem to Peripheral lnterface
Terminal to Modem lnterface fl Serial Data Bus
E l Modem to Terminal lnterface
 General Description
The COM 5025 is a COPLAMOS" channel silicon gate MOSILSI device that meets the majority of
synchronous communications requirements, by interfacing parallel digital systems to synchronous serial
data communication channels while requiring a minimum of controller overhead.

The COM 5025 is well suited for applications such as computer to modem interfaces, computer to computer
serial links and in terminal applications. Since higher level decisions and responses are made or initiated by the
controller, some degree of intelligence in each controller of the device is necessary.

Newly emerging protocols such as SDLC, HDLC, and ADCCP will be able to utilize the COM 5025 with a
high degree of efficiency as zero insertion for transmission and zero deletion for reception are done
automatically. These protocols will be referred to as Bit Oriented Protocols (BOP). Any differences between
them will be discussed in their respective sections. Conventional synchronous protocols that are control
character oriented such as BISYNC can also utilize this device. Control Character oriented protocols will be
referred to as CCP protocols. Other types of protocols that operate on a byte or character count basis can
also utilize the COM 5025 with a high degree of.efficiency in most cases. These protocols, such as DDCMP
will also be referred to as CCP protocols. I
!

The COM 5025 is designed to operate in a synchronous communications system where some external
source is expected to provide the necessary received serial data, and all clock signals properly
Synchronized according to EIA standard RS334. The external controller of the chip will provide the
necessary control signals, intelligence in interpreting control signals from the device and data to be
transmitted in accord with RS334.

The receiver and transmitter are as symmetrical as possible without loss of efficiency. The controller of the
device will be responsible for all higher level decisions and interpretation of some fields within message
frames. The degree to which this occurs is dependent on the protocol being implemented. The receiver and
transmitter logic operate as two totally independent sections with a minimum of common logic.

References:
1. ANSI-American National Standards Institute
X353, XS341589
202-466-2299
2. CCITT-Consultative Committee for International
Telephone and Telegraph
X.25
202-632- 1007
3. EIA-Electronic Industries Association
TR30, RS334
202-659-2200
4. IBM
General Information Brochure, GA27-3093
Loop I n t e r f a c e O E M Information, GA27-3098
System Journal-Vol. 15, No. 1, 1976; G321-0044
MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .O C to + 70°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-. 55 C to + 150' C
Lead Temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. i.-.3 2 5 'C
Positive Voltage on any Pin, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18.OV ..
Negative Voltage on any Pin, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V ..
*Stresses above those llsted may cause permanent damage to the devlce Thrs 1s a stress ratlng only and
functional operation of the device at these or a? any other condltlon above those lnd~catedIn the operational
sectlons of thls speclftcat~on1s not ~mplted.
ELECTRICAL CHARACTERISTICS (TA=O'C to 70'C, VCC=t 5V15?'o, VDD- t 12V ?5Olo, unless otherwise noted)

--- - --- - - -- - - - -- - - . .

Parameter Min. Typ. Max. Unit Comments

-- - - -- ---.- --- -- ------- -- - - - -- .---- - -- -- ---
D.C. Characteristics
INPUT VOLTAGE LEVELS
Low Level. VIL 08 V
H~gh Level, Vni Vck- 1.5 Vcc V
OUTPUT VOLTAGE LEVELS
Low Level, VOL 04 V IOL- 1 6ma
H~gh Level. VOH 24 \OH 40pa
INPUT LEAKAGE
Data Bus 50 100 O - VIN- 5v, DPENA- 0 or WIR I
All others Pa
'la VIN- t 5 v
INPUT CAPACITANCE
Data Bus, CIN ~f
Address Bus. CIN PI
Clock, CIN ~f
All other. CIN ~f
POWER SUPPLY CURRENT
Icc ma
loo ma

A.C. Characteristics
CLOCK-RCP, TCP
frequency MHz
PWH ns
PWL ns
tr, t1 ns
DPENA. TWOPENA ns
Set-up Tlme. TAS ns
Byte Op. W/R
A2, Ai. Ao
Hold Time, TAH
Byte Op. WIR,
A2. Ai. Ao
DATA BUS ACCESS, TDPA
DATA BUS DISABLE DELAY, TDPD
DATA BUS SET-UP TIME. Toes
DATA BUS HOLD TIME, TDBH
MASTER RESET, MR
 Description of Pin Functions
Pln No. Symbol Name 110 Funct~on
-- -. - - - -
1 voo Power Supply PS 4 12 volt Power Supply
2 RCP Recelver Clock I The poslt~ve-gangedge of thls clock shllts data Into the recelver shlfl reglster
3 RSI Receiver Ser~allnput I This lnput accepts the ser~alb ~Inputt stream
4 SFR SynclFlag 0 Thls output IS set h~gh,for 1 clock tlme of the
Recelved RCP, each time a sync or flag character 1s recelved
RXACT Recelver Actlve 0 Thls output IS asserted when the RDP presents the flrst data character of the
message to the controller In the BOP mode the f~rstdata character 1s the flrst
non-flagcharacter (address byte) In the CCP mode 1 11str~p-sync 1s set. the
flrst non-sync character 1s the llrst data character 2 11str~p-sync 1s not set. the
flrst data character 1s the character following the second sync In the BOP
mode the tralllng (next) FLAG resets RXACT In the CCP mode RXACT
IS neverreset, 11can be cleared vla RXENA
RDA Recelver Data 0 This output 1s set h ~ g hwhen the RDP has assembled an entlre character and
Available transferred 11Inlo the/RDB Thls output 1s reset by readlng the RDB
RSA Recelver Status 0 Thls output 1s set h ~ g h1 CCP-~n the event of recelver over run (ROR)
Available or panty error (11selected). 2 BOP-~n the event of ROR. CRC error (11selected)
recelvlng REOM or RABIGA Thls output 1s reset by readlng the
recelver status register or dropplng of RXENA
RXENA Recelver Enable I A h~gh level Input allows the processlng of RSl data A low
level dlsables the RDP and resets RDA, RSA and RXACT
GND Ground GND Ground
DEB8 Data Bus 110 i B~dlrect~onal Data Bus
I
DB09 Data Bus 110 B~dlrectlonalData Bus
DBl$ Data Bus 110 B~dlrect~onal Data Bus
DBl 1 Data Bus I10 B~dlrect~onal Data Bus
DB12 Data Bus I10 B~dlrect~onal Data Bus
DB13 Data Bus 110 B~dlrect~onal Data Bus
DB14 Data Bus I10 B~dlrecttonalData Bus
DB15 Data Bus 110 B~dlrectlonalData Bus OR w~thDP07
WIR Wrlte:Read I Controls d~rect~on of data port WIR 1 Wr~teW/R 0. Read
A2 Address 2 I Address lnput -MSB
A1 Address I 1 Address Input
A$ Address 0 I Address ~nput-LSB
BYTE OP Byte Operat~on I If asserted byte operat~on(data port IS 8 b ~ t sw~de)1s
selecled If BYTE OP 0 data port 1s 16 blls w ~ d e
DPENA Data Port Enable I Strobe for data port After address, byte op WIR and data are set-up DPENA '
may be strobed If read~ngthe port. DPENA may reset (dependlng on reglster
selected by address) RDA or RSA If wr~tlngInto the port. DPENA may reset
(dependlng on reg~sterselected by address) TBMT
Data Bus 110 B~dlrect~onal Data Bus-MSB
Data Bus 110 Bldlrect~onalData Bus
Data Bus I10 B~dlrect~onal Data Bus
Data Bus I10 B~dlrect~onal Data Bus
Data Bus 110 B~direct~onal Data Bus
Data Bus 110 B~d~rect~onal Data Bus
Data Bus 110 B~dlrectlonalData Bus
Data Bus I10 B~dlrect~onal Data Bus-LSB
Power Supply PS 1 5 volt Power Supply

Master Reset I Th~sInput should be pulsed h ~ g h after power turn on Thls will clear all flags, and
status cond~t~ons set TBMT 1. TSO 1 and place the devlce In the prlmary
BOP mode w~th8 btt TXIRX data length. CRC CClTT l n ~ t ~ a l ~to z eall
d 1s
TXACT 0 Thls output lndlcates the status of the TDP TXACT w ~ lgo l h ~ g hafter asserllng
TXENA and TSOM colns~dentlyw~ththe first TSO b ~ tThls output will reset one
half clock after the byte dur~ngwhlch TXENA 1s dropped
TBMT Transm~tterBuffer 0 Thls output 1s at a h ~ g hlevel when the TDB
Empty or the TX Status and Control Regrster may be loaded wlth
the new data TBMT 0 on any wr~teaccess to TDB or TX Status and
Control Reg~sterTBMT returns h ~ g h when the TDSR 1s loaded
TSA Transm~tterStatus 0 TERR b ~ tlndtcatlng transm~tterunderflow
Available Reset by MR or assert~onof TSOM
TXENA Transm~tterEnable I A h~gh level Input allows the processlng of transm~tter
data
TSO Transmltter Serial 0 t the transmitted character
Thls o u t ~ uIS
output
TCP Transmitter Clock I The pos~llvegolng edge of thls clock sh~lts
data out of the
lransmltter sh~ftreglster
MSEL Ma~ntenance I Internally RSI becomes TSO and RCP becomes T .-
Select Externally RSI is disabled and TSO= 1.
 Definition of Terms
Register Bit Assignment Chart 1 and 2
Term Def~n~t~on
- --- - - - - - -
RSOM Recelver Start of Message-read only b ~ tIn BOP mode only goes h ~ g h when first non-flag (address byte)
1
character loaded Into RDB It 1s cleared when the second byle 1s loaded Into the RDB
REOM Recelver End of Message-read only bll In BOP mode only set hlgh when last byte of data loaded Into RDB or
when an ABORT character IS recelved It 1s cleared on readlng of Recelver Status Reg~steror dropplng of RXENA
RABlGA Recelved ABORT or GO AHEAD character read only b ~ tIn BOP mode only 11LM 0 thls b ~1ts set on recelvlng an
ABORT character ~f LM 1 th~sb ~ISl set on recmvlng a GO AHEAD character Thls IS cleared on reading of
Receiver Status Reg~steror dropplng of RXENA
ROR Rece~verOver Run-read only blt Set hlgh when rece~veddata transferred ~ n l oRDB and prevtous data has not
been read lndlcatlng fallure to servlce RDA w~lhlnone character llme Cleared on readlng of Recetver Status
Reg~steror dropping of RXENA
ABC Assembled B I Count-read
~ only btts In BOP mode only, examlne when REOM 1 ABC 0 message terminated
on stated boundary ABC -XXX message termlnated (by FLAG or GA) on unstated boundary, blnary value of ABC
= number of valrd b ~ t s available In RDB (r~ghthand justlf~ed)
ERR CHK Error Check-read only b ~ tIn BOP set hlgh 11CRC selected and rece~ved~nerror, examlne when REOM 1 In
CCP mode 1 set h ~ g h11panty selected and received In error, 2 11CRC selected (tested at end of each byte) ERR
CHK 1 11CRC GOOD. ERR CHK = 0 11CRC NOT GOOD Controller must determine the last byte of the
message
TSOM Transmttter Start of Message--WIR b ~ tProvtded TXENA 1, TSOM lnillales start of message In BOP, TSOM- 1
generates FLAG and conllnues to send FLAG s until TSOM 0 then begln dala In CCP 1 IDLE =0, transm~tout of
SYNC reg~slerconllnue untll TSOM 0 then begln data 2 IDLE 1 transmtt out of TDB In BOP mode there IS also
a Spec~alSpace Sequence of 16-0 s ln~tlatedby TSOM 1 and TEOM 1 SSS IS followed by FLAG
TEOM Transmlt End of Message-WIR b ~ tUsed to lermlnate a message In BOP mode TEOM 1 sends CRC, then
FLAG. 11TXENA 1 and TEOM - 1 contlnue to send FLAG s. ~f TXENA 0 and TEOM- 1 MARK llne In CCP 1
IDLE 0 TEOM 1 send SYNC 11TXENA 1 and TEOM 1 contlnue lo send SYNC s, l f TXENA-0 and TEOM= 1
MARK hne 2 IDLE I.TEOM 1, MARK llne
TXAB Transm~tterAbort-WIR b ~ tIn BOP mode only. TXAB= Ifln~shpresent character then 1 lDLE=O, transmtt ABORT
2 IDLE 1 transm~tFLAG
TXGA Transmlt Go Ahead-WIR b ~ tIn BOP mode only, modtf~escharacter called for by TEOM GA sent In place of FLAG
Allows loop term~nat~on-GAcharacter
TERR Transm~tterError-read only b ~ tUnderflow, set hlgh when TDB not loaded In t ~ m e l o malntaln continuous
lransmlss~onIn BOP automattcally lransm~l1 IDLE 0. ABORT 2 IDLE 1. FLAG In CCP automat~callytransm~t
1 IDLE - 0 SYNC 2 IDLE- 1 MARK Cleared by TSOM
XYZ Z Y X -W/R btts These are the error control blts
0 0 0 X16+ XI2+ X5+ 1 CCITT-ln~tiallze to 1 '
0 0 1 X1et XI2+ X5+ 1 CClTT-In~t~al~ze lo ' 0 '
0 1 0 Not used
0 1 1 XI6 t X15 1 X2 I 1-CRCl6
1 0 0 Odd Parlty-CCP Only
1 0 1 Even Par~ty-CCP Only
1 1 0 Not Used
1 1 1 lnhtb~lall error detect~on
Note Do not mod~fyXYZ unttl both dala paths are idle
IDLE IDLE mode select-WIR bll Effects lransm~lteronly In BOP-control the type of character sent when TXAB
asserted or In the event of data underflow In CCP-conlrols the method of lnlt~alSNYC character transm~ss~on and
underflow 1 transmlt SYNC from TDB 0 lransm~tSYNC from SYNC ADDRESS regtsler
SEC ADD Secondary Address Mode-W/R bll In BOP mode only-after FLAG looks for address match prior to act~val~ng
RDP 1f no match found, begtn FLAG search agaln SEC ADD b ~should l not be set 11EXADD 1 or EXCON 1
STRIP SYNCILOOP Str~pSync or Loop Mode-WIR b ~ tEffects recelver only In BOP mode-allows recogn~l~on of a GA characler In

PROTOCOL
'APA
CCP-after second SYNC strlp SYNC when flrst data character detected set RXACT- 1. stop strtpptng
PROTOCOL-WIR bit BOP 0. CCP - 1
All Part~esAddress-WIR b ~ tIf selected, mod~fiessecondary mode so that the secondary address or 8-1 s will
actlvate the RDP
e
TXDL Transmitter Data Lenglh-WIR blls
TXDL3 TXDL2 TXDLI LENGTH
0 0 0 Elght blls per character
1 1 1 Seven btls per character
1 1 0 SIX blts per character
1 0 1 F~vebits per character
1 0 0 Four blts per characler'
0 1 1 Three blts per character'
0 1 0 Two bits per character'
0 0 1 One b ~per
t character'
'For data length only not to be used for SYNC character (CCP mode)
RXDL Recelver Dala Length-WIR b~ts
RXDL3 RXDL2 RXDLl LENGTH
0 0 0 Elght btls per character
1 1 1 Seven blts per characler
1 1 0 SIX blts per character
1 0 1 F~vebits per character
1 0 0 Four blts per character
0 1 1 Three blts per character
0 1 0 Two blls per character
0 0 1 One b ~pert character
EXCON Extended Control Ftcld-W/R bll In rece~veronly. 11set, will recelve control f~eldas two 8-bit bytes Excon btt should
not be srt 11SEC ADD 1
EXADD Extended Addreqs Flcld - W/R bll It1 rccetvcr only I SO of dddrrss bytr t ~ s t e dfor a 1 If NO-conl~nue recelvlng
address bylrs 11 YES go Into control f~cldEXADD b ~should
t not bo s(.t 11SEC ADD 1
'Note Thls feature does not cx~slIn the presenl verslon of the COM5025 It IS In the Rrv A vt,rslori dor out In ~ a r l y3 0 7 7
ND-12.018.01
 Register Bit Assignment Chart 1
REGISTER DP07 DP06 D~d5 DP04 DP03 DP02 DPdl Df'Iw
Recelver Data RD7 RD6 RD5 RD4 RD3 R D2 RDl RDEf
Buffer
(Read Only- MSB LSB
Rlght Jusllf~ed-
Unused 611s - 0 )
Transm~tterData TD7 TD6 TD5 T D4 TD3 TD2 TD 1 TD%
Register
(ReadlWrite- MSB* LSB
Unused Inputs X)
SynclSecondary SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSAl SSAB
Address
( ReadIWrlte- MSB LSB
Rlght Justlf~ed-
Unused Inputs X)

I
Register Bit Assignment Chart 2
REGISTER DP15 DP14 DP13 DP12 DP11 DP~$ DP09 ~ ~ 6 8
Recelver Status ERR CHK C B A ROR RABIGA REOM RSOM
(Read Only)
TX Status TERR 0 0 0 TXGA TXAB TEOM TSOM
and Control (Read Only)
(ReadIWrite)
Mode Control *APA PROTOCOL STRIP SECADD IDLE Z Y X
(ReadlWrite) SYNC1
LOOP
Data Length TXDL3 TXDL2 TXDLI EXADD EXCON RXDL3 RXDL2 RXDLl
Select
(ReadIWrite)

Register Address Selection

f"Q
:s-
1) BYTE OP 0, data port 16 b ~ t w
s ~de
A2 A1 A$ Register
0 0 X Recelver Status Reg~sterand Recelver Data Buffer
0 1 X Transmitter Status and Control Reg~slerand Transmitter Data Buffer
1 0 X Mode Control Reglster and S ~ ~ C l ~ d d r Reg~ster
ess
1 1 X Data Length Select Reglster
X = don't care

2) BYTE OP
A2
- 1, data port 8 blts wlde
A1 A0 Register
0 0 0 Recelver Data Buffer
0 0 1 Receiver Status Register
0 1 0 Transmitter Data Buffer
0 1 1 Transmltter Status and Control Register
1 0 0 SYNClAddress Register
1 0 1 Mode Control Register
1 1 0
1 1 1 Data Length Select Register
 TRANSMITTER OPERATION
Apply Power
PutseMR TSO 1 Protocol BOP
TBMT
TXACT 0
TSA 0
-
1 APA - NO
Loop NO
Sec Add NO
RXACT - 0 IDLE - ABORT Character
RDA = 0 ZYX C C I U - I
RSA 0 TXDLI, TXDL2. TXDLl = 8 b ~ t
RXDL3. RXDL2. RXDLl 8 b ~ t
EXADD - NO
EXCON NO
All reglster b ~ t set
s lo zero
Set Byte Op :1 (8 bits)
Apply TCP
Note Example bebw based on lnltlally Masler Resetting If other
condlllons are required (different Mode Control settings) load prlor
toTSOM 1

CONTROLLER USYNRT COMMENT

TXENA= 1 T y p ~ c aEnding
l Sequences
TXGA =TXAB =
4
-
TEOM-0.
TSOM = 1 - wrltlng Into TX
Status 8 Control
I TXGA TXAB-
TSOM 0.
TEOM - 1
-..
- TBMT 0
end of message

Reqlsler
TSO CRC
-TBMT 0 -TBMT t
cTXACT 1 TSO - FLAG
TSO FLAG TSGA TXAB share flag. lor next
TXGA- TXAB
TEOM=TSOM=O-'
- -TBMT= 1
lake down TSOM
TSOM TEOM - 0 -*

Load Address
--TBMT 0
lrame
Ignore
must be loaded prlor
-
--+
+- TBMT 0 Ignore
Byte to TBMT -. 1
Load Address musl be loaded
Byte prlor to TBMT - 1
.-TBMT 1
TSO Address - --
Character
Load Control OR
Byte -- --- ----
a-TBMT 0
.-TBMT t end of message
TSO Control
Character
t
Load Data __ 11other than 8 blts
Length desired musl be fin- TSO FLAG 11deslred repeat
lshcd prlw to TBMT FLAG sequence
returning l o a "I'

Load Data -
-TBMT 0 TBMT 0
-TBMT t . TBMT 1
TSO - DATA TSO FLAG 01 next lrame
Load Data - TXGA TXAB
take down TSOM
--TBMT - 0 TEOM TSOM o-'
-TBMTy 1 .-TBMT 0 tgnore
repeal sequence un- Load Address -_ must be loaded prlor
111all DATA loaded Byte 10 TBMT- 1

-TBMT 1 last data charac-

I
TSO = Last Data
Byte
ler being trana-
mltted
- OR

TXGA TXAB=
TSOM- 0, A end of message
TEOM - 1
. TBMT 0
TSO CRC
TBMT 1 llag wilt be sent
TSO FLAG
TXENA 0
TSO 1 allor FLAG. shul down
TX mark llne
TXACT 0
 RECEIVER OPERATION

.
Apply Power
Pulse MR TSO - 1
TBMT 1
Protocol BOP
APA NO
CONTROLLER
WIR - 1, DPENA - USYNRT COMMENT
11required, load Mode
Control and Data Length
TXACT - 0 Loop NO Select Registers
TSA 0 Sec Add NO enable receptlon begln
RXACT 0 IDLE - ABORT Character FLAG search
RDA = 0 ZYX CCITT-1 USYNRT synchronzed be-
RSA -- 0 TXDL3. TXDC2. TXDL1 - 8 b ~ t gin l~lllng
p~pel~ne
RXDL3 RXDLP, RXDLI - 8 b ~ t
EXADD NO
-RDA
RSOM 1 -
1. RXACT= 1. address byte (8 b ~ t )
ava~lable

Set Byte Op - 1 (8 bits)

EXCON NO
All reglsler blts set to zero W/R=O. DPENA -
--RDA-0
RSA not ra~sed
read address byte

-RDA- 1. RSOM-0 control byte (8 bit)

APPW RCP

Note Example below based on ln~l~ally

Masler Resetting If olher cond~t~ons are
W/R -0, DPENA -
-RDA 0
available
read control byte

requ~red(d~flerenl
Mode Control or Data Length settings) load prlor to .-RDA 1 llrst data byte (n b~ts)
RXENA = 1
I
WIR-0, DPENA -
-RDA 0
available
read data byte

-ADA 1. R S A = t last dala byte ava~lable

WIR -0, DPENA - R E O M - 1. RXACT=O

read data byte

W/R=O, DPENA -
6

.-RSA-0
RDA=O
read status

RXENA=O -+ recelver inactwe

-RDA = 1 Nth byte ava~labtecon- ,

troller falls to read

WIR-0. DPENA -.
+

.-
RSA t . R O R = l

RDA 0
RDB overwrlnen
read data byte

W/R O.DPENA read status

. RSA 0
RXENA 0 term~nalereception
RXACT 0

Terminology
Term Definition Term Definition
- - -- -- - - - -- - - -- - - ---- - - -
BOP Bit Oriented Prolocols: SDLC, HDLC, ADCCP GA 01 11 1111 (0 (LSB) followed by 7-1's)
CCP Control Character Protocols: Bisync, DDCMP LSB First transmitted bit, First received bit
TDB Transminer Data Buffer MSB Last transmitted bit. Last received bit
RDB Receiver Data Buffer RDP Receiver Data Path
TDSR Transmitter Data Shift Register TDP Transmitter Data Path
FLAG 01 1 1 1110 LM Loop Mode
ABORT 111 111 11 (7 or more contiguous 1's)
 AC TIMING DIAGRAMS

RCP 1-
TCP 1-
TBMT
RXACT

RDA, RSA
3c
-
DPENA
WIR 1

1
to Transmitter
Registers I
DPENA
WlR 0
to Receiver
Registers
1-
I

RDA, RSA
7
TCP r
-(!)A'
TSO
RXENA
300 ns

TXACT 2 Resets: RDP-RDA, RSA,

RXACT, receiver
into search
mode (for FLAG)
 Receiver Data
and
Receiver Status
Access Sequence

u
Preferred readbnq soquence of recelver RDA and RSA

ENTER

I R r n d ADA anrl RSA prior to re.nr11nq

data or sIa111s I

0
,:,
RSA 1

READ RPB

4
READ RDB

STATUS

Data Port Timing

READ FROM USYNRIT

WRITE TO USY NRlT

 BLOCK DIAGRAM
. 7

MASTER
RESET

RCP 0
-
0 k 0 'CP

RKENA 0 - - 0 -.i',A
axacT TIMING 8 CONTROL
0 -"aL-
RDA
'S*
RSA 0 - e 7 3 h t -

-1 5i= aL 3 i - l c u -

Y 1
TX PARITY GEN
-
O=a------ SYNC ADDR
SFR
COMPARE
IL

TX CRC GEN
--

-la
TXSEQ A. j - r 3 - -
-5v gc
GND (>c

.- - =
v
T5- V1\> 6 -2V-ilOL

r , 9
RCVR MODE DATA TX ACVR SYNC TX
STATUS CONTROL LENGTH SEL STATUS B DATA ADDRESS DATA
REG REG REG CNTRL REG BUFFER REG BUFFER
. J
4

TRl STATE I 0 BUS ADDRESS DECODE TRl STATE I 0 BUS

1 1
b b b b l d b d W
mls DBlr Det3 m12 Dell D B I ~ DM9 OBOE A0
a A, dA, WR d DPENI BYTEOP
~ o m
b oem
" d D w DB13
d Den
i b DBH d
A .3 HDLC LINE CONNECTION AND DRIVER SPECIFICATIONS
 - -- .
! Titlo
- ; 1): ,.,,I!.,$ co.
AIS I!OXSI; DA'TA- 1 H D L C ~)i!'s~l
1I ti 1
ELCi;TZQfi!ll<I< 1~
\'-?/;,I>::! is 1.

. A

w
0
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10 10' bids
Data signalling rate I ~III-~II*-A

Data signalling rate versus cable length for unbalanced interchange circuit related to
V.lO, X.26, R S 423.
 .-
lo' 10' to'
Data signalling rate
Curve 1 : terminated interchange circuit
Cur* 2 : unterminstsd interchange circuit

Data signalling rate versus cable length f o r balanced interchange circuit related t o
V.11, X.27, RS422.
 SUMMARY OF EIA RS-422 STANDARD FOR A BALANCED DIFFERENTIAL INTERFACE
-- ---- -- --

1
-- ---..- - -. - .-. -----. --- --- -- -- - -

A. Line Driver B Line Receiver

Open C ~ r c u Voltage
~t (ellher loglc state) S ~ g n dVoltage
l Range
D~fferent~ai jVdol 6 OV -. D~ffererit~al lVdl - 6 OV
Common Mode lVcn,oI ' 3 @v Cornrnon M o d e IVLMI ' 7 ov

I Dlfferent~alOutput Voltage (across 100 o h m load)

Ellher logic state IV,,I -
max (05V, 2 OVI
S~nglo.EndedInput Current (power O N or OFF)
E~ttiorlrrput at V,
i

f Output Impedance Other input Grounded

Ellher loglc state
Mark-Space Level S y r n n ~ e t r y(across 100 o h m load)
Srtigle Ended Input B ~ a Vbltage
s
Elltier Input Open C ~ r c u ~ t
(other tnput grounded)
IVt,I 3OV -
I
D~fferenttai
Common Mode
IVd5l
lvcrnsl
IV,,MI - 0 4V
I v c n l ~ I 0 4V
Single Eritled Input Impedance (other Input grounded)
E ~ t h e rInput RL . 4000 o h m s
I
I
I
Output Short Circu~tCurrent (to ground) D ~ f f e r e r ~ tThreshold
~i~l Sens~tiv~ty
Ellher Output 1Is,1 - 150mA C o m ~ n o rhlotle
l Voltaye Rango \V,,I - 7.0V

i Output Leakage Current (power o f l ) E ~ t h e rLogic St;cte jVT1 . 200mV

I
Voltage Range 0 25V . V, - OV
I6 At>solule M d x ~ r n u r nInput Voltage
Ellher Output at V, (I,\ . 1001~A D~fferer~t~dl IVdI ' 12V
R ~ s eand Fall T~rries(across 100 ohrn loiltl) Single Ended IV,l ' 1OV
T - Baud interval (I,,tl) - max (0.1T. 20ns) lrlput Bdlarice (threshold s h ~ f t )
R ~ n g l n g(dcross 100 o h m lodd) Corilmon M o d e Volt,~ge Range L 7 ov
Dlfferent~,~l
Threshold (500 ohms In serles wrth edch
Def~nlt~ons
~npirl)
Vdss Vd (steddy state) Either Logrc State lVll 400mV -
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L ~ m ~(ecther
ts
Percentaye
Absolute
i o g ~ cstate)
lv6 vdssl a 0 ~ V S S
2 OV - lVdl . 6 0 V
T e r r n ~ n a t ~ o(optional)
n
Total Load Res~stance( d ~ f f e r e n t ~ a l ) RT
Multiple Receivers (bus appiicat~ons)
. 90 ohms
I
I
U p to 10 receivers allowed D ~ f f e r e n t ~threshold
s ~ t c v ~of
t y 2001nV must t)e malntdlned
Hysteres~s( o p t ~ o n a l )
al sen-

I
As r e q u ~ r e dfor app!ications w i t h slow riselfall time at
recerver, t o control Osc~llations
Fall Safe ( o p t ~ o n a l )
As r e q u ~ r e dby appllcatlon to provide a steady MARK or
SPACE c o n d ~ t ~ ounn d e r o p e n connector or d r ~ v e r
power
OFF c o n d ~ t i o n .

C. lnterconnectlng Cable
TYPO
Twlsted Pair W ~ r eor Flat Cable Conductor Pair
Conductor Scze
Copper W ~ r e(solld or stranded) 24 AWG or larger
Other (per conductor) R . 30 ohms11000 h
Capac~tance
Mutual P a ~ r
Stray
Pair-to Pair Cross Talk (balanced)
A t t e n u a t ~ o nat 150KHz
A.4 HDLC DATA - HDL C DMA CONTROL INTERCONNECTION
 Card M t x l u i e :

T h e irirerfdce m o d u l e IS fi: . n t o a 100 t e r m i n a l

c o n n e c t o r w h e r e 4 o f t h e termtnais are used f o r
p o w e r ( 6 V ) a n d 4 r e r r n ~ n a l sf o r g r o u n d (GND)

T h e t e r m ~ n a l ; 4-55 are ass$c,ned f o r t h e local l i O

BUS, w h ~ i et e r m i n a l 56-95 are used f o r c o n n e c t i o n
t o t h e externdl device via t h e plug-panel.

Local 110 Bus Siqnal Levels:

> Locai 1/0 Bus L o c a l 1/0 Bus siandls are T R I - S T A T E T f L fcr a11
s ~ g c a i se x c e p t ~ n t e r r u p lines
t a n d D N A request
line, whic5 a t e o p e n c o l l e c t o r T T L .

LocjicaI "1" signal O (S C Q.4v

t o q r w l "0" signal 2,4 S 5-5 V

/'L These terrntrlals d o n o t

have a 1-1 c o n n e c l t o n :o
' '/ t h e n e x t l/C m s i t l o n
(used f o r IDEPJT and GRAI'JT,
A.4.1 Speed Selection (Switch Setting on 7 7871 Intercomputer Link

2,400 bps OFF OFF OFF ON OFF ON

4,8000 bps OFF OFF ON OFF OFF ON
9,600 bps OFF ON OFF OFF OFF ON
19,200 bps ON OFF OFF OFF OFF ON
38,400 bps OFF OFF OFF ON ON OFF
76,800 bps OFF OFF ON OFF ON OFF
153,600 bps OFF ON OFF OFF ON OFF
307,200 bps ON OFF OFF OFF ON OFF
A.5 PROGRAMMING SPECIFICATIONS

The HDLC interface for NORD-10 computers is designed around a Mutti Protocol
Communication Controller, MPCC, of the type X2652 from Signetics or the
almost equivalent COM 5025 from SMC Micro systems.

Sixteen different I10 instructions are used t o control the interface. Eight are used
t o read from or write into the MPCC, four are for status and control and four are
for DMA Module Address and Command.

Possible interface standards a re:

a) CClTT V-24, CClTT X-21 BIS, CClT X-21 (X-27 signal levels), EIA RS-232-C
and EIA RS-422.

b) CClTT V-35.

The interface is also equipped with an internal clock which makes it easy for two
interfaces to communicate without external communication equipment
(MODEMS).

The interface may be extended with a DMA module to reduce software load o n
interrupt and I 1 0 handling. Four I10 instructions are used separate from the DMA
module and four are used together with data module.

The 16 110 instructions are:

Group No. +0 Read Receiver Data Register

Group No. +1 Write Parameter Control Register
Group No. +2 Read Receiver Status
Group No. +3 Write Synchl Address Register
Group No. +4 Write Character Length
Group No. +5 Write Transmitter Data Register
Group No. +6 Read Transmitter Status Register
Group No. +7 Write Transmitter Control Register
Group No. + 10 Read Receiver Transfer Status
Group No. + 11 Write Receiver Transfer Control
Group No. + 12 Read Transmitter Transfer Status
Group No. + 13 Write Tranmitter Transfer Control
GroupNo. + 14 Read DMA Address
Group No. + 15 Write DMA Address
Group No. + 16 Read DMA Command Register
Group No. + 17 Write DMA Command

Instructions 0-7 operate directly on the MPCC. For a detailed description of these
registers (bit mapping, etc.) the reader is advised to study the data sheets from
the manufacturers or the HDLC Interface Control Hardware Manual (ND-11.018).

Note that all I10 instructions operate only on bits 0-7 when the DMA module is
not installed.

In this text registers 0-7 are named related to X2652 Signetics notations. For cross
reference to COM 5025 and HDLC Hardware Manual equivalent register notations
are given.
A.5.1 /OX Instruction Overview Table

IOX + GP 0, Read Receiver Data Register:

Receiver Data Register is the low byte of the Receiver DataIStatus Register
(RDSRL) as described in the data sheet. A n assembled character (byte) is read
from the interface into the A register in the CPU. (Character length is specified by
IOX GP + 4 or indicated by RDSRH (IOX GP + 2.) The received character is right
justified.

IOX GP + 1, Write Parameter Control Register (PCSARH):

This is the high byte (bits 8-15) of the Parameter Control SyncIAddress Register
(PCSARH) described in the data sheet. The register defines protocol, etc. Refer
t o the data sheet.

IOX GP + 2, Read Receiver Status Register:

This is the high byte of the Receive DataIStatus Register (RDSRH) and contains
receiver status information. Bit mapping is described in the data sheet.

IOX GP + 3, Write SyncIAddress Register:

The SyncIAddress Register holds the secondary station address in bit-oriented
procedures or the SYNC character in byte-oriented procedures. it is the lower
byte (Byte Control Procedure) of the Parameter Control SyncIAddress Register
(PCSARL). Refer t o the data sheet.

IOX GP + 4, Write Character Length:

The high byte of the Parameter Control Register (PCRH) is used t o specify
character length for receiver (bits 0-2) and transmitter (bits 5-71.A t this point the-
re is a difference between X2652 and Signetics and COM 5025 from SMC Micro
systems. See the data sheet. Equal operation when bits 3 and 4 are 0.

IOX GP + 5, Write Transmitter Data Register:

The low byte of the Transmit DataIStatus Register (TDSRL) holds the character
t o be transmitted. The Qharacter length is specified by IOX GP +
4. Character
must be right-justified.

IOX GP + 6, Read Transmitter Status Register:

The high byte of the Transmit DataIStatus Register (TDSRH) contains
transmitter command and status information. The functions of the different bits
are described in the data sheets.

IOX GP + 7, Write Transmitter Control Register:

This is the same byte as may be read by IOX GP + 6.
IOX GP + 10, Read Receiver Transfer Status:
The low byte is the receiver transfer status from the data modules. The high byte
is the transfer status from the DMA module, and is not used unless the D M A
module is installed.

Bit mapping:

0R EMTY LE F E BE Rl DSR SO i!
DMA O N L Y

Bit 0: Data Available

lndicates that a character has been assembled and may be read

from the Receiver Data Register (RDSRL). Interrupt on level 13
if enabled.

Bit 1: Status Available

Indicates that status information is available in the Receiver

Status Register (RDSRH). Interrupt on level 13 if enabled.

Bit 2: Receiver Active

The receiver has seen the start of a frame, but not the end. This
means that the receiver is active within a frame.

Bit 3: Sync1Flag Received

A t least one SYNC character or FLAG has been receiver after

the last reading of Receiver Transfer Status or Master Clear1
Device Clear.

Bit 4: 0 ( D M A Module Request)

This bit is activated by the DMA module. If the DMA module is

installed, this bit may be the reason for an interrupt on level 13 if
enabled. It is, however, always read as 0 because it is cleared at
the beginning of IOX GP +
10. If the DMA module caused an in-
terrupt, the reason for this interrupt is given in the most
significant byte of the Transfer Status.

Bit 5: Signal Detector (SD)

1,
Status of the Signal Detector (CCITT circuit 109) from the Data
Communication Equipment. A change in the status causes an
interrupt o n level 13 if enabled.

Bit 6 : Data Set Readyll (DSR)

Status of the Data Set Ready (CCITT circuit 107) signal (V-24,
X-21 BIS) or the I signal (X-21) from the Data Communication
Equipment. A change in the status causes an interrupt on level
13 if enabled.
Bit 7: Ring lndicator (RI)

Status of the Ring Indicator (CCITT circuit 125) from the Data
Communication. A change in the status causes an interrupt on
level 13 if enabled.

Bit 8: Block End Status bit from DMA module.

Bit 9: Frame End Status bit from DMA module.

Bit 10: List End Status bit from DMA module.

Bit 11: List Empty Status bit from DMA module.

Bit 15: Receiver Overrun Status bit.

Note: Bits 8-15 are cleared by reading the Receiver Transfer Status.

IOX GP + 11, Write Receiver Transfer Control:

The low byte is for interrupt and data enabling on the data module and also some
Data Communication Equipment control signals. The high byte is for DMA
module control signal.

Bit mapping:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LE PE RE MIF Malnt Int En. Int Inl
In? In* In1 Inl O T A (0." En. DMA R X E En, En*
En. En. En. En. cl..rl DM statu Dare

DMA ONLY

Bit 0: Data Available Interrupt Enable

A 1 in this bit together with Data Available (RXDA) will cause an

interrupt on level 13. The bit is cleared by a servicing IDENT, by
MASTER CLEAR and by DEVICE CLEAR.

Bit 1: Status Available lnterrupt Enable

A 1 in this bit together with Status Available (RXSA) will cause

an interrupt on level 13. The bit is cleared by a servicing IDENT,
by MASTER CLEAR and by DEVICE CLEAR.

Bit 2: Enable Receiver ( RXE)

Incoming serial data stream is enabled into the receiver. The bit
is cleared by MASTER CLEAR.

Bit 3: Enable Receiver DMA

With a 1 in this bit, Data Available (RXDA) will cause a request

to the DMA module. The bit is cleared by MASTER CLEAR and
by a "List Empty" key during DMA operation.

Bit 4: DMA Module Interrupt Enable

A 1 in this bit together with a request from the DMA module will
cause an interrupt on level 13. The bit is cleared by a servicing
IDENT, by MASTER CLEAR and by DEVICE CLEAR.
Bit 5: Device ClearISelect Maintenance

Writing a 1 into this bit first gives a DEVICE CLEAR, clearing

interrupts and interrupt enabling flip-flops, control signals to the
Data Communication Equipment, transmitter control signals,
Data Communication Equipment status latches and the Multi
Protocol Communication Controller. Then it turns the Multi Pro-
tocol Communication Controller into maintenance mode, lo-
oping transmitted data back to the received data. When the inter-
face is in maintenance mode, the DEVICE CLEAR function is
disabled. The bit is cleared by MASTER CLEAR.

Bit 6: Data Terminal ReadyIC (DTR)

This bit controls a line to the Data Communication Equipment. It

is the Data Terminal Ready (CCITT circuit 108) signal (V-24,
X-21 BIS) or the C signal (X-21). The bit is cleared by MASTER
CLEAR.

Bit 7: Modem Status Change lnterrupt Enable

When set, this bit will cause an interrupt on level 13 when one or
more of the Data Communication Equipment status signals
connected to the receiver changed to a state different from the
last reading (SD, DSII, RI). The bit is cleared by servicing
IDENT, by MASTER CLEAR and DEVICE CLEAR.

Bit 8: Block End lnterrupt Enable

This bit will, together with Block End and DMA Module lnterrupt
Enable, cause an interrupt on level 13.

Bit 9: Frame End lnterrupt Enable

This bit will, together with Frame End and DMA Module Inter-
rupt Enable, cause an interrupt on level 13.

Bit 10: List End lnterrupt Enable

This bit will, together with List End and DMA Module lnterrupt
Enable, cause an interrupt on level 13.

Bit 15: Always 1 after IOX + 11 if inspected after a DUMP command

(M11).

Note that List Empty (Receiver Transfer Status, Bit 11) always gives a DMA
Module Request (Bit 4).

IOX GP + 12, Reed Transmitter Status:

The low byte is the transmitter transfer status from the data module. The high
byte is the transfer status from the DMA module if installed.

Bit mapping:

DMA ONLY 1
Bit 0: Transmit Buffer Empty

Indicates that the Transmit Buffer (TDSRL) may be loaded with

a new character. Interrupt on level 12 if enabled.

Bit 1: Transmitter Underrun

Indicates that the Transmit Buffer has not been loaded with a
new character in time. The transmitter will act as defined by the
IOX GP + 1 instruction (PCSARH). The underrun condition
may cause an interrupt on level 12 if enabled. Transmitter
Underrun may be cleared by Master Clear, Device Clear or
Transmit Start of Message (TSOM) command.

Bit 2: Transmitter Active

This bit is turned on by sending Start of Message. It will go off

when Transmitter Enable (TXE) is turned off and the characters
or sequences already in the transmitter are shifted out on the
Transmit Data Line (TSO).

Bit 3: Not used

Bit 4: 0 (DMA Module Request)

This bit is activated by the DMA module, and thus it has no
meaning unless the DMA module is installed. It is, however,
always read as 0 because it is cleared at the beginning of IOX GP
+ 12. If the DMA module is installed, additional information is
given in the high byte. DMA Module Request causes an inter-
rupt on level 12 if enabled.

Bit 5: Not used

Bit 6: Ready for Sending (RFS)

Status signal from the Data Communication Equipment (CCITT

circuit 106). A change in the status causes an interrupt on level
12 if enabled.

Bit 7: Not used

Bit 8: Block End Status bit from DMA module.

Bit 9: Frame End Status bit from DMA module.

Bit 10: List End Status bit from DMA module.

Bit 11: Transmission Finished status bit from the DMA module.

Bit 15: Illegal Key or Illegal Format in Transmitter Buffer Descriptor

This status bit indicates an error stop and the transmitter should
be restarted.
IOX GP + 13, Write Transmitter Transfer Control:
The low byte is for interrupt and data enabling on the data module and also two
signals concerning the connection to the Data Communication Equipment. The
high byte if for the DMA module.

Bit mapping:

LE FE BE MSC Int EN In? Int

Re~ervcdforDMArnodula Int Inr Int In, ROT HD Ena DMA TXE Ena Ena
- Ena. Ena Ena Ena. D MA Stan, Data

DMA ONLY

Bit 0: Transmit Buffer Empty Interrupt Enable

A 1 in this bit together with Transmit Buffer Empty (TXBE) will

cause an interrupt on level 12. This bit is cleared by a servicing
IDENT, by MASTER CLEAR or DEVICE CLEAR.

Bit 1: Transmitter Underrun lnterrupt Enabled

A 1 in this bit together with a Transmitter Underrun condition

will cause an interrupt on level 12. The bit is cleared by a
servicing IDENT, by MASTER CLEAR and by DEVICE CLEAR.

Bit 2: Transmitter Enabled (TXE)

A 1 in this bit together with Ready for Sending (RFS) (CCITT

circuit 106) enables the transmitter part of the Multi Protocol
Communication Control (MPCC) to be 1 (MARK) and the
Transmitter (TXA) to go off when closing flag or last character
has been transmitted. The bit is cleared by MASTER CLEAR and
by DEVICE CLEAR.

Bit 3: Enable Transmitter DMA

With a 1 in this bit, Transmitter Buffer Empty (TXBE) will cause

a request to the DMA module. This bit is cleared by MASTER
CLEAR by Transmission Finished or by Illegal Key/Format
(DMA operation).

Bit 4: DMA Module lnterrupt Enable

A 1 in this bit together with a request from the DMA module will
cause an interrupt on level 12. The bit is cleared by a servicing
IDENT, by MASTER CLEAR and by DEVICE CLEAR.

Bit 5: Half Duplex

A 1 in this bit will cause the interface to operate in a half duplex

mode. The request to send (ROTS) (CCITT circuit 105) signal is
not turned ON unless the Signal Detector (SD) (CCITT circuit
109) is off. A 0 in this bit will cause the interface to operate in a
full duplex mode. The bit is cleared by MASTER CLEAR and by
DEVICE CLEAR.
Bit 6: Request to Send (ROTS)

This is a control signal to the Data Communication Equipment

(CCITT circuit 105). In full duplex, 1 means ON and 0 means
OFF. In half duplex, Signal Detector (SD) (CCITT circuit 109)
must be OFF before the Request to Send line goes ON. Normal
response from the Data Communication Equipment is to turn
Ready for Sending (CCITT circuit 106) ON when Request to
Send is ON. The bit is cleared by MASTER CLEAR and by
DEVICE CLEAR.

Bit 7: Modem Status Change Interrupt Enable

When set, this bit will cause an interrupt on level 12 when Ready
for Sending from the Data Communication Equipment changes
to a state different from the last reading. The bit is cleared by
servicing IDENT, by MASTER CLEAR and by DEVICE CLEAR.

Bit 8: Block End lnterrupt Enable

This bit will, together with Block End and DMA Module lnterrupt
Enable, cause an interrupt on level 12.

Bit 9: Frame End lnterrupt Enable

This bit will, together with Frame End and DMA Module
lnterrupt Enable, cause an interrupt on level 12.

Bit 10: List End Interrupt Enable

This bit will, together with List End and DMA Module lnterrupt
Enable, cause an interrupt on level 12.

Bit 15: Always 1 after IOX GP + 13 if inspected after a DUMP

command (MI51

Note that Transmission Finished (Transmitter Transfer Status, bit 11) always
gives a DMA Module Request (bit 4).

Note that bit 15 is 1 if inspected after a DUMP command.

IOX GP + 14, Read DMA Address:

The last value written to this register by IOX GP + 15 is read back. May be used
for debugging or control.

IOX GP + 15, Write DMA Address:

The 16 least significant bits for the first location in a loadldump area or the first
location in a list of buffer descriptors are written into a register (M3) in the DMA
module.

IOX GP + 16, Read DMA Command Register:

Before a new command is written to the DMA module, this register should be
inspected. If it is zero, the new command sequence can be started. If not, wait un-
til it becomes zero. A MASTER CLEAR command sequence can, however, be
started even if the command register is not zero.
IOX GP + 17, Write DMA Command:

The two most significant bits of the address for the first location in a loadldump
area or the first location in a list of buffer descriptors are written into a register
(M2) in the DMA module together with a value giving one of 8 commands. The
data format for this instruction is described in the next section.

The HDLC DMA module is partly controlled by 110 instructions, and partly by con-
trol information in buffers in main memory. 110 instructions are used to set buffer
addresses, to start operations (give commands), to enable interrupts and to read
status.

Control information in the memory is used as additional information for the inter-
face when an operation has been started (by a command).
@
A.5.2 The Commands

The commands may be divided into 3 groups:

1. Device Clear ( 1)
2. Load/ Dump and Initialize (4)
3. Data Transfer (3)

Device Clear

is started by placing octal 40 in the A register and executing IOX GP + 17

(octal).

Load/ Dump and Initialize

is started by first writing the least significant 16 bits of a buffer address to

the interface (IOX GP + 15 (octal)) and then writing the two most
significant buffer address bits (bank bits) together with the command bits t o
the interface (IOX GP + 17 (octal)).

Data Transfer

is started by first writing the least significant 16 bits of a buffer address to

the interface (IOX GP + 15 (octal)), then the two most significant bits (bank
bits) together with the command bits (IOX GP + 17 (octal)) and at last
enable interrupt and DMA module (IOX GP + Il(octal) for receiver and IOX
GP + 13 (octal) for transmitter).

A command sequence should never be interrupted.

The Specific Commands

Eight different commands may be used. They are:

A register when IOX GP + 17 is executed. Y is bank address: BE. P,3]

- Device Clear
- Initialize
- Receiver Start
- Receiver Continue
- Transmitter Start
- Dump Data Module
- Dump Register
- Load Register

Device Clear (Command 0)

Recommended program for Device Clear is:

SAA 0 % A register = 0
+
IOXGP 11 (octal) % Write Receiver Transfer Control
BSET ONE 50 DA % A register = 40 (octal)
+
IOX GP 11 (octal) % Device Clear t o Data Module
IOX GP +
17 (octal) % Device Clear to DMA Module

The Device Clear sequence as described above will stop all data transfers t o and
from the interface and it can be used at any time. Device Clear will clear all
interrupts from the interface and a dialed up modem connection will be broken.
Initialize (Command 1

The Initialize sequence uses 7 locations in memory. The contents of the locations
are:

1. Parameter Control Reg. (8 least significant bits)

2. SyncIAddress Register (8 least significant bits)
3. Character Length (8 least significant bits)
4. Displacement 1 (No. of bytes, first block in frame)
5. Displacement 2 (No. of bytes, other blocks in frame)
6. Max. Rec. Block Length (No. of bytes, including displacement)
7. Checksum ( 102164 is written back from interface

The content of the 3 first locations are written into the Data Module and the
mapping of the control bits are described in data sheets for SMC COM 5025 and
Signetics MPCC 2652. Displacement 1 is the number of free bytes reserved at the
beginnning of each buffer containing the start of a message (Frame). Displace-
ment 2 is the number of free bytes reserved at the beginning of each buffer which
does not contain the start of a message (Frame). Maximum Receiver Block
Length is the total number of bytes in a receiver buffer, including displacement.
The Checksum written back from the interface may be used as a control. The
interface should not be used in DMA mode if this checksum is wrong.

Receiver Start (Command 2)

The address written to the interface in a Receiver Start sequence is denoted a

"List Pointer". The address is the first address of a list containing "Buffer Descrip-
tors" (see the HDLC DMA List Structure). This command also selects Displace-
ment 1 for the first buffer and should therefore be used the first time the receiver
is started after a power up or receiver disable.

Receiver Continue (Command 3)

This command is used to write a new List Pointer to an enabled and working inter-
face. It should only be used as a response to a "List Empty" interrupt.

Transmitter Start (Command 4)

This command is always used to start transmission of data. The address written to
the interface is the "Transmitter List Pointer" or the start address for the list of
"Buffer Descriptors".

Dump Data Module

This command is mainly for maintenance purposes. It requires 5 location in

memory, where the contents of the following registers are stored:

1. Parameter Control Reg. (8 least significant bits)

2. SyncIAddress Register (8 least significant bits)
3. Character Length (8 least significant bits)
4. Receiver Status Register (8 least significant bits, not accumulated)
5. Transmitter Status Reg. (8 least significant bits, not accumulated)

The contents of the registers in the Multi Protocol Communication Controller

(MPCC) is transferred to memory. The Receiver Status Register is also ORed into
the Receiver Dataflow Status Register to prevent loss of information.
 Dump Register

This command can be used to dump the contents of any number of the 256
random access memory registers in the DMA module. Required space in memory
is 2 locations plus 1 location for each register to be dumped. The contents of the 2
locations are:

1. First Register Address

2. Number of Registers

If both values are zero, the contents of the 16 registers in the Bit Slice are written
into memory.

The meaning of the different values are illustrated in the figure below.

DMA COMPUTER
MODULE MEMORY

Address written
by IOX GP 15,lOX GP

Load Register

This command can be used to load any number of the 256 random access
memory register in the DMA module. Required space in memory is 2 locations
plus 1 location for each register to be loaded. The contents of the 2 locations are:

1. First Register Address

2. Number of Registers

The Load Register command is simular to Dump Register except that data is
moved in the opposite direction. It is not possible to load the register in the Bit
Slice by this command.
 HDLC DMA LlST STRUCTURE

DATA BUFFER
I
LlST POINTER
I-fC !KEY Dataflow Co

BYTE Count
Most Address
Least Address

New List Pointer is old List Pointer+:4,

or loaded from memory (if New List Pointer)

Bits 10 9 8
Key for Empty Receiver Block is 0 1 0 = 10008
Full Receiver Block is 0 1 1 = 14008
Block to be Transmitted is 1 0 0 = 200%
Already Transmitted Block is 1 0 1 = 24008
New List Pointer is 1 1 0 = 30008

Legal Keys for the Receiver = 10008and 30008

Legal Keys for the Transmitter = 20008 and 30008
All other key bit combintations mean list empty.
 HDLC DATA 1181 t
Device No. /dent Code
Switch Position (octal! (octal) Comments

OFF 0
3C1 ON 1
OFF 0
3 C7 ON 7
OFF 0
3C3 ON 4
OFF 0
, 3C4 ON 10
OFF 0
3C5 ON 20
OFF 0
3C6 ON 40
OFF 0
3C7 ON 100
OFF 0
3C8 ON 700
OFF Test, CLK Disconnected
10A1 ON Normal. CLK Connected ,
OFF X-21 Interface
1OA7 ON V-74laterface
OFF 0
. 10A3 ON 20
OFF 0
, 10A4 ON 40
OFF 0
10A5 ON 100
OFF 0
10A6 ON 200
OFF 0
10A7 ON 400
OFF 0
10A8 ON 1000

Standard Device Numbers:

HDLC IOX IbISTRUCTIONS

NOTES:
THIS B I T IS 1 IF INSPECTED AFTER A DUMP COMMAND. DMA PQ IS A L W A Y S READ AS 0 (CLEARED A T THE START OF THE IOX INSTRUCTION] iOX GP+10
or IOX GPt12.
X BIT 5 I N COMMAND SHOULD BE 0 EXCEPT FOR DEVICE CLEAR COMhqAND
 I IOX INSTRUCTION 2 IOX IPISTRUCTION 3 IOX INSTRUCTION MEMORY hr3TES
COMMANDS - _ _ _ -
A REGISTER IOX GP+ A REGISTER IOX G P t A REGIST~R
I _ _
IOX G P t
_ _
BUFFER_ -

DEVICE C L E A R 0 000040 17 - - -

INITIAI.IZE 1 XXXXXX 15 00040Y 17 - PCR I*,\I<ALII rkK(o\rKOI K l ( 1 1 ~ iI<

l
- SA t7 S t \c 4 I ) I ) K t ,S H t ( ~ l 5II k
1: L ( l l \ l < \ (I l l <l l ' . ~ ~ i l l
DlSP 1 I ) I ~ I ~ Ii t I $11 \I, ! I n 5 1 b l w k
DlSP 2 I)I\PI \( I ~ I\ II 111111n ljlck >,t
\lAXHlO(h h i 4 1 ~ l C t l \ l l < l $ i t J h< l l \ l ~ l l l

1 0 2 1 6 4 ( I l l 1 h\L\I I K o h l l \ l t U l A ( I

--
RECEIVkR 51 A R T 2 xxxxxx 15 0 0 100
1' 17 (BIT 3 = I ) 11 I S U ~ F E RO E ~ C R I P T I 4 ) 51 I ( I > 1)1\1' 1

RECEIVER CONTINLJE 3 XXXXXX 15 001 JOY 17 ( B I T 3=1) 1I kBuiFkR u E s c n ~ p T O ~( ~t ~ b l j I\ ~\ \ I [ I ~ \ I

, t I 11 I, ) I > ?
-
TRAI\ISMITTEH START 4 XXXXXX 15 00200'1' 17 13
- --' B I T 3-11
DUMP D A T A MODULE 5 XXXXXX 15 00240Y 17 - - PC R P \ l < + h l l 11 I t C O \ I K C J i l < l ~ 9 1 ~ l t l <
SA R s Y h C 4UL)Hr S 5 K I L I b I t It
CL (li\l'\( l l l ~ L t ~ . \ m I t l
RSR R11 I l \ 1 K 3 1 4 1 1 5 R I (sIb11 R
1 SR I H A h 5 h l l I I I K 5 1 , ~ I ~ (J!ST'
5~I I<

.-
1 REG I) G 1 Kki; 4 377
DUMP REGISTERS 6 xxxxxx 15 003C0Y 17 - - \( V H I H <40O 1 I < I ( . : ) H IJI'.~%I
NtJMtjEH

1 REG r, < I HI(, - 377

LOAD REGISTEAS 7 XKXXXX 15 003.40~ 17 - NU~,~~CR \till K G 4'10 1 KI ( V

XXXXXX 16 LEAST SIGN. BITS OF ADDRESS

-..... Y 2 MOST SIGN BITS OF ADDRESS ( B A N K BITS)
( N B ) IF NUMBER -0 IN DUMP REGISTER. THE B I T SLICE REGISTER BLOCK IS COPIED I N T O M E M O H Y
 TRANSFER STATUS 1ilANSTER CONTROL DATAFLOW STATUS DATAFLOW CONTROL
lox GP + 10, (RTS) (bl10) lox GP + 1 l 8 (R7C) (M11I (RCOST) (M20. R10) (RCOST) (b1120, R 10)

DATA A
-- -V-
-
A-
-ILABLE -.r N A B L E D A T A IIJlEf1RUPT +
RSOlbl - 0 I
5 ii l T l i S A V A I L A B L E ENABLE STATUS INTERRIIPT 0
RXEN 0
ENABLE RECEIVER DMA 0
I
0 (DMA MODULE REQUEST) ENABLE DbIA MOD. INTF-RRUPT RSCL 0 0
-
--
MAlNT RSCL 1 0
1

- - -
ENABLE MOUEhl CHANGE INT. 0
ENABLE BLOCK DONE 0
ENABLE KEY (1)
---- --. ---
LIST END ENABLE KEY (0)

TRANSFER STA 1US TRANSFER CONTROL DATAFLOY! STATUS D A T A F L O h CONTROL

4 17R { TTS) (F"41
lo,! GI' IOX GP + 13R (TTC) (tv? 151 (TCOST) (PA30) (TCOST) (h420)
----- 2

D A l k REOIJEST - ENABLE D A T A INTERRUPT i-s

o rul TSOM
UNOERRUN . E;.IABLE S-rATUS INTERRUPT TEOM TEOM
TX A -- TXEN TABORT TABORT

. ENABLF T&&NMITER DMA TGA TGA

ENABLE
.
- -..--U V A :vlOD.
- INTERnLlPT -. TSC LO TSC LO
tfDX TSC L 1 - < -
TSCL l
F1QTS _ TSCLZ - - TSC L 2
EYARLE
-. .-
- -- R,IODEM CHANGE INT. - TERR 0
--
ENABLE BLOCIC Dot.!€ 0
-- -- -. - --- -
- ENABLE KEY 101 KEY (0)
a IST E N D ENABLE KEY (11 KEY ( 1 ) 1
--- --
1 RP:\IS~IJ~ISSIOPI --
-- --- FINISHED
e
A.5.3 Simple Debugging Programs with Memory Map
HDLC DMA MODULE DEBUGGING PROGRAMS

USES DEVICE NUMBERS 1640- 1657 ON INTERFACE

Device Clear SAA 0

l o x 1651
SAA 40
l o x 1651
IOX 1657
WAlT

LDA "5
IOX 1655
LDA "4
IOX 1657
WAlT
(ADDRESS)
(COMMAND)
ADDRESS /PC R
SAR
CL
DISP 1
DISP 2
MAX BLOCK
CHECKSUM

Dump ALU LDA * 5

IOX 1655
LDA "4
IOX 1657
WAlT
(ADDRESS)
(COMMAND)
ADDRESS 10
0
ALU 0

ALU 17

DUMP MEMORY : LDA " 5

IOX 1655
LDA "4
IOX 1657
WAlT
(ADDRESS)
(COMMAND)
ADDRESS I 0
40 (G377)
MO
-
INIT RECEIVER : LDA +7
IOX 1655
LDA * 6
IOX 1657
LDA *5
IOX 1651
WAlT
(LIST ADDRESS)
(COMMAND)
(CONTROL)

LlST
ADDRESS1 KEY
BYTE COUNT
DATA ADDRESS
DATA ADDRESS
KEY
-

lnit Transmitter : LDA 7

IOX 1656
LDA 6
IOX 1657
LDA* 5
IOX 1653
WAlT
(LIST ADDRESS)
(COMMAND)
(CONTROL)
LlST
ADDRESS1 KEY
BYTE COUNT
DATA ADDRESS
DATA ADDRESS
KEY
-
MEMORY MAPPING FOR HDLC DEBUGGING PROGRAMS
I
Address: Program: I Address: Program:
0 500 Memory Dump
10 ,,
20 Device Clear #,

30 lnit
40 Dump ALU
50 Dump Memory
60 lnit Receiver
70
100 lnit Transceiver 600 Memory Dump
110
lnit Parameters

ALU dump
ALU dump

Receiver List Receiver Buffers

Receiver List ,I

Receiver List
Receiver List
Transmitter List
Transmitter List
Transmitter List
Transmitter List
Transmitter Buffers
,,
320
330
340
350
360
370
400 Memory Dump
,,

The following procedure should move the content of [2004,2023] to [1004,1023]:

Last DMA address (if displayed):

Content of 126 should be:
Content of 200 should be:
Content of 201 should be:
Content of 240 should be:
A.6 HDLC LOGICAL DIAGRAMS
 ACC,
s1
s2
s3
SL
55
WS6

FCSO -
FSEL,
Ct6
FLAG
TRIGGER

;m -
JJ
'1
FSDO

L ,---
T--EW.I~ m ?7
HD&C O W CONTROL
1151 E Port 1
- .-* TU
*I
-.-
 U
'9
RAMS
RAM6
RA M 0,
RAM I,

1.11.1 0.t. I,."

Mh'**tohk
1wmBW 2
c 78
HDLC OMA SHADOW KO",, ru
1932 B i P I-
A/$ N O R S K D A T A ELEKTRONIKK 7823
 h4 I C R 9 CODE
0 LEAST B I T SLICE

A
= 7
TO hlOST B I T SLICE

PO INTER f----'J \ ONE OF 2431(3 x 53 BITS

PAun_lL R80 3 RA 0 3 IAO-3 IBO 3 16 18 15 3 CO MICRO INSTRUCTIONS I N PROM
1

B I T SLICE
DESTINATION
CONTROL
AOH B
F u l v C T l O N SELECT
- -, - -- - -. - - -- - -- - -- - - - - - - -
;I - -1
v I
I -REGIS7'E
- .- R A A OPERAND I
A L U SOURCF 4 BITS D A T A OUT
DArAIN 1 16X4BIT I
REGISTER BLOCK A LU 1 Y811
~ 3 1 18 Y 1 2 15
I B OPERAND I
DB12 15
I I
I . - "__I I ON. oFTbt..lr
SLICES MOST B Y T E
,
L - - - -- - - - - - - - - - - - - - - - - - - - - - - -I

REGISTER A
A OPERAND
A L U SOURCE

1
ONE OF TvVO BIT SLICES
I ! LEAST B Y T E
 NORSK DATA A. S.
L q r e n v e i e n 57 - P o s t b o k s 163, @ k e r n
OSLO 1

C O M M E N T A N D EVALUATION SHEET
HIGH LEVEL DATA LINK CONTROL (HDLC) INTERFACE ND-12.018.01
NOVEMBER 1978

In o r d e r f o r t h i s m a n u a l to develop to t h e point w h e r e i t b e s t s u i t s
your needs, w e must have your comments, corrections, suggestions
f o r additions, etc. P l e a s e w r i t e down y o u r c o m m e n t s on t h i s p r e -
a d d r e s s e d f o r m and p o s t it. P l e a s e be s p e c i f i c w h e r e v e r p o s s i b l e .

FROM
 - we make bits for the future
-

NORSK DATA A.S L0RENVElEN 57 OSLO 5 NORWAY PHONE: 21 73 71 TELEX: 18284