OTN Manual

E1 and T1 Interface Cards

(S30824-Q32-X and -X100)
Doc. No.: AE-M240-E-5
COPYRIGHT AND TRADE SECRETS/LIABILITY
The present document and its contents remain the property of OTN Systems NV and shall not, without prior
written consent, be copied or transmitted or communicated to third parties, nor be used for any other
purpose than such as underlies their delivery to the addressee.

The present document and its contents may change in the course of time or may not be suitable in a
specific situation. Consequently, they are recommended as suggested guideline only.
OTN Systems NV hereby disclaims any liability for any damages that may result from the use of the present
document unless it is used with respect to the operation and maintenance of equipment originally
manufactured by OTN Systems NV and covered by its standard warranty.
Open Transport Network E1 and T1 Interface Cards

Contents
1. INTRODUCTION .........................................................4
1.1 General ................................................................ 4
1.2 References.......................................................... 4
2. E1 AND T1 LINKS .......................................................4
2.1 General ................................................................ 4
2.2 OTN and E1/T1 .................................................. 5
3. CARD DESCRIPTION .................................................6
3.1 Operation............................................................. 6
3.2 Bandwidth Allocation ......................................... 7
3.3 Status and Control Data .................................... 8
3.4 LED Indications .................................................. 9
3.5 Specifications ..................................................... 9
3.6 Applications......................................................... 9
4. INSTALLATION GUIDELINES ................................. 10
4.1 General .............................................................. 10
4.2 E1 and T1 Interface Card................................ 10
4.3 Maximum Cable Lengths ................................ 10
4.4 Link Programming ............................................ 11
5. FAULT DETECTION ................................................. 11
6. ABBREVIATIONS ..................................................... 11

List of Figures
Figure 1 Example of E1 Links through the OTN ...........................4
Figure 2 E1 (Multi)frame ............................................................4
Figure 3 AMI Coding and Violations ...........................................4
Figure 4 HDB3 Coding ................................................................5
Figure 5 T1 (Multi)frame ............................................................5
Figure 6 B8ZS Coding..................................................................5
Figure 7 E1 or T1 Link via OTN ....................................................5
Figure 8 E1-T1 Line Interface ......................................................6
Figure 9 OTN-Stuffing or Asynchronous Mapping .......................7
Figure 10 Irregular Transmit Clock..............................................7
Figure 11 Jitter Attenuator in Line Interface ...............................7
Figure 12 Internal Fault Handling ...............................................8
Figure 13 Dual Loopback in Line Interface ..................................8
Figure 14 E1 and T1 Interface Card: Front Panel .........................9
Figure 15 OTN Ring Coupling ......................................................9
Figure 16 RJ45 Interface Connector .......................................... 10
Figure 17 E1 and T1 Strappings ................................................ 10

List of Tables
Table 1 Reference documents ....................................................4
Table 2 Power Drain (typical) .....................................................9
Table 3 E1 Cable S30827-C40-Axx-y .......................................... 10
Table 4 T1 Cable S30827-C39-Axx-y .......................................... 10
Table 5 E1 Strappings ............................................................... 11
Table 6 T1 Strappings ............................................................... 11

AE-M240-E-5 Page 3 of 12
E1 and T1 Interface Cards Open Transport Network

1. INTRODUCTION 2. E1 AND T1 LINKS

1.1 General 2.1 General

This document describes the E1 (S30824-Q32-X) and T1 E1 and T1 links are used worldwide to implement high
(S30824-Q32-X100) interface cards that allow to set up, bandwidth synchronous links between two endpoints.
through the Open Transport Network (OTN), digital links These links typically transport voice and/or data using a
compliant with the international E1 or T1 standards. This standard TDM (Time Division Multiplex) technique.
way, links are set up between telephone exchanges (PBX),
network (LAN) routers and video codecs (Figure 1). The application of E1 or T1 is country related. T1 is primari-
ly used on the North American continent and Japan whe-
PBX PBX reas E1 is used in most other areas. Both carriers differ
Router with respect to the physical interface, the framing algorithm,
signaling and network management (alarms, measur-
Codec ing/reporting of the performance, etc.).
Cameras
2.1.1 E1
E OTN
1 x x x x x x xx xx xx xx
E1 is a 2.048 Mbps bi-directional (full duplex) link through
x x x x x x xx xx xx x

OTN node
x x x x x x xx
x x x x x x xx xx x
which the data is transported in a digital way in frames. One
Open Transport Network frame consists of 32 time slots (Figure 2). One time slot (0)
is used for framing and one time slot (16) for signaling. The
E OTN node bandwidth of one time slot is 64 kbps (8 bits). One frame
1
thus consists of 256 bits and lasts 125 µs. Typically 16
OTN node E
1 frames are packed together in one multiframe.

Codec Frame = 125 µs

Router
Monitors

PBX PBX
Bit slot
F S
Figure 1 Example of E1 Links through the OTN Time 0 1 2 16 31
slot

F = Framing
See ref. [1] for an overview of the node types in which the S = Signaling
cards can be installed.

Prior to describing the E1 and T1 interface cards (Chapter

3), Chapter 2 will explain about E1 and T1 links. Frame 1 16 1
Multiframe = 2 ms
Chapter 4 describes the installation of the cards in the node
as well as the cabling guidelines for connecting external Figure 2 E1 (Multi)frame
equipment.
The physical interface consists of four signals (Transmit
Chapter 5 provides some guidelines for tracing errors that Tip, Transmit Ring, Receive Tip and Receive Ring). An E1
may occur in the course of the installation. Tip-Ring pair can be either coax (75 ) or a balanced
Chapter 6 is an overview of the abbreviations used. twisted pair (120 ).

The data transmission through a pair is bipolar and AMI, i.e.

an impulse op the line corresponds with a logical "1" (mark)
1.2 References and a space with a logical "0". Each logical "1" is transmit-
ted with the inverse polarity of the previous logical "1"
Table 1 is an overview of the documents being referred to (Figure 3).
in this document, ‘&’ refers to the language code and ‘*’
refers to the document issue.

0 0 1 1 0 1 0 1 0 1 1
50%
Table 1 Reference documents
V
Ref. Number Title V
[1] AA-M205-&-* OTN Installation and Operation
Manual V = AMI violations
[2] AG-M330-&-* OTN Management System
(OMS), User Manual Figure 3 AMI Coding and Violations

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Open Transport Network E1 and T1 Interface Cards

As the E1 link has no separate clock transmission, the re- The physical interface appears in two basic formats: on-
ceiver will derive the clock from the incoming data stream. premise/short-haul (DSX-1) and off-premise/long-haul (DS-
A minimum density of logical ones is required in order to 1). DSX-1 and DS-1 differ as to protections and distances
guarantee a faultless clock recovery, which is achieved by to be bridged. DS-1 requires more protections and must be
replacing a number of successive zeros agreed upon with a capable of bridging greater distances since it concerns an
fixed recognizable code in which a number of ones are interface connecting to the "outside world".
present (recognition using AMI code violations). This coding
is called HDB3 (Figure 4). Another but less popular possi- A T1 Tip-Ring pair is a balanced twisted pair (100 ). Just
bility is ADI. as with E1, data transmission is bipolar and AMI (see Fig-
ure 3) and extra coding is applied. B8ZS (Figure 6) is most
popular and different from HDB3. Other possibilities are
JB7, ZBTSI and time slot inversion.
0000
Just as with E1, there are different framing algorithms for
replace T1: Superframe (SF or D4) and Extended Superframe
4 zeros
with (ESF). RBS is applied for signaling.

B0 0V

B is 0 or 1. The choice is such that the number of ones 00000000

between two successive violations (V) is odd
replace
8 zeros
Figure 4 HDB3 Coding by
The algorithms used for (multi)framing are: basic framing, 0 0 0V1 0V1
CAS and CRC4 (CCS). The signaling algorithm is CAS. A
description of this algorithm is beyond the scope of this Figure 6 B8ZS Coding
document because the OTN is transparent to the complete
2.2 OTN and E1/T1
frames and does not participate in framing and signaling.

2.1.2 T1 The original E1 or T1 copper link between two users is in-

terrupted and restored via the optical ring of the OTN
T1 is a 1.544 Mbps bi-directional (full duplex) link through (Figure 7). Consequently, an E1 or T1 interface card inter-
which the data is transported in a digital way in frames. One connects an end user and the OTN. Separate E1 and T1
frame consists of 24 time slots + 1 bit (Figure 5). The extra interfaces have been developed because of the differences
bit is used for framing. The bandwidth of one time slot is 64 between E1 and T1. Each interface can connect to maxi-
kbps (8 bits). One frame thus consists of 193 bits and lasts mum four E1 or four T1 users. The four circuits work inde-
125 µs. Depending of the framing algorithm applied either pendently of one another. The interfaces that are back to
12 or 24 frames are packed together in one multiframe. back via the OTN are identical.
Signaling bits are transported in the Least Significant Bit of
the time slots in each multiframe agreed upon (in-band). The E1 and T1 links are synchronous among themselves
but asynchronous with respect to the OTN. Indeed, OTN
The physical interface consists of four signals (Transmit frames travel at their own frequency from node to node.
Tip, Transmit Ring, Receive Tip and Receive Ring. OTN stuffing (asynchronous mapping) is applied to main-
tain the synchronous link through the OTN (§ 3).


Frame = 125 µs

F PBX PBX
Bit
slot Master Slave
0 23
Time
slot
Node Node
PBX Optical PBX
1 12 1 ring
Frame
Multiframe (SF)
Master Slave
or
1 Multiframe (ESF) 24 1 E1 or T1 interface

Figure 7 E1 or T1 Link via OTN

Figure 5 T1 (Multi)frame

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E1 and T1 Interface Cards Open Transport Network

The E1 and T1 interfaces are transparent to the E1 and T1 One interface is connected to the master. The second inter-
frames and consequently have no framer but only a line face in another OTN node is connected to the slave (Figure
interface. The different framing algorithms possible and the 7).
signaling (§ 2.1) have no impact on the transport mechan-
ism through the OTN.

List of the main characteristics of these interfaces: 3.1.1 From End User to OTN

a. Separate interfaces for E1 and T1 (on-premise/short- The frame transmitted by the PBX master is received by a
haul DSX-1). line interface (Figure 8). A commercial line chip
(LXT332QE) decodes the incoming bipolar bit pattern and
b. Four independent E1 or T1 circuits per card. generates a unipolar (NRZ), serial, digital data stream
(RDATA). The "Timing & Data Recovery" block integrated
c. OTN-stuffing (asynchronous mapping) to ”synchronize" in the line interface recovers the system clock (RCLK) from
the OTN to the E1 or T1 link. the incoming data stream (2.048 MHz (E1)/1.544 MHz (T1)
and may generate Loss-Of-Signal (§3.3 Status bits).
d. Transparent to the frames i.e. independent of framing
algorithms and signaling. The bit stream (RDATA) from the line chip is written into an
elastic buffer with the recovered system clock (RCLK).
e. Bit rate = 2,048 Mbps (E1) and 1,544 Mbps (T1).
Reading the buffer will only be started if, after startup, a
f. Full duplex 4 wire interface (one transmit pair and one hardware set stuffing degree has been reached (Figure 9a).
receive pair). The buffer read frequency is derived from the reserved
bandwidth in the OTN frame. As the frame traveling fre-
g. Balanced twisted pairs of 120 (E1) and 100 (T1). quency through the OTN is asynchronous versus the re-
covered system clock, the buffer will want to run empty
h. AMI coded digital transmission with HDB3 (E1) and (OTN is faster) or overflow (OTN is slower).
B8ZS (T1).
In order to avoid this two bits of the programmed bandwidth
The default (OMS) setting for the line coding (HDB3 for are indicated in the OTN frame as stuffing bits. Stuffing is
E1 and B8ZS for T1) can be switched off per circuit. In triggered by measuring the level in the elastic buffer and by
that case, we fall back on pure AMI, but too many suc- comparing with a fixed underflow (min.) and overflow
cessive zeros in the data stream must be avoided in (max.).
another way.
As long as the buffer does not reach its overflow 63 (E1)/47
i. Instead of generating AIS in the case of fault situations (T1) bits are transported in the OTN frame (stuffing bits
the transmitter on the remote interface is brought in tri- carry no data). This number of bits represents a bandwidth
state resulting in e.g. a Loss Of Signal alarm with the below the minimum bandwidth of the link so that the num-
connected, downstream user. The interface is transpa- ber of bits in the elastic buffer will increase (Figure 9b).
rent to AIS, however.
From the moment the overflow is reached 65 (E1)/49 (T1)
3. CARD DESCRIPTION bits will be transported in the OTN frame. Both stuffing bits
now carry data. The number of bits in the OTN frame re-
3.1 Operation presents a bandwidth that is higher than the maximum
bandwidth of the link so that the number of bits in the elas-
Via two identical interfaces links are set up between two
tic buffer will decrease (Figure 9c).
end points (e.g. trunk between two exchanges) through the
optical ring. In practice, one of these end points is the link The cycle is repeated when reaching the underflow, i.e. the
master (determines the clock) and synchronizes the other content of the elastic buffer moves between an underflow
end point (slave) to the master (slave recovers the clock and an overflow.
with a PLL).

Protec- 2,048 MHz (E1)/1,544 MHz (T1)

tion OSC BPV
LOS
Double
LXT332QE loopback B8ZS/HDB3 RDATA
Peak Timing & Data decoder
Rx 1 2 detector Recovery + RCLK
LOS Proces.
Transmlitter Jitter- B8ZS/HDB3 TDATA
Compen- Line coder
Tx 2 1 sator repeater
Timing & attenuator
TCLK
Control (DPLL + 32-bit
fifo)
RJ45 Transfo
screened
TXZ Dip switch OMS
OMS

Figure 8 E1-T1 Line Interface

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Open Transport Network E1 and T1 Interface Cards

E1 T1
From line interface NOM From line interface NOM

2.048 Mbps 1.544 Mbps

a. a.
MAX. MAX.
63 Bits in OTN frame 47 Bits in OTN frame
2.048 Mbps 2.016 Mbps 1.544 Mbps 1.504 Mbps

b. b.
MIN MIN
65 Bits in OTN frame 49 Bits in OTN frame
2.048 Mbps 2.080 Mbps 1.544 Mbps 1.568 Mbps

c. c.

Figure 9 OTN-Stuffing or Asynchronous Mapping

Dn-2 Dn-1 Dn V1 S1 V2 S2 R1 R2 D1 D2 Dn-2

V1 defines V2 defines
pulse S1 pulse S2
LEGEND:
D = DATA V = VALID R = REMOTE S = STUFFING

Figure 10 Irregular Transmit Clock

In order to indicate whether or not a stuffing bit contains Digi-

data, the OTN frame is provided with two extra bits that we tal
call "valids" (one valid per stuffing bit). Irregular PLL
TCLK
transmit clock
3.1.2 From OTN to End User EB
1 0 1 1 0 1
32-bit
Valids, stuffing and data bits are received by the remote TDATA
interface. All data bits are written into an elastic buffer upon
reception. Stuffing bits are only written into this buffer pro- Figure 11 Jitter Attenuator in Line Interface
vided they carry data. This is indicated by the received va-
3.2 Bandwidth Allocation
lids preceding the stuffing bits, i.e. the net data stream
equals the data stream from the line interface on the re- The OMS automatically assigns transmission channels to
mote interface. An impulse is made for each bit of this net each E1 or T1 link. Each bit of an OTN frame corresponds
data stream, received from the OTN. This pulse train is the with a 32 kbps data rate.
transmit clock which together with the associated bits is
offered to the line chip. The transmit clock is an irregular In the case of E1/T1, data is transported through the OTN
clock (a lot of jitter) because (Figure 10): in OTN channel groups (groups of 3 bits).
a. The data bits in the OTN frame of this link are not en- 3.2.1 E1
tirely equidistant.
An E1 frame represents 2.048 Mbps. Nominally 64 bits are
b. No clock pulses are generated for stuffing bits not car- required per OTN frame (64 x 32 kbps = 2.048 Mbps) in
rying any data and remote bits. (See § 3.2). order for these frames to be transported. However, we pro-
vide one extra bit for stuffing when the E1 link is faster than
A jitter attenuator, integrated in the line chip, consists of a the OTN (e.g. due to clock offsets).
digital PLL (DPLL) combined with a 32-bit deep elastic buf-
fer (Figure 11), in which the data bits (TDATA) with the irre- In other words the maximum capacity is 65 bits or 2,080
gular clock (TCLK) are written. From the irregular clock, the Mbps (two of these bits are stuffing bits). As shown in §
digital PLL generates a regular clock that is used to read 3.1.1 two valids are associated with the stuffing bits, the
the elastic buffer producing a bit stream with hardly any subtotal then being 67 bits.
jitter and without losing any bits.
Finally two bits ("remote" bits) are used to exchange infor-
The serial, unipolar data stream is coded by the line inter- mation between both interfaces (§ 3.3 Control bits), such
face and converted into a bipolar data stream. as:
The other direction of the link works in an identical way, but a. Reporting local fault conditions to the remote interface.
from the received data stream the connected slave PBX b. Detecting the presence of the remote interface.
recovers a clock that is used for transmitting frames to the
interface. Consequently the OTN bandwidth per E1 link is 69 bits (23
channel groups) or 2.208 Mbps.
This way, the synchronous master-slave link via the OTN is
guaranteed. 3.2.2 T1

A T1 frame represents 1.544 Mbps. Nominally 48.25 bits

are required per OTN frame (48.25 x 32 kbps = 1.544
Mbps) in order to transport these frames. We provide more

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E1 and T1 Interface Cards Open Transport Network

bandwidth to allow stuffing when the T1 link is faster than f. 1 bit indicating the card initialization status. The card
the OTN (e.g. due to clock offsets). contains a logical component (FLEX) which must be in-
itialized from a PROM prior to being operational. The
In other words the maximum capacity is 49 bits or 1.568 initialization always occurs when the interface card is
Mbps (two of these bits are stuffing bits). Exactly like in the reset.
case of E1 we have two valids and two remote bits here,
i.e. a subtotal of 53. When the switch (front panel) is ON, the OMS checks
this bit. If the initialization fails, then the card is deficient
Since the OTN data transport occurs in channel groups (per and no communication is possible via this card.
3 bits) one bit is not used.
3.3.2 Control Bits
Consequently the OTN bandwidth per T1 link amounts to
54 bits (18 channel groups) of 1.728 Mbps. a. 1 bit to reset the interface card. Using this bit the net-
work administrator can deny card access to the optical
3.3 Status and Control Data ring (does not receive bandwidth). The logical compo-
nent (FLEX) is initialized with a card reset. If the reset
In order to allow the interface card to be monitored and the
remains, the logical component will start up, however.
OMS to be controlled, the card provides a number of status
and control bits that are accessible from the OMS. b. Per circuit 1 bit that switches the HDB3(E1) or
B8ZS(T1) coding/decoding in the line interface on/off
3.3.1 Status Bits
from the OMS.
a. 1 bit indicating the position of the switch. When the
c. Per circuit, 1 bit used in the protocol to detect the pres-
switch is OFF the DRA-II(C) or the (B)ORA card pro-
ence or absence of the remote interface. Two extra bits
vides no bandwidth for the interface card and no com-
have been programmed in the OTN frame (remote
munication will be possible via this card.
bits). From interface A towards interface B, interface A
b. 7 bits for card identification. These bits allow the OMS writes a logical "1" in the first remote bit, which is in-
to know which cards are installed in the node and verted by interface B and sent back to interface A. In-
which card slots are no longer available to other inter- terface A then receives a logical "0" in this bit position
face cards. but only if interface B is present. If interface B is absent
then interface A reads a logical "1" (Figure 12).
c. Per circuit 1 bit indicates whether or not the input signal
is okay (LOS). The alarm is active if the receiver in the Interface Interface
A B e.g.
line interface detects 175 15 successive zeros in the
“1" - BPV alarm
incoming bit stream. The alarm is suppressed if a den- Transport via special bit in
Due - LOS alarm
sity of 12.5 % of "ones" (4 ones in a 32-bit window) with to - fifo over-
OTN frame (RMT1)
no more than 15 successive zeros is found. fault or underflow
“0" - no interface
d. Per circuit 1 bit indicating whether or not the receiver
Due “1"
detects too many bipolar violations (BPV). The thre- Transport via special bit in
to
shold values with a test pattern consisting of all ones fault OTN frame (RMT2)
and AMI coded are as follows: “0”

-3
- E1: activation as of 1 BPV/1356 bits (0.74.10 ). Figure 12 Internal Fault Handling
-4
Deactivation as of 1 BPV/10854 bits (0.9.10 ).
-3 The same principle applies from interface B towards in-
- T1: activation as of 1 BPV/1023 bits (0.98 10 ). terface A, but in the second remote bit. Interface B thus
-4
Deactivation as of 1 BPV/ 8183 bits (1.22.10 ). receives a logical "0" in this bit position, only if interface
A is present. If interface A is absent then interface B
e. Per circuit 1 bit indicating whether or not the line driver reads a logical "1" (Figure 12).
in the line interface is in tri-state. The line driver is
brought in tri-state if: The control bit defines which interface of the link is A
and which interface is B. For this purpose, when setting
- Loss Of Signal is detected on the remote interface. up the link the control bit on interface A is made "0"
- The BPV alarm is activated on the remote interface. whereas on interface B it is made "1".
- No data transport is possible through the OTN
because: The network administrator cannot control this control bit
- The OTN bandwidth is not the expected but it is automatically written when setting up a link be-
bandwidth. tween two interface cards.
- The node is out of sync.
The remote bits are also used to inform the remote in-
- The remote interface is absent.
terface of fault conditions that occur on an interface.
- Overflow/underflow of elastic buffer
This can easily be done by not inverting the remote bit
(line interface  OTN) on remote interface.
in the case of a fault condition
- Interface is not operational because:
- The switch on the front panel is OFF. d. Per circuit 1 bit to force a loopback. This loopback is
- The OMS resets the interface via a control bit. both of the "local" and "remote" type and occurs inside
- The backplane reset signal is active. the line chip (Figure 13).
- The backplane OFS signal is absent.
- The backplane HIZ signal is active. Interface
OTN
Interface
- The 5 V voltage monitor on the interface forces A B
Local Remote
a reset. Loopback Loopback

Figure 13 Dual Loopback in Line Interface

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Open Transport Network E1 and T1 Interface Cards

- local: loopback of digital inputs from line interface - -20 °C to +70 °C

to digital outputs (through internal jitter attenuator - - 4 °F to +158 °F
and HDB3/B8ZS coder/decoder).
c. Relative humidity (non-condensing)
- remote: loopback of recovered clock and data, - Operation: 20 % through 80 % at 25 °C (+77 °F)
from the incoming data stream to the analog (node surrounding).
outputs. - Storage and shipment: 20 % through 95 %.

d. Power drain
3.4 LED Indications The values in Table 2 apply when all circuits receive
Per circuit two red LEDs are provided on the front panel: and transmit an all ones test pattern (AIS).
LOS and TXZ (Figure 14). Table 2 Power Drain (typical)
a. LOS lights if the receiver detects Loss Of Signal in the
line interface (§ 3.3). Power drain (mA) +5 V +12 V -12 V -48 V
E1 320 - - -
b. TXZ lights if the line driver in the line interface is tri-
state (§ 3.3). T1 320 - - -

The LED will light and then go dark repetitively in the case
of loopback. The information as to whether or not the line e. Bit rate
driver is tri-state can then be read on the OMS interface - E1: 2.048 Mbps 50 ppm ( 103 bps)
management screen. - T1: 1.544 Mbps 32 ppm ( 50 bps).
130 ppm ( 200 bps) is possible with
old installations.
E1

T1

ON ON
f. Code
OFF OFF

LOS1 TXZ1 LOS1 TXZ1 - E1: AMI (50 %) or HDB3 (default).

- T1: AMI (50 %) or B8ZS (default).
1 1
8 8 g. Weight
- E1: approx. 410 g.
LOS2 TXZ2 LOS2 TXZ2
- T1: approx. 410 g.
1 1
h. MTBF at 25 °C (+77 °F)
8 8
- E1: 37 years (3107 fits).
- T1: 37 years (3107 fits).
LOS3 TXZ3 LOS3 TXZ3

i. Electromagnetic compatibility
1 1
8 8 - Emission: EN 61000-6-3 and EN 61000-6-4, EN
55022 (Class B);
LOS4 TXZ4 LOS4 TXZ4
- Immunity: EN 61000-6-1 and EN 61000-6-2.

1 1 3.6 Applications
8 8
Some examples of E1 or T1 links through the Open Trans-
port Network.

a. PBX Network

Figure 14 E1 and T1 Interface Card: Front Panel In order to avoid bit slips in the PBX, the PBXs be-
tween which trunks run through the OTN must be syn-
3.5 Specifications chronized.

a. In compliance with the following standards provided b. OTN Ring Coupling

they apply to the interface:
Figure 15 shows a link between 2 PBXs connected to
- E1: ANSI T1.102. different optical rings. Both rings must not be synchro-
ITU-T rec's. G.703 and G.823. nized among themselves contrary to the PBXs, which
- T1: ANSI T1.102, T1.403, T1.408. must be in order to avoid bit slips in the PBX.
ITU-T rec's. G.703,G.824 & I.431.
Bellcore 000499.
* *
b. Temperature (node surrounding)
OTN-1 OTN-2
- Operation: * * * *
- -20 °C to +55 °C
- - 4 °F to +131 °F * *

PBX1 PBX2
- Start-up:
- -10 °C to +55 °C
- +14 °F to +131 °F * E1 or T1 interface

- Storage and shipping Figure 15 OTN Ring Coupling

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E1 and T1 Interface Cards Open Transport Network

c. Network Routers and Codecs - TX is the interface transmitter. RX is the

interface receiver.
Even though basically PBXs are concerned between - Tip-Ring polarity is not important (AMI).
which E1 or T1 trunks are set up, there are other types
of users who can communicate via an E1 or T1 link
The type of card specifies the installation procedure to be
(Figure 1).
followed.
Some examples: 4.2 E1 and T1 Interface Card
- Network routers or LAN routers.
1. These cards must be strapped prior to their insertion
- Video codecs to which e.g. cameras are
into the node. See Figure 17, Table 5 and Table 6.
connected.
2. Insert the card into the node with the switch OFF.
4. INSTALLATION GUIDELINES Tighten the mounting screws. Check whether the LEDs
"LOS" and "TXZ" of all circuits light.
4.1 General
3. Screened cables can be used for connecting the
Figure 14 shows the front panel of the E1 and T1 interface
interface card to the periphery. One cable end is
cards. Table 3 and Table 4 show the pin numbers, signals
terminated by a screened, male RJ45 connector for
and the color code of the cables. The color codes are ex-
direct connection to the screened, female RJ45
plained in Ref [1]. Figure 16 shows the RJ45 interface con-
connector on the interface card. The other end consists
nector.
of loose wire pairs to connect the correct connector to.
Table 3 E1 Cable S30827-C40-Axx-y This end is connected to the user.

Color Signal Name Pin number The following cables are available: S30827-C40-Axx-y
OG Rx Ring 1 (120 ) for E1 and S30827-C39-Axx-y (100 ) for T1.
(Axx refers to the cable length, e.g. A50 is 5 m). Also
WH-OG Rx Tip 2 refer to ref. [1].
not used 3
BU Tx Ring 4 4. Put the switch on the card to ON.
WH-BU Tx Tip 5
4.3 Maximum Cable Lengths
not used 6
not used 7 The maximum line attenuation allowed of 6 dB at 1024 kHz
with a resistive termination of 120 defines the maximum
not used 8
cable length for the E1 interface card. It is about 300 m for
the recommended cable type.
Table 4 T1 Cable S30827-C39-Axx-y
As for T1 the equalizer of the transmitter in the line inter-
Color Signal Name Pin Number face compensates cable distances up to +/- 200 m (655 ft).
WH-GN Rx Ring 1
GN Rx Tip 2
WH-OG not used 3 ON ESD

BU Tx Ring 4 OFF
WH-BU Tx Tip 5
OG not used 6
WH-BN not used 7
L1-0
BN not used 8 L1-1
L1-2

L2-0
Pin Description L2-1
L2-2
1 Rx Ring
2 Rx Tip L3-0
3 Node housing L3-1
1 8 4 Tx Ring L3-2
5 Tx Tip
L4-0
6 Node housing L4-1
7 Node housing L4-2
8 Node housing

Figure 16 RJ45 Interface Connector

NOTE: The unused wire pairs in the cable (3-6 and 7-8)
are connected to the housing of the OTN node
through the interface card connector.
Figure 17 E1 and T1 Strappings

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Open Transport Network E1 and T1 Interface Cards

Table 5 E1 Strappings

Strapping Setting Explanation

Lx-0 Lx-1 Lx-2 OPEN CLOSED CLOSED Unique setting for E1
(x = circuit 1 ... 4) (to be set for all circuits x = 1 ... 4)

Table 6 T1 Strappings

Strapping Setting Cable Length

Lx-0 Lx-1 Lx-2 OPEN OPEN CLOSED 0-133 ft
(x = circuit 1 ... 4) CLOSED CLOSED OPEN 133-266 ft
OPEN CLOSED OPEN 266-399 ft
CLOSED OPEN OPEN 399-533 ft
OPEN OPEN OPEN 533-655 ft

4.4 Link Programming

- Check whether LED "LOS" on the remote interface
1. Program the links. The following data is required for is dark.
this purpose:
- Check with the OMS whether the remote interface
- The addresses of the nodes in which the E1 or T1 has been included in the link.
cards are installed.
- Check with the OMS whether any code violation
- The positions of these interface cards in the alarm has been generated on the remote interface.
respective nodes. If yes, then check the interface setting AMI or
HDB3/B8ZS and the code applied by the
- The ports of the interface cards to which the users connected user.
are connected.

See ref. [2] (OMS, User Manual). - Replace this or the remote interface card. Indeed,
LED "TXZ" may be caused by errors occurring on
both the remote and the local interface.
2. LED "LOS" goes dark when the user is connected to
the interface port:
6. ABBREVIATIONS
3. LED "TXZ" goes dark after the following conditions ADI Alternate Digit Inversion
have been complied with:
- Both end users connected to the interface ports. AIS Alarm Indication Signal
- Allocation of bandwidth from the OMS. AMI (50%) Alternate Mark Inversion
- Correct interface settings from the OMS (no (50% = a ”1” lasts a half bit period)
loopback, AMI or HDB3/B8ZS).
B8ZS Bipolar with 8-Zero Substitution (AMI code
5. FAULT DETECTION with violations applied in T1)

This Chapter describes a number of faults, which may oc- (B)ORA (Broadband) Optical Ring Adapter
cur upon card installation. = OTN system card
BPV BiPolaire Violatie
1. LED LOS does not go dark after the user has been
connected: CAS Channel Associated Signaling
CCS Common Channel Signaling
- Check the user/interface link.
- Check whether the user transmits data. CRC Cyclic Redundancy Check
- Check whether the data is E1 or T1 compliant
DRA-II(C) Dual Ring Adapter, version II (clock input)
(e.g. bit rate, pulse shape).
- Replace the interface card. = OTN-systeemkaart
- Replace the connected user. DS-1 Digital Signal Level 1 - off-premise T1
standard interface
2. LED "TXZ" does not go dark after connecting both end
users: DSX-1 Digital Crossconnect Signal Level 1 - on-
premise T1 standard interface
- Check whether the card/the circuit has been E1 2.048 Mbps interface
programmed in a link or has been inactivated
through the OMS (see ref. [2] (OMS, User Manual). ESF Extended Superframe

AE-M240-E-5 Page 11 of 12
E1 and T1 Interface Cards Open Transport Network

FLEX Flexible Logic Element MatriX SRAM

architecture (Altera brand programmable
component)
HDB3 High Density Bipolar of order 3 (AMI code
with violations applied in E1)
JB7 Jammed-Bit Seven
KBPS KiloBits Per Second
LOS Loss Of Signal
MTBF Mean Time Between Failure
NRZ Non Return to Zero
OFS OTN Frame Sync
OMS OTN Management System
OTN Open Transport Network
PBX Private Branch Exchange
PLL Phase Locked Loop
PPM Parts Per Million
PROM Programmable Read Only Memory
RBS Robbed-bit Signaling
RX Receiver
S.V.P.R. System Version Point Release
SF Superframe
T1 1.544 Mbps interface used in North America
and Japan
TDM Time Division Multiplex
TX Transmitter
TXZ Transmitter High Impedance

Page 12 of 12 AE-M240-E-5